Bode Stability Analysis For Single Wall Carbon Nanotube Interconnects Used in 3D VLSI Circuits

World Academy of Science, Engineering and Technology
Vol:5 2011-05-24
Bode Stability Analysis for Single Wall Carbon

Nanotube Interconnects Used in
3D-VLSI Circuits
Saeed H. Nasiri, Rahim Faez, Bita Davoodi, and Maryam Farrokhi
l
International Science Index Vol:5, No:5, 2011 waset.org/Publication/8373
AbstractBode stability analysis based on transmission line

modeling (TLM) for single wall carbon nanotube (SWCNT)
interconnects used in 3D-VLSI circuits is investigated for the first
time. In this analysis, the dependence of the degree of relative
stability for SWCNT interconnects on the geometry of each tube has
been acquired. It is shown that, increasing the length and diameter of
each tube, SWCNT interconnects become more stable.
KeywordsBode stability criterion, Interconnects, Interlayer

via, Single wall carbon nanotubes, Transmission line method, Time
domain analysis
I. BACKGROUND
S process technology continues to scale downward,

traditional copper interconnects in high-performance
very large scale integration (VLSI) systems will suffer from
serious problems such as restricted max current density, low
electrical and thermal conductivity and short mean free path
[1], [2]. Over the last decade we have witnessed tremendous
advances in the characterization of structure and electrical
properties of carbon nanotubes (CNTs) [3]. Because of high
mechanical and thermal stability, high thermal conductivity
and large current carrying capacity, CNTs have aroused a lot
of research interest in their applicability as VLSI interconnects
of the future. Bundles of metallic single-walled CNTs
(SWCNTs) with electron mean free paths of the order of a
micron are the most suitable candidates for interconnects [4].
In addition, this innovative material shows significant
properties in terms of thermal dissipation and reliability, so it
is proposed to realize both horizontal and vertical
interconnections at chip and package level for future VLSI
ultrascaled technologies. The fabrication technology for these
bundles is well-assessed for vertical vias where high density
bundles with low contact resistance have been realized [5].
S. H. Nasiri is with the Department of Electrical Engineering, Qazvin,

Islamic Azad University, Qazvin 3419915195, Iran. (Corresponding author; email: s.nasiri@qiau.ac.ir).
R. Faez is with the Electrical Engineering Department, Sharif University of
Technology, Tehran, Iran. (e-mail: faez@sharif.edu).
B. Davoodi is with the Department of Electrical Engineering, Qazvin,
Islamic Azad University, Qazvin 3419915195, Iran. (e-mail:
b.davoodi@qiau.ac.ir).
M. Farrokhi is with the Department of Electrical Engineering, Qazvin,
Islamic Azad University, Qazvin 3419915195, Iran. (e-mail:
m.farrokhi@qiau.ac.ir).
International Scholarly and Scientific Research & Innovation 5(5) 2011
Fig. 1 RLC schematic of transmission line circuit model for a driverSWCNT interconnect-load configuration
Fig. 1 illustrates a schematic representation of a typical

RLC model for a SWCNT bundle interconnect made of N
SWCNTs of the same lengths l and diameters D. In this
figure, RC, RQ, and RS represent the equivalent resistances
introduced by the imperfect contacts, the quantum effect, and
the carriers scatterings, respectively. One can approximate
the quantum contact resistance as RQh{2e2NchN}1 [6],
wherein h, e, and Nch are the Planks constant, electron charge,
and number of conducting channels in each SWCNT. When
the length of each SWCNT is greater than its carriers mean
free path (), the equivalent distributed ohmic resistance (per
unit length) introduced by carriers scatterings with defects,
substrate-induced disorders, and phonons can be written as
RS RQ / [6]. Also shown in Fig. 1; CE 2/(Nln(y/D)) [7]
in which is the dielectric permittivity, y is distance of
SWCNT bundle from ground plane, and D is diameter of each
tube. CQ{RQvF}1 is the per unit length values of the
equivalent capacitances induced by the electrostatic and
quantum effects, respectively, in which vF is the Fermi
velocity in graphite.
Since the separation between any two SWCNT is much
smaller than y, the effect of the electrostatic capacitances
between any two SWCNT in the bundle is negligible.
Furthermore, LK=RQ / vF and LM ln(y/D)/(2N) [7]
represent the per unit length values of the kinetic and the
magnetic inductances, in presence of the ground plane,
wherein is the CNT permeability. In a practical case
LM << LK [6].
In order to obtain the number of conducting channels in
each SWCNT, one can add up contributions from all electrons
in all nC conduction sub-bands and all holes in all nV valence
sub-bands [8]:
N ch =
[e
nC
i =1
( Ei EF ) / kT
] + [e
+1
nV
i =1
( Ei + EF ) / kT
+1
(1)
where i(=1, 2, 3, ) is a positive integer, EF, k, and T are the
492

Vol:5 2011-05-24
Fermi energy, the Boltzmann constant, and temperature,

respectively, and Ei represents the quantized energy that
corresponds to the i-th conduction or valence subband. This
quantization is due to diameter confinement, introduced by the
tubes finite diameter.
The system studied in this research is shown in Fig2. Two
horizontal tracts have been considered on two layers,
connected together by a via, where both top and bottom layers
as well as via are CNT bundles.
Despite valuable properties there are several prospects to be
investigated for practical use of carbon nanotube
interconnects. Following this stream, here, the stability
analysis of on-chip CNT interconnects has been studied,
considering both horizontal traces and vertical vias. In this
paper, Bode analysis has been used as a criterion to study
relative stability by changing the geometry of CNTs, and
MATLAB software for approaching the stability issue.
In Bode' plots, magnitude (in db) and phase are plotted
against frequency and we can see large ranges of gain because
the db scale presents information differently. The gain margin
(GM) and phase margin (PM) provide measures of how close
a system is to a stability limit. Phase margin is just the
difference between -180o and the actual phase angle of the
frequency response function, measured at the frequency where
the magnitude of the frequency response function, is equal to
one (0 db). Gain margin is just the amount of gain that we can
add to move the zero db crossing to occur at the same
frequency as the -180o crossing. The system becomes more
stable if the GM and PM increase [9].
HH d
BT
A
Ttotal = T
CT DT
0 1 Rex
1 Rout 1
0 1 sC
out 1 0 1
1 + ( RS dx + Ldxs ) sCdx ( RS dx + Ldxs )
sCdx
1
lvia
y
Ground Plane
(b)
(a)
Horizontal bundle
Vertical
bundle
( via )
Horizontal bundle
(c)
Fig. 2 Schematic of a) 3D VLSI structure; b) cross-section of the
bundles; c) complete schematic
Where Rex=(RC+RQ)/2, L=LK+LM ,C=CECQ/(CE+CQ), dx=l/NB

,and s=j is the complex frequency. We obtain the linear
parametric equivalent for the transfer function of as:
H ( s) =
Vo ( s )
1
=
Vi ( s ) AT + sC L BT
(3)
Since a combination of the two horizontal and a vertical

structures is used here, the formula in (3), will be devised as:
II. MATRIX FORMULATION

In Fig. 1, a SWCNT bundle interconnect is shown with the
length l that is represented by a series of distributed
resistances (RS), inductances (L), and capacitances (C) (all in
per length units) Such interconnect is applied to both
horizontal and vertical structures and these are driven by a
driver with an output resistance Rout and an output
capacitance Cout. The SWCNT bundle interconnects is also
connected to a load of capacitance CL.
In order to calculate the input-output transfer function of
the configuration in Fig. 1, total transmission parameter
matrix should be derived. For this purpose ABCD
transmission parameter matrix are used for a uniform RLC
transmission line of length l that contains NB distributed
blocks. Accordingly, total ABCD transmission parameter
matrix is defined as:
H( s ) =
Vo1 ( s ) Vo 2 ( s ) Vo ( s )
Vi ( s ) Vo1 ( s ) Vo 2 ( s )
(4)
III. BODE STABILITY ANALYSIS

By varying the nanotubes dimensions, (2 m l 6 m and
3 nmD7 nm) and generating various Bode diagrams, we
have studied the effect of SWCNT bundle geometry on the
relative stability of the configuration given in Fig. 2(c). All
geometrical and physical parameters are according to the 22nm technology node, extracted from ITRS2009 [2]. Both
horizontal local interconnects are assumed to have ideal
contact (i.e., RC=0) [2]. The driver size is set to be 100 times
the minimum sized gate for the 22-nm technology node, given
in [2]. The bundle width is 22 nm and its thickness is 44 nm.
The values of N are 83, 32 and 15 for D=3, 5 and 7
respectively. The space between two adjacent CNTs is
assumed as 0.34 nm and EF as 0.3 eV. All individual
SWCNTs are assumed to be metallic. In this analysis, we have
(2)
NB
1 Rex
0 1
assumed the parameters in via as l=80 nm, RC=21.22 , CL=0,
Cout=0, in top tract as CL =0, Cout=0.049e-15 fF, and in bottom
493

Vol:5 2011-05-24
0
-500
-1000
0
-500
-1000
-1500
0
-1500
0
Phase (deg)
500
D = 3 nm NB=3
-360
l = 2 m
l = 4 m
l = 6 m
-720
-1080
-1440
Phase (deg)
Magnitude (dB)
500
l = 2 m NB=3
-360
-720
D = 3 nm
D = 5 nm
D = 7 nm
-1080
-1440
-1800
10
-1800
10
damping and the system tend to be more stable.

Bode diagrams for D=3, 5, and 7 nm is illustrated in Fig. 5.
The length of each tube is assumed to be 2 m. As shown in
Magnitude (dB)
tract as CL=0.14e-15 fF, Cout=0.

Bode diagrams are shown in Fig. 3 for the configuration of
Fig. 2(c) regarding l=2, 4, and 6 m. The diameter of each
tube is assumed to be 3 nm. As shown in Fig. 3, by increasing
12
14
10
Frequency (rad/sec)
10
16
Fig. 3 The Bode diagrams for driver-SWCNT bundle interconnectload configuration of Fig. 2(c) for D=3 nm and 2 m l6 m
Fig. 4. (a) Decreasing the absolute values of gain margins versus

frequency with D=3nm and 2 m l6 m; (b) Decreasing the
absolute values of phase margins versus frequency
the length of CNTs, the gain margin and phase margin of

interconnect increase; the details are depicted in Figs. 4(a) and
4(b). Thus, by increasing the length of CNT bundle, the
system becomes more stable. This is because by increasing the
length of tubes, the equivalence impedance of the interconnect
increases so that the step response of the system go to more
12
14
10
Frequency (rad/sec)
10
16
Fig. 5 The Bode diagrams for driver-SWCNT bundle interconnectload configuration of Fig. 2(c) for l=2 m and 3 nmD7 nm
Fig. 6 (a) Decreasing the absolute values of gain margins versus

frequency with l=2 m and 3 nmD7 nm; (b) Decreasing the
absolute values of phase margins versus frequency
Fig. 5, gain margin and phase margin of interconnect

increase as the diameter of each tube increases; therefore, the
system becomes more stable. This is because by increasing the
tube diameters the bundle becomes less dense and its
conductivity decreases so that its step response tends to be
more damping. The relevant details are depicted in Figs. 6(a)
and 6(b).
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Vol:5 2011-05-24
The present general analysis whose transfer function is of the

order of 20, provides much more accurate and realistic
numerical results than those that could be obtained by similar
analyses presented in [10] with order of four and [11] with the
order of six both for SWCNT-bundle interconnects, and in
[12] with the order of four for multi layer graphene
nanoribbon (MLGNR) interconnects.
IV. CONCLUSION
In the analysis presented in this paper relative stability
analysis for single wall carbon nanotube interconnects used in
3D-VLSI circuits is investigated. Using transmission line
modeling along with Bode stability diagrams, we have shown
that with increasing the length or diameter of each tube, the
relative stability increases and hence the system will be more
stable. This is because any increase in the parameters will
cause switching delay; therefore, the systems step response
tends to damp faster and consequently the system will be more
stable.
research interests include Graphene nanoribbon (GNR) and carbon nanotube

(CNT) interconnects.
Dr. Rahim Faez received B.S. degree from Sharif University of Technology
in 1977 and the M.S. and Ph.D. degrees from UCLA in 1979 and 1985
respectively. Then he joined Sharif University of Technology and currently he
is Associate professor in there. His research interests include design and
simulation of advanced semiconductor nano and quantum devices.
Miss Bita Davoodi is currently working toward the M.S. Department of
Electrical and Computer Engineering, Islamic Azad University of Qazvin.
Miss Maryam Farrokhi is currently working toward the M.S. Department of
Electrical and Computer Engineering, Islamic Azad University of Qazvin.
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Saeed Haji Nasiri was born in Tehran, Iran, in 1981. He received the B.S.
and M.S. degrees in Electrical Engineering from the Qazvin Branch, Islamic
Azad University, Qazvin, Iran, in 2004 and the Central Tehran Branch,
Islamic Azad University, Tehran, Iran, in 2007, respectively. He is currently
working toward the PhD degree at the Department of Electrical Engineering,
Sciences and Research Branch, Islamic Azad University, Tehran, Iran. His
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