Session A1 Communication Networks and Services Research Conference 2003
Integrated RF/DSP Designs Using Software Radios:
A Modern Approach to Radio Engineering
[Overview Paper]
Jacek Ilow
Dalhousie University
Department of Electrical and Computer Eng.
Halifax, Nova Scotia, B3J 2S4
j.ilow@dal.ca
ABSTRACT
Software defined radios (SDRs) represent a major change
in the wireless transceiver design paradigm in which a large
portion of the transceiver functionality is implemented thr-
ough programmable digital signal processors or field pro-
grammable gate arrays (FPGAs). A software radio approach
reduces the content of radio frequency (RF) and other ana-
log components of traditional radios and emphasizes digital
signal processing (DSP) to enhance overall transceiver flex-
ibility.
In the past, the choice for the software/digital hardware
platforms to implement SDRs was mainly determined by
the processor clock rates and the speeds of analog-to-digital
converters (ADC), though lately there are additional vari-
ables that influence this decision. To bridge the gap be-
tween system engineering and hardware design in matching
the transceiver complexity to real-time processing capability
of digital hardware, design tools have been developed that
automate the translation from system algorithms to silicon
design flows. These Electronic Design Automation (EDA)
tools enable rapid prototyping of transceivers and are be-
coming critical factors in the quest to reduce design costs
and time to market.
The objective of this paper is to elaborate on some aspects
of this new RF/DSP design paradigm.
Categories and Subject Descriptors
B.4 [Input/Output and Data Communications]: Data
Communications Devices; C.2.1 [Network Architecture
and Design]: Wireless communication
General Terms
Algorithms, Design
Keywords
Software defined radios, EDA, rapid prototyping
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1
1. INTRODUCTION
The basic concepts behind software radios have been re-
searched and implemented in practice for more than a de-
cade [1]—[4]. During the 1980’s and the 1990’s the ad-
vances in DSP and ADCs allowed to have the baseband
signal processing implemented on specialized DSP proces-
sors for voiceband telephone modems. There is currently a
resurgence of interest in software defined radios as the ever
increasing sampling rates of ADC and clock rates of DSP
cores allow to move the DSP functions closer to antenna
and the IF stages of transceivers [5], [6].
A software radio is a transceiver whose channel modu-
lation waveforms are defined in software and implemented
on a DSP or FPGA platform using DACs [7]—[9]. Fig. 1
shows the architecture of a generic software radio. Software
defined radios (SDRs) are designed for applications ranging
from low-power hand-held devices to fixed basestations. As
a result, at present, they employ different technologies and
architectures. One of the driving objectives underlying SDR
concepts today is the desire to have a single platform capable
of servicing a number of radio environments. In general, the
hardware platforms have the following components: (i) I/O
subsystems; (ii) the transmission methodology; and (iii) the
programming environment. The SDR platform focused in
this paper (i) provides a framework for the investigation
into the baseband and IF stages of radio transceivers with
signal bandwidths up to 20MHz and (ii) is versatile enough
to demonstrate proof-of-concept for a number of radio in-
terfaces.
Software radio research has been primarily motivated by
interoperability problems that result from the implemen-
tation of radios in dedicated hardware [10]. In advanced
applications, in addition to more traditional tasks of (de)
modulating waveforms at the baseband, SDRs (i) probe and
characterize radio channels; (ii) adaptively select power lev-
els and steers antenna; (iii) recognize the mode of incoming
transmission; and (iv) null interferes and combine multi-
path signals. For example, in order to improve the spectrum
utilization and to achieve robust communications, the At-
lantic Innovation Fund (AIF) project lead by this author
in the area of SDRs will investigate the implementation
of algorithms able to exploit and manage the characteris-
tics of the channel and variable data transfer demands us-
ing advanced channel coding techniques. Even though the
clock-rates of DSP systems are significantly increasing every
2 CNSR 2003, Moncton, New Brunswick, Canada
Figure 1: Generic Software Radio Architecture.
year, the more sophisticated algorithms and more complex
software invariably require the use of parallel and sequen-
tial partitioning of algorithms to get the required processing
power. The integrated software and hardware tools devel-
oped within the AIF project should be efficient in realizing
these latest trends of multitasking and multiprocessing in
embedded system designs.
2. SOFTWARE/HARDWARE PLATFORMS
Determining the digital hardware composition of a SDR
is a key design step. Basically, three major factors define
the choice of the digital hardware platform:
1. flexibility and configurability of hardware/software com-
ponents;
2. price and performance trade-offs;
3. scalability and support for real-time operation.
Real-time SDR hardware can be built using a variety of dig-
ital hardware consisting of ASICs, DSPs and FPGAs. The
design of digital hardware typically involves computer-aided
design of logic, construction of the schematic diagram, and
building the printed circuit board. DSP processors present
the most generalized type of hardware that can be pro-
grammed to perform almost any function, while an FPGA
can be configured using logic gates with static functionality.
ASICs are the most specialized piece of hardware and are
not considered in this paper.
2.1 Digital Signal Processors
As the DSP business has matured, there is a variety of
DSP processors with different functionalities. e.g., (i) fixed
vs. float point arithmetics, (ii) Harvard and very long in-
struction word architectures, (iii) various addressing modes;
(iv) pipelining; (v) peripherals; (vi) multiprocessing, etc.
In the non-OS (Operating System) approach (traditional
approach with DSP), the main process executes in a syn-
chronous manner; that is the signal processing calculations
are done between each sample (or group of samples, often re-
ferred to as frames). An important note is the fact that since
we have real-time processes, all calculations MUST be done
within this time interval or we loose real-time performance.
Recently, specialized real-time OSs for DSPs appeared on
Session A1
the market. This shows a trend that DSPs are becoming
ubiquitous in electronics, and that more and more support
and/or sophisticated functions are performed by DSPs.
Fortunately, when dealing with these complex DSP chips
and DSP platforms, thanks to an array of preconfigured and
customizable DSP boards and related software, the designer
is not starting from scratch. Reuse of Intellectual Property
(IP) cores becomes a necessity to benefit from more com-
plex hardware platforms. Representative examples of wire-
less designs using DSP processors are discussed in [11], with
the DSP lead chip TMS320C6xxx from TI [12]. The most
exciting development in the DSP boards is not the boards
themselves, but rather, it is the support that companies offer
surrounding their products.
2.2 FPGA DSP Systems
FPGAs are high-speed configurable logic circuits pack-
aged as high-density commodity chips. Configuration of
FPGAs is typically performed when the system is powered
on so that during the operation the FPGA configuration
is usually fixed, although there are examples, e.g., Xilinx
XC6200 series, of FPGAs that can do dynamic reconfigura-
tion [13]. The cellular array of logic cells in the FPGA is
configured for fast local communications and when properly
configured to exploit algorithm parallelisms, an FPGA can
provide a much greater computational advantage than the
general purpose DSP processor.
Introducing FPGA components into DSP system imple-
mentations creates an assortment of challenges across sys-
tem architecture and logic design. Where system architects
may be available, skilled logic designers are a scarce re-
source. There is a growing need for tools to allow system
architects to be able to implement FPGA-based platforms
with limited input from logic designers. Getting FPGA de-
signs translated from software algorithms to hardware im-
plementations follows the process:
1. Model the circuit in VHDL or Verilog;
2. Verify the functionality of the models through simula-
tions;
3. Build a netlist from the VHDL code;
4. Generate the bit files and download them on the target
device;
Session A1 Communication Networks and Services Research Conference 2003 3

FPGA Chip DSP chip

Programming Language VHDL, Verilog C, Assembly Language
Ease of software Fairly easy. However, a programmer needs to Easy
programming understand the hardware architecture
Performance Very fast if an appropriate architecture is Speed is limited by clock speed of DSP chip
implemented
Reconfigurability SRAM-type FPGAs can be reconfigurable Can be reconfigurable by changing program
infinite times
Reconfiguration method Reconfiguration is done by downloading Reconfiguration is done by simply reading
configuration data to chip electronically a program at a different memory address
Areas where FGPAs can FIR and IIR filters, correlator, convolver, FFT A signal processing of sequential nature
outperform DSPs
Power Consumption minimized if the circuit is designed to save Power consumption does not depend
power, or the power is dynamically controlled on the size of the program
as long as memory is the same
Implementation Parallel multiplier/adder or distributed Repeated operation of MAC function
method of MAC arithmetic
Parallelism Can be parallelized to achieve high DSP chip programming is usually sequential
performance

Table 1: A comparison of FPGA and DSP chips.

5. Test the performance. Eventually, only a final system implementation can pro-
vide realistic metrics of the overheads associated with soft-
The comparison between FPGA and DSP chips is shown in ware and hardware configurations in a real-world design.
Table 1.

3. RAPID PROTOTYPE DESIGN 4. PRACTICAL REALIZATIONS AND

Communication equipment manufacturers, to speed up
their development time and reduce necessary investments
to convert their designs to products, resort to embedded
DSP systems. Software radio is an example of such a wire-
less technology. The construction of seamless communica-
tion systems, combining reprogrammable software and re-
configurable hardware poses a number of new challenges.
Co-design and co-simulation must be used during the early
stages of the design flow to consider interaction between re-
configurable and fixed system functions. A DSP example of
an EDA system is the eXpressDSP real-time DSP software
environment that simplifies and streamlines the DSP prod-
uct development process offering a choice of reusable soft-
ware components [12]. An example of the rapid prototyping
DSP/FPGA hardware platform for DSP-FPGA (C67x/Virtex)
architecture in SDR processing applications is the Signal-
Masters from LSP of Quebec which allows the user to de-
velop and test DSP algorithms and perform hardware/software
co-design in a real-time environment [14]. The critical point
in all these EAD systems is to be compatible with the most
popular system-level tools such as Matlab Simulink from
MathWorks, Xilinx’s System Generator or Signal Process-
ing Workstation from Cadence.
The diagram in Fig. 2 represents a complete system-level
design flow process for the LSP DSP-FPG Electronic De-
sign Automation tool. First, a model of a process is done in
Simulink. Then, the model, in whole or in part, is gradually
moved towards an optimized real-time target DSP/FPGA
implementation using code generators, code development
IDEs, real-time I/O boards, optimized DSP libraries, etc.
The reader is referred to LSP documentation and applica-
tion notes for a more in-depth description of this highly ef-
fective development approach [14].
TRADE-OFFS
Resources critical to SDR architectures include I/O band-
width, memory, and processing capacity. A good demand
estimation of these resources and a proper partitioning may
alleviate many bottlenecks in the design of such systems.
4.1 ADC
ADCs are key components of DSP and may even dictate
system architectures due to the limited sampling rates and
the (quantization) resolutions. The ADC determines the
quality of the digital signal available for subsequent pro-
cessing. The ADCs cover a variety of implementations from
parallel (flash), which is the fastest, through integrating,
which is the most accurate.
Advances in ADC technology are still required to sup-
port the high dynamic range requirements of wideband radio
front-ends. Advances are also needed in the area of config-
urable high-bandwidth analog signal processing for realizing
the RF and IF stages of a radio. Micro-electro-mechanical
systems (MEMs) appear to be a promising technology for
addressing in-system configurable analog signal processing.
4.2 Memory
In an embedded system such as a radio terminal there
are usually memory issues to be considered, the normal de-
sire being for more memory than the design or commercial
constraints allow.
4.3 Processing Demands
One of the implementation problems facing SDR designers
is the concept of real time. An efficient utilization of pro-
cessing power is the key to meet throughput and response
time specifications. There are always bottlenecks on differ-
4 CNSR 2003, Moncton, New Brunswick, Canada Session A1

4.4 Performance Tuning

5. CONCLUSIONS

6. REFERENCES