E.C.E.

Department
DESIGN LAB

Experiment No-1

TITLE:
Realization of 555 TIMER
OBJECTIVE:
To familiarize with the operation of timer, its characteristics and applications.
THEORY:
The 555 timer is a unique IC that has enjoyed unprecedented popularity.It is an integrated circuit
(chip) used in a variety of timer, pulse generation, and oscillator applications. The 555 can be
used to provide time delays, as an oscillator, and as a flip-flop element. Derivatives provide up to
four timing circuits in one package.3 This is attributed to its versatility, stability, high
performance, and low cost. It has altered the course of the electronics industry with an impact not
unlike that of the op-amp. The timing period can be varied over a wide range by a choice of
externally connected resistance and capacitance.1

FIG: 1 Pin diagram of 555 IC 2

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

CLASSIFICATION OF MULTIVIBRATORS:2

The 555 timer lends itself to three basic operating modes viz
a) Monostable
b) Astable

1. ASTABLE MULTIVIBRATOR
Astablemultivibrator is known as free running multivibrator.It has two quasi-stable states and
it continues to oscillate between two stable states. This multivibrator has no stable state and
external trigger pulses are not required to change the states. This device can be used to generate
square wave and the time duration depends upon circuit parameters. The continuously generated
pulses are used as clock pulses in flip-flops, registers, counters and other digital circuits where
clock pulse is required for operation.

2. MONOSTABLE MULTIVIBRATOR:
Monostablemultivibrator has a single stable state and a quasi-stable state. In this multivibrator
,trigger signal is applied to switch from stable state to quasi-stable state. After a short time,
circuit reverts back to its stable state. Hence, a single output pulsed is generated when a trigger
pulse is applied to it. Therefore, it is known as one shot or single shot multivibrator circuit.

COMPONENTS USED:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

Sl.
No.
1.

Component/
Apparatus Name
CRO

Quantit
y
1

2.

555 TIMER
TRAINER KIT
CONNECTING
WIRES

3.

Specification

Manufacturer

Remark

3802,25 MHz (2
CH 4
TRACE)
-

APLAB

CALIBRATE
D

SINGLE
STRING

MICROTECH
INDUSTRIES
-

CIRCUIT DIAGRAM:

FIG: 2 EXPERIMENTAL CIRCUIT FOR ASTABLE MULTIVIBRATOR4

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

FIG: 3 EXPERIMENTAL CIRCUIT FOR MONOSTABLE MULTIVIBRATOR5

PRECAUTIONS:7
1.Pin 7 gets connected to the 0v rail via a transistor inside the chip during part of the operation of
the 555. If the pot is turned to very low resistance in the following circuit, a high current will
flow through the pot and it will be damaged.
2.The impedance of the 100u electrolytic will allow a very high current to flow and the chip will
get very hot. Use 10u maximum when using 8R speaker.
3.The reset pin (pin 4) is internally tied HIGH via approx 100k but it should not be left floating
as stray pulses may reset the chip.

CONCLUSIONS:3
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

1. In the monostable mode, the 555 timer acts as a "one-shot" pulse generator.
2. In bistable mode, the 555 timer acts as a basic flip-flop.
3. In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having
a specified frequency.
.
REFERENCE:
1.
2.
3.
4.
5.
6.
7.

Analog electronic circuits S.K Mandal (Pg: 9.1-9.2 &9.19 )

Lab manual (analog electronics dept.)
http://en.wikipedia.org/wiki/555_timer_IC
http://www.electrosome.com/astable-multivibrator-555-timer/
http://www.electrosome.com/monostable-multivibrator-555-timer/
http://w3education.in/w3/wp-content/uploads/2013/03/pic2.jpg
http://www.555-timer-circuits.com/common-mistakes.html

Experiment No-2

TITLE:
Realization of op-Amp adder and Subtractor
OBJECTIVE:
To designop-Amp adder and Subtractor

THEORY:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

The adder can be obtained by using either non-inverting mode or differential amplifier. Here the
inverting mode is used. So the inputs are applied through resistors to the inverting terminal and
non-inverting terminal is grounded. This is called virtual ground, i.e. the voltage at that
terminal is zero. The gain of this summing amplifier is 1, any scale factor can be used for the
inputs by selecting proper external resistors.
The subtractor circuit, input signals can be scaled to the desired values by selecting appropriate
values for the resistors. When this is done, the circuit is referred to as scaling amplifier.
However in this circuit all external resistors are equal in value. So the gain of amplifier is equal
to one. The output voltage Vo is equal to the voltage applied to the non-inverting terminal minus
the voltage applied to the inverting terminal; hence the circuit is called a subtractor.

COMPONENTS USED:
Sl.
Component/ Apparatus
No.
Name
1.
IC 741
2.
Resistors
3.
Vco
4
Function generator

Quantit
y
1
3
1
1

Specificatio
n
1k ohm
-

CIRCUIT DIAGRAM:
Op amp adder:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Manufacture
r
-

Remar
k
good
good
good
good

E.C.E. Department
DESIGN LAB

Op amp subtractor:

PROCEDURE:
Adder circuit

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

1.

Connect the circuit as per the diagram.

2.

Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.

3.

Apply the inputs V1 and V2 as shown.

4.

Apply two different signals (DC/AC ) to the inputs.

5.

Vary the input voltages and note down the corresponding output at pin 6 of the IC
741 adder circuit.

6.

Notice that the output is equal to the sum of the two inputs.

Subtractor circuit
1. Connect the circuit as per the diagram.
2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.
3 Apply the inputs V1 and V2.
4. Apply two different signals (DC/AC ) to the inputs.
5. Vary the input voltages and note down the corresponding output at pin 6 of the IC 741
subtractor circuit.
6. Notice that the output is equal to the difference of the two inputs.

EXPERIMENT RESULT:
Adder circuit
V1

V2

V o/p

-4.06

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

5.8

-8.04

Calculation: Adder

Vo = (V1 + V2)

If V1 = 2V and V2 = 2V, then

Vo = (2+2) = -4V.

Subtractor circuit
V1

V2

V=o/p

-2

3.1

5.7

-2.67

Calculation: Subtractor

Vo = V2 V1

If V1=4 and V2 = 2, then

Vo = 4 2 = -2

PRECAUTIONS:
We must check whether the connections are proper or not.
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

2. Adapter was connected to +V cc and ground.

3. Adapter and LED should be checked.

CONCLUSIONS:
From the above experiment performed here, we have acquired the experimental data of op amp
adder and subtractor which is verified with the theoretical value.

REFERENCE:
[1]http://www.google.co.in/imgres?
imgurl=http://www.electronicstutorials.ws/combination/comb27
[2] http://www.ee.surrey.ac.uk/Projects/Labview/adder/
[3]http://en.wikipedia.org/wiki/subtractor
[4]https://www.google.co.in/search?q
[5]https://www.google.co.in/search?
q=4+to+1+adder+truth+table&tbm=isch&tbo=u&source=univ&sa=X&ei=W5D
[6]https://www.google.co.in/search?
q=4+to+1+subtractor+truth+table&tbm=isch&tbo=u&source=univ&sa=X&ei=W5D

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

Experiment No-3

TITLE:
Realization of 4:1 multiplexer
OBJECTIVE:
Truth table verification of 4:1 multiplexer using basic gates.

THEORY:
It quite often happens, in the design of large-scale digital systems, that a single line is required to
carry two or more different digital signals. Of course, only one signal at a time can be placed on
the one line. What is required is a device that will allow us to select, at different instants, the
signal we wish to place on this common line. Such a circuit is referred to as a Multiplexer [1, 2 ,
3and 4]
.A multiplexer performs the function of selecting the input on any one of 'n' input lines and
feeding this input to one output line.
Multiplexers are used as one method of reducing the number of integrated circuit [5] packages
required by a particular circuit design [6]. This in turn reduces the cost of the system. Assume that
we have four lines, I0, I1, I2 and I3, which are to be multiplexed on a single line, Output(Y). The
four input lines are also known as the Data Inputs. Since there are four inputs, we will need two
additional inputs to the multiplexer, known as the Select Inputs, to select which of the C inputs
is to app select lines S0 and S1. Call these select lines S0 and S1 .The circuit symbol for the above
multiplexer is:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

TRUTH TABLE:
Input
S1
0
0
1
1

S0
0
1
0
1

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Output
Y
I0
I1
I2
I3

E.C.E. Department
DESIGN LAB

Circuit diagram:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

COMPONENTS USED:
Sl. No.
1.
2.
3.
3.
4.

Component/ Apparatus
Name
Not gate
3 I/P AND gate
2 i/p OR gate
LED
Bread Board

Quantit
y
1
2
1
1
1

5.

Connecting wires

22

6.

Adaptor

Specification
IC 7404
IC 7411
IC 7432
4-5 V
Series & parallel
connection
Single String plastic
coated
AC100-240V50/60Hz

EXPERIMENT RESULT:
Hence the truth table of 4:1 multiplexer is verified using basic gates.

PRECAUTIONS:
1. We must check whether the connections are proper or not.
2. Adapter was connected to +V cc and ground.
3. Adapter and LED should be checked.

CONCLUSIONS:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Manufacture
r
Intel
Intel
Intel
-

Remark

Ok

Mastech

Ok

Ok
Ok
Ok
Ok

E.C.E. Department
DESIGN LAB

From the above experiment performed here, we have acquired the logical expression, truth table
and Boolean expressions of 4:1 Multiplexer. The expression also made us familiar with the
operation of multiplexer.

REFERENCE:

[1]http://www.google.co.in/imgres?
imgurl=http://www.electronicstutorials.ws/combination/comb27
[2] http://www.ee.surrey.ac.uk/Projects/Labview/multiplexer/
[3] Truth Table from G.K.KHARATE (Page no. 241).
[4]http://en.wikipedia.org/wiki/Multiplexer
[5]https://www.google.co.in/search?q
[6]https://www.google.co.in/search?
q=4+to+1+multiplexer+truth+table&tbm=isch&tbo=u&source=univ&sa=X&ei=W5D

Experiment No-4

TITLE:
Realization of 1:4 demultiplexer
OBJECTIVE:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

Truth table verification of 1:4 demultiplexer using basic gates.

THEORY:
Demultiplexer means one to many. A demultiplexer is a circuit with one input
and many output. By applying control signal, we can steer any input to the
output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16
demultiplexer.
Following figure illustrate the general idea of a demultiplexer with 1 input
signal, m control signals, and n output signals.

Fig 1: Demultiplexer Pin Diagram

TRUTH TABLE:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

Circuit diagram:

Fig 2: 1 to 4 Dempultiplexer Circuit Diagram

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

COMPONENTS USED:
Sl. No.
1.
2.
3.
3.
4.

Component/ Apparatus
Name
Not gate
3 I/P AND gate
2 i/p OR gate
LED
Bread Board

Quantit
y
1
2
1
1
1

5.

Connecting wires

22

6.

Adaptor

Specification
IC 7404
IC 7411
IC 7432
4-5 V
Series & parallel
connection
Single String plastic
coated
AC100-240V50/60Hz

EXPERIMENT RESULT:
Hence the truth table of 1:4 demultiplexer is verified using basic gates.

PRECAUTIONS:
1. We must check whether the connections are proper or not.
2. Adapter was connected to +V cc and ground.
3. Adapter and LED should be checked.

CONCLUSIONS:

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Manufacture
r
Intel
Intel
Intel
-

Remark

Ok

Mastech

Ok

Ok
Ok
Ok
Ok

E.C.E. Department
DESIGN LAB

From the above experiment performed here, we have acquired the logical expression, truth table
and Boolean expressions of 1:4 Demultiplexer. The expression also made us familiar with the
operation of demultiplexer.

REFERENCE:

[1]http://www.google.co.in/imgres?
imgurl=http://www.electronicstutorials.ws/combination/comb27
[2] http://www.electronicshub.org/multiplexer-and-demultiplexer
[3] Truth Table from G.K.KHARATE (Page no. 257).
[4]http://en.wikipedia.org/wiki/Demultiplexere
[5]https://www.google.co.in/search?q
[6] http://www.electronicshub.org/wp-content/uploads/2015/07/1-to-4-Demux-truth-table.jpg

Experiment No-5

TITLE:
Realization of BCD to 7 segment decoder.
OBJECTIVE:
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

To design BCD to 7 segment decoder.

THEORY:
The basic idea involves driving a common cathode 7-segment LED display using combinational
logic circuit. The logic circuit is designed with 4 inputs and 7 outputs, each representing an
input to the display IC. Using Karnoughs map, logic circuitry for each input to the display is
designed.
The first and foremost aspect of this circuit is decoder. A decoder is a combinational circuit
which is used to convert a binary or BCD (Binary Coded Decimal) number to the corresponding
decimal number . It can be a simple binary to decimal decoder or a BCD to 7 segment decoder.

COMPONENTS USED:
Sl.
No.
1.
2.
3.
4.

Component/ Apparatus
Name
IC 7411
IC 7408
IC 7432
LED

Quantit
y
1
3
2
7

Specificatio
n
-

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

Manufacture
r
-

Remar
k
good
good
good
good

E.C.E. Department
DESIGN LAB

CIRCUIT DIAGRAM:

TRUTH TABLE:

PROCEDURE:
Step 1: The first step of the design involves analysis of the common cathode 7-segment display.
Step 2: The second step involves constructing the truth table listing the 7 display input signals,
decimal number and corresponding 4 digit binary numbers.

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

Step 3: The third step involves constructing the Karnoughs map for each output term and then
simplifying them to obtain a logic combination of inputs for each output.
Step 4: The final step involves drawing a combinational logic circuit for each output signal

EXPERIMENT RESULT:
Hence the truth table of bcd to 7 segment decoder is verified using basic gates

PRECAUTIONS:
1. We must check whether the connections are proper or not.
2. Adapter was connected to +V cc and ground.
3. Adapter and LED should be checked.

CONCLUSIONS:
From the above experiment performed here, we have acquired the logical expression, truth table
and Boolean expressions of bcd to 7 segment decoder. The expression also made us familiar with
the operation of bcd to 7 segment decoder.

REFERENCE:
[1]http://www.google.co.in/imgres?
imgurl=http://www.electronicstutorials.ws/combination/comb27
[2] http://www.ee.surrey.ac.uk/Projects/Labview/bcd to 7 segment decoder/
[3]http://en.wikipedia.org/wiki/bcd to 7 segment decoder
ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT

E.C.E. Department
DESIGN LAB

[4]https://www.google.co.in/search?q

ELECTRONICS & COMMUNICATION ENGINEERING DEPARTMENT