International Journal of Computer Systems (ISSN: 2394-1065), Volume 03 Issue 03, March, 2016

Available at http://www.ijcsonline.com/

A Novel Approach for High Speed Multimedia compression using 64 bit

Quadrature Amplitude Modulator/Demodulator
Dr. V. Vidya Devi, M. Indraja
Department of ECE, JNTU University,
Holy Mary Institute of Technology & Science Bogarm(v),
Keesara (M).R R dist- India

Abstract
This project aims Reconfigurable ability and high throughput performance Field Programmable Gate Array (FPGA)
,embedded applications like communication broad coasting, industrial automation, bio medical imaging, mobile
communication and automation . A reconfigurable design using quadrature amplitude modulation is used for analogue
and digital scheme using amplitude Phase Shift Keying(ASK) (PSK) modulation and demodulation implemented on a
Virtex4 FPGA board using MATLAB / Simulink and Xilinx system generator . Numerically controlled oscillator (NCO)
controls the phase of the each carrier signal which creates a synchronous (i.e. clocked), discrete amplitude modulation
with bit error reduction -time, discrete-valued used in conjunction with a digital-to-analog converter (DAC) at the output
to create a direct digital synthesizer (DDS). A carrier recovery circuit and a numerically controlled oscillator are used
on the receiver side to correctly recover transmitted data. 64 bit QAM is designed with cut off frequency of 1 MHZ with
single bit error .Compare to Binary phase shift keying this in turn reduces the number of multipliers used in filter
circuits ,band width and increase the speed.64bit QAM have been successfully designed and results are verified by
simulation and presented. As the number of multipliers reduces there is waste reduction in data and good compression is
achieved.
Keywords: QAM quadrature amplitude modulation, VCO voltage controlled oscillator, BPSK binary frequency shift
keying, FPGA field programmable gate array, PRK phase reversal keying.

I.

INTRODUCTION (BPSK 1)

This BPSK ( PRK, phase reversal keying, or 2PSK) is

the simplest form of phase shift keying (PSK). It uses two
phases which are separated by 180 and so can also be
termed 2-PSK. It does not particularly matter exactly where
the constellation points are positioned, and in this figure
they are shown on the real axis, at 0 and 180. This
modulation is the most robust of all the PSKs since it takes
the highest level of noise or distortion to make
the demodulator reach an incorrect decision. It is, however,
only able to modulate at 1 bit/symbol (as seen in the figure)
and so is unsuitable for high data-rate applications.

waveform and regeneration from the band limited

waveform back to the binary message bit stream. In the
first stage, translation back to baseband requires a local,
synchronized carrier. Translation back to baseband is
achieved with a synchronous demodulator. This requires a
local synchronous carrier. In this experiment a stolen
carrier will be used. Carrier acquisition will be investigated
in the experiment entitled DPSK carrier acquisition and
BER .At second stage, the translation process does not
reproduce the original binary sequence, but a band limited
version of it. The original binary sequence can be
regenerated with a detector. This requires information
regarding the bit clock rate. If the bit rate is a sub-multiple
of the carrier frequency then bit clock regeneration is
simplified.

Figure 1. BPSK modulator

BPSK DEMODULATOR
Demodulation of a BPSK signal can be considered as a
two-stage process. These are the translation back to
baseband, with recovery of the band limited message

Figure 2 Characteristics of BPSK Modulator

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator

waveform look-up-table to provide a corresponding

amplitude sample its shown in figure (6).
Sometimes interpolation is used with the look-up table to
provide better accuracy and reduce phase error noise.
Other methods of converting phase to amplitude shown in
figure
(6).

Figure 3. BPSK Demodulator

II.

OPTIMIZATION ON BPSK MODULATOR BY

USING NCO:

In BPSK the modulator portions having a two blocks are

available to produced sine and inverse sine wave. but
Numerically Controlled Oscillator (NCO) can reduced
those two blocks into a single block area and power will
be reduced in modulator.
Input
sequence

NCO
Generation

Clock
generatio
n

Look-uptable(LUT
)

Figure. 4 Design of BPSK Modulator

2s
Compleme
nt

Sine
Cosin
e

Figure 6. Numerically Controlled Oscillator (NCO)

When clock is applied to the oscillator, the phase

accumulator creates saw tooth waveform. After that the
PAC is converted into sinusoidal, where N is the number
of bits carried in the PA. Then N sets the NCO frequency
resolution and is normally much larger than number of bits
defining the memory space of the PAC look-up-table. If
supposed the PAC capacity is 2^M , the PA bits should be
returned to add the input signals. The frequency accuracy
relative to the clock frequency is limited only by the
precision of the arithmetic used to calculate the phase to
know about this information check with reference paper 2.

Figure. 7. Characteristics of NCO

Figure 5.Architecture for BPSK Using NCO

a) LINEAR FEEDBACK SHIFT REGISTER

The LFSR is Linear feedback shift register is a shift
register used to generated sequence of bits which system is
need random input bits for linear function of its previous
stage. The mostly used linear function of single bits is
XOR. Thus, the LFSR is most often a shift register whose
input bit is driven by the exclusive-or (XOR) of some bits
of the overall shift register value shown in fig (5).
b) NUMERICALLY CONTROLLED OSCILLATOR
A numerically controlled oscillator (NCO) is a digital
signal generator which generated a synchronous (i.e.
sinusoidal). NCOs are often used in conjunction with
a digital-to-analog converter (DAC) at the output to create
a direct digital synthesizer for about this information
check with reference paper 1.
An NCO consists of two blocks first phase accumulator
which add to the value held at this output a frequency
control value at each clock sample increment, second is
phase to amplitude convertor is used to the phase
accumulator output word usually as an index into a

If the data is read from 0 to 15, the increment operation

will done at phase accumulator, so sine wave will
generate. When the data reads from 15 to 0, the decrement
operation is done at PA, so that cosine wave will generate.
Usage of NCO:-can reduces the area in modulator,
However, if the sample rate reduces means resources
reduces.
c) APPLICATIONS FOR NCO
NCOs are used in many communications systems
including digital up/down converters used in 3G wireless
and software radio systems, Digital PLLs, radar systems,
Acoustic
transmissions,
and
multilevel FSK/PSK
modulators/demodulators.
III.

QAUDRATURE AMPLITUDE MODULATION

A)QAM:
QAM is both an analogy and digital modulation is
presented. It used to conveys two digital bit streams or

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator

analog signals, by modulating the amplitude of the two

carrier waves using PSK and ASK scheme.
QAM = phase-shift keying (PSK) + amplitude-shift
keying(ASK ), In the digital QAM case, a finite number
of at least two phases and at least two amplitudes are used.
PSK modulators are often designed using the QAM
principle, but are not considered as QAM since the
amplitude of the modulated carrier signal is constant.
There are two types of QAM1.Rectangular QAM, 2.NonRectangular QAM.for detail information pls check with
reference link 10.

which is shown here. A gray coded bit-assignment is also

given. The reason that 16-QAM is usually the first is that a
brief consideration reveals that 2-QAM and 4-QAM are in
fact binary phase-shift keying(BPSK) and quadrature
phase-shift keying (QPSK), respectively. Also, the errorrate performance of 8-QAM is close to that of 16-QAM
(only about 0.5 dBbetter , but its data rate is only threequarters that of 16-QAM.

TABLE 1. DESIGN VALUES FOR I AND Q MEMORY

B) 64-RECTANGULAR QAM:
Rectangular QAM constellations are, in general, suboptimal in the sense that they do not maximally space the
constellation points for a given energy. However, they
have the considerable advantage that they may be easily
transmitted as two pulse amplitude modulation (PAM)
signals on quadrature carriers, and can be easily
demodulated. The non-square constellations, dealt with
below, achieve marginally better bit-error rate (BER) but
are harder to modulate and demodulate.

Figure 8. 64_QAM Modulator design

The values are obtained by using scatter plot program in

matlab.
The matlab program as follows as:
for i=0:63
s = i; dd = [];
for i=1:10 dd = [dd s];
end
jj = qammod(dd,64);
dd scatterplot(jj);
hold on;
end ........
The signal are shifted towards from upper to lower in
design.
IV.

POWER SCALING FACTOR CALCULATION

Figure .9 Constellation diagram for 64_QAM

C) SPECIFICATION FOR 64_QAM DESIGN

64-QAM: (64-state quadrature amplitude modulation).

three I values and three Q values are used,
yielding three bits per symbol
64-QAM:
64 states
= 64:I = 3; Q=3,
bits = 2 changing
The first rectangular QAM constellation usually
encountered is 16-QAM, the constellation diagram for

The 64_QAM power scaling factor design is given below

= (1/42) * 2^16 = 10112.4
( i.e) 64QAM=
77j, 75j, 7+3j, 71j
57j, 55j, 5+3j, 51j
37j, 35j, 3+3j, 31j
17j, 15j, 1+3j, 11j
E64QAM

= E[|64QAM|]
=E[Real
[|64QAM|]
+
E[image[|64QAM|]
= 2E[R| [|64QAM|]
= 2*4 1+3+5+7 =42
16
ies . the power factor is calling in square root of factor
value.

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator

ROLL-OFF FILTER:
The roll-off filter is used to limit the frequency range. For
example the sampling frequency is 16MHZ means, the
cut-off frequency should be 1MHZ.Then normal function
also done this filter (i.e reducing the noise signal).

Figure 10. 64-QAM Demodulator

TIMING RECOVERY
The reality is that receiver never knows the precious
arrival times of pulse. The receiver must knows the sample
frequency and where to take the sample within each
symbol interval. Timing recovery consists of timing
measurements and correction. The timing measurement
means estimation of the the timing error (i.e.
algorithm)The timing correction can be performed in
several ways;
1. Adjusting the timing phase of the voltage controlled
oscillator
2. Using the interpolation filter.
3. Adjusting the receiver filter
Synchronization is the process of aligning the time
scales between two or more periodic process that are
occurring at spatially separated points. This is one of the
most critical receiver functions in synchronous
communication systems. The receiver synchronization
problem is to obtain accurate timing information
indicating the optimal sampling instants of the received
data signal.In early systems, the timing information was
transmitted on a separate channel or by means of a discrete
spectral line at an integer multiple of the clock frequency
imposed on the data signal itself. Clearly such system had
many disadvantages, including inefficient utilization of
bandwidth.

GARDNER ALGORITHM
1t needs two sample per symbols,2.Insensitive to carrier
offsets, the timing recovery loop can lock first, therefore
simplifying the task of carrier recovery
Gardner error can be used to determine whether the
sampling is correct , late or early,Gardner error is most
useful on symbol transitions.Finding the timing recovery,
which means that where the signal is starting from origin.
Error for the Gardner algorithm is computed using the
following equation:
En = (Y1-Yn-2)Yn-1,where the Yn and Yn-2 is T Sec
and the spacing between Yn and
Yn-1 is T/2 Sec.

Figure 12. Correct Timing

en = (yn yn --2) yn-1

= (-1-1)*0
= 0 (correct timing) no pushing and pulling

Figure 13. Early timing (Fig 4.6)

en = (yn (yn--2)) yn-1= (-0.8-0.8)*0.2= -0.32 (early

timing) negative side pulling

Figure 14. Late timing

en = (yn yn-2) yn-1= (-0.8-0.8)*-0.2

timing) positive side pushing.

= 0.32 (early

NEED FOR PREAMBLE

To finding the synchronization data where it started
from origin to add the preamble signal with before carrier
signal .Its used to estimation the unknown pattern of the
modulated sample and also finding the sample space at
each.

Figure 15.Preamble signal characteristics

Figure 11. Timing recovery characteristics

In digital communication system that are efficient in

power requirement and bandwidth occupancy, the timing
information must be derived from the data signal itself and
based on some meaningful optimization criterion which
determines the steady-state location of the timing instants.
For finding the samples we can use the Gardner algorithm.

Timing = (42+42) / 16
= 84/16
= 1.25 sec/sample
When the signal is come by correct timing, that signal
should be locked remains signal is called as modulated
signal.
DOWN SAMPLING
Down sampling is the process of reducing the sampling
rate of a signal done to reduce the data rate or the size of
the data. It acts like a switch. Similar to sampling, but

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator

operates on sequence, analysis is simplified by breaking

into two steps 1)multiply input by impulse sequence of
period N Samples,2)Remove all samples of
x(n)
associated with zero-valued sample of the impulse
sequence, P(n) .Amount to scaling of time axis by factor
1/N.The down sampling is like a switch, which means that
when the signal is presented on early timing
synchronization that signals are generated positive digital
synchronous pulse(ON Mode) and other case if the signals
is presented in late timing synchronization that signals are
generated negative digital synchronous pulse(Off
Mode).By the by using synchronization output signal we
could down the sampling signal at whatever at presented
in modulated signal.
EQUILIZER OPERATION
In constellation point the input datas can be placed at a
particular range of values. By performing operation like
this there will be chances for merging the input data from
another constellation points. So there will be more
complexity in constellation of down sampling signal on
synchronous. This complexity can be reduce by using
The formulas given below.
, Equalizing = (first sample - last sample) x middle sample
For example, if we dont know the exact sample means;
can take it as reference amplitude is to reduce inter symbol
interference to allow recovery of the transmit symbols.
DEMAPPING
For 16-QAM, 32-QAM, 64-QAM, 128-QAM and 256QAM, the constellation points in quadrant 1 are converted
to quadrants 2, 3 and 4 by changing the two most
significant bits (Ik and Qk) and by rotating the q least
significant bits. For user-defined mapping, the input binary
bit sequence is mapped to a constellation point with the
corresponding decimal index specified in the Mapping
Table parameter.
V.

Figure 17.RTL schematic for NCO

COMPUTED
INPUTS=0029 FFD7
0029=0000000000101001
FFD7=1111111111010111
OUTPUT:
0-SINE WAVE ;1-COSINE WAVE

When the input data will be changed from 0 to 1, the

output wave will change at 180degree phase shift
accordingly.

Figure 18. Output Waveform

RESULTS

The following diagram shows the results obtained in

modulation and demodulation for both BPSK and QAM
modulation and demodulation with RTL and output
waveforms.

Figure 16 RTL schematic for BPSK modulation

Figure 19. RTL Schematic For 64_QAM Modulator

Figure 20.RTL Schematic For 64_QAM Modulator

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator

In constellation point the input datas can be placed at a

particular range of values. By performing operation like
this there will be chances for merging the input data from
another constellation points. Basically the equalizer can
performing under the cardiac dived.

Figure 21.Output Waveform For 64_QAM modulator

Figure 25.Output Waveform For 64_QAM System (Mod and Demod)

Figure 22.Output Waveform In Analog

Here found the single bit error while demodulating the

signal after equalizing operation. slightly variation is there
in output d-out part compare with the input signal. If
implemented this program into FPGA kit we can predict
that single bit error. Then, by using the 8byte input data
can reduce the area on QAM system as before. The single
bit error show in below as file comparison

OUTPUT WAVEFORM IN ANALOG

In this fig is shown as a analog for verification of signal
complexity. Since input data is 6 bytes but output is 64
bits. Input signal add with a schnournous (Carrier signal)
to modify the amplitude of the signal

Figure 26.File Comparison

Figure 23.RTL schematic for 64_QAM Demodulator - Equalizer

Figure 27. Ouput waveform for QAM demodulator

Figure 24.RTL Schematic For 64_QAM Demodulator Equalizer

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V. Vidya Devi et al

A Novel Approach for High Speed Multimedia compression using 64 bit Quadrature Amplitude Modulator/Demodulator
[7]

[8]

[9]

[10]

[11]
Figure 28.Output Waveform for 64 QAM Demod in Gated clock
Weave for Analog

Here, the input signal is generated with 6 Bytes, by

performing the preamble signal can predict the middle
clock frequency for each. When signal is enters in correct
time then only the original message signal will be
generated. Here the one bit error is generated with it.
VI.

CONCLUSION

The BPSK modulator and demodulator was

implemented and verified in system generator. In BPSK
system speed is very slow. QAM was designed to
overcome the speed with sampling rate of 16MHz , the
cut-off frequency is 1MHz is enough. Thus the 64_QAM
Modulator and demodulator was designed and
implemented with single bit error. Here the sample
frequency is 16MHz and cut off frequency is 1MHz, The
number of multiplier on filter side is reduced in turn
increases bandwidth, system speed. As we design and
implementing this program into FPGA kit reduction in
number of multipliers with single bit error, area reduction
is achieved. As reduction in number bits the over all
performance there is a major compression in data format is
achieved.

[12]

[13]

[14]

[15]

[16]
[17]

[18]
[19]

[20]

[21]

[22]

REFERENCES
[1]

[2]
[3]

[4]

[5]

[6]

O.Popescu, A.S.Gontean and G.Budura, "BPSK simulation by

using Xilinx FPGA and Matlab ", IEEE Applied machine
intelligence and informatics (SAMI)2012,pp301-306.
Miller, Brian M., "Numerically controlled oscillator and method of
operation", issued October 14, 2008
S.O.Popescu, A.S.Gontean, F.Alexa, Improved FPGADetector,in Proceedings of the 6th IEEE International Symposium
on Applied Computational Intelligence and Informatics (SACI
2011), Romania, 2011, pp.455-458.
S.O.Popescu,
A.S.Gontean,
G.Budura,
Simulation
and
Implementation of a BPSK Modulator on FPGA, in Proceedingsof
the 6th IEEE International Symposium on Applied Computational
Intelligence and Informatics (SACI 2011),Romania, 2011, pp.459463.
S.O.Popescu, G.Budura, A.S.Gontean, Review of PSK and QAM
Digital Modulation Techniques on FPGA, International Joint
Conference on Computational Cybernatics and Technical
Informatics (ICCC-CONTI), Romania, 2010, pp.327-332.
H.Chye, M.F.Ain, N.M.Zawawi, Design of BPSK Transmitter
Using FPGA with DAC, in Proceedings of the 2009 IEEE
9thMalaysia Conference on Communications, Malaysia, 2009,
pp.451-456.

[23]

O.Azarmanesh, S.Bilen, Developing a rapid prototyping method

using a Matlab/ Simulink/ FPGA development to enable importing
legacy code, Proceedings of the SDR 08 Technical Conference
and product Exposition, USA, 2008.
P.Dondon, J.M.Micouleau, J.Legall, .K.Kadionik, Design of a low
cost BPSK modulator/demodulator for a practical teaching of
digital modulation techniques, in the 4th WSEAS/IASME
International Conference on Engineering Education, Greece, 2007,
F.Ahamed, A.Scorpino, An educational digital communications
project using FPGAs to implement a BPSK Detector,
IEEETransactions on Education, Vol.48, No.1, 2005, pp.191-197.
Sampei S., Moriyama E., Sasaoka H., Kamio Y., Kinoshita N.,
Hiramatsu K., EInogai K. and Honma K.Field 16 QAM / TDMA
for land mobilecommunication systems, Proc.PIMRC93, pp.8993 (Sep. 1993).
Sasaoka H.:High capacity TDMA experiments on trellis
Codedcellular System Using Coded 16 QAM and Cyclic Slow
Frequency Hopping,43th IEEE VTC, pp.285-288 (May 1999)
Wei and C. Lin Non coherent-Coded tutoutial at,ion constructed
from conventional trellis coded
modulation, IEEE Corri
Priiinications Let-1 2 3ters. V01.2, No.9, pp.260-262, Sept. 1998.
F.Ahamed, A.Scorpino, An educational digital communications
project using FPGAs to implement a BPSK Detector, IEEE
Transactions on Education, Vol.48, No.1, 2005, pp.191-197.
H.Nguyen, E.Shwedyk, A first Course in Digital Communications,
Cambridge University Press, New York, 2009. J.G. Proakis, Digital
Communications, 4th edition, McGraw Hill, New York, 2001.
G. Smithson, Introduction to Digital Modulation Schemes, in IEE
Colloquium on The Design of Digital Cellular Handsets, 1998,
United Kingdom, pp. 2/1 - 2/9
F.Xiong, Digital Modulation Techniques, Artech House, UK,
2000.
Mccallister, Ronald D. & Daniel Shearer III, "Numerically
controlled oscillator using quadrant replication and function
decomposition", published 12/04/1984]
Kroupa,Venceslav F.,Direct Digital Frequency Synthesizers, IEEE
Press, 1999, ISBN 0-7803-3438-8.
F.Ahamed, A.Scorpino, An educational digital communications
project using FPGAs to implement a BPSK Detector,
IEEETransactions on Education, Vol.48, No.1, 2005, pp.191-197.
Ampei S., Moriyama E., Sasaoka H., 8Kamio Y., Kinoshita N.,
Hiramatsu K., EInogai K. and Honma K.:FIELD16 QAM /
TDMA
For
Land
Mobilecommunication
Systems,
Proc.PIMRC93, pp.89-93 (Sep. 1993).
Sasaoka H.:High capacity TDMA experiments on trellis coded
cellular System Using Coded 16 QAMand Cyclic Slow Frequency
Hopping,43th IEEE VTC, pp.285-288 (May 1999)
F. Tosato and P. Bisaglia, Simplified soft-output demapper for
binary interleaved COFDM with application to HIPERLAN/2, in
Proc. IEEE ICC 2002, New York, May 2002, vol. 2, pp. 664668.
Sasaoka H.:High capacity TDMA Cellular System Using Coded
16 QAM 14 16 18 20 22 24 and Cyclic Slow Frequency Hopping,
43th IEEE VTC, pp.285-288 (May 1993).

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