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AIM:
a)To design CE single stage amplifier with potential divider circuit using NPN
Transistor 2N2923 for the specifications : IC= 3 mA, Vce = 10v, = 190, & IR1 =
32IB .
b) To observe dc operating point, frequency response, & C.R.O waveforms using
MULTISIM software.
DESIGN PROCEDURE:
Vcc=
Select Vre Vce
Select Vre = 5v
Re=Vre/Ic
Vrc= Vcc-VCE-VRE
Rc=VRC/Ic
IB=Ic/
IR1=32IB
IR2=IR1-IB
VB=VBE+VRE
R2=VB/IR2
R1= (VCC-VB)/IR1
CIRCUIT DIAGRAM:
PROCEDURE:-
1. Rig up the circuit using multisim software and verify the results using DC
operating point analysis (simulate----analysis ---- DC operating point)
2. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate ---- analysis ----- AC analysis)
3.Rig up the circuit using multisim software and verify the results using
oscilloscope
EXPECTED WAVEFORMS:
RESULT:-
AIM: a) To design a single stage FET Common Source amplifier with potential
divider circuit using 2n4861 FET-N channel for the following specifications:
VDD = 24V,ID = 1ma,VGS=2V,VPMAX =13V,RL=1K.
DESIGN PROCEDURE:
CIRCUIT DIAGRAM:
PROCEDURE:- 1. Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate----analysis ---- DC operating
point)
2. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate ---- analysis ----- AC analysis)
3..Rig up the circuit using multisim software and verify the results using
Oscilloscope
EXPECTED WAVEFORMS:
RESULT:
AIM:
Q1) Design a single stage transistor amplifier with potential divider circuit
(using an npn si transistors) with following specifications.
IC=1.6ma,VCE=7.6v,RC=2.2k,VCC=12v, I1=10IB and =54. Verify the DC
values (Voltage and current) at various nodes using Multisim software
DESIGN: IB=IC/
VCC=IC(RC+RE)+VCE ;
RE=0.516k V2=VBE+ICRE ; V2=
V2=I1R2 ; R2=V2/(I1=10IB) ;
I1=VCC/(R1+R2) ; (R1+R2)=
R 1=
PROCEDURE: Rig up the circuit using multisim software and verify the
Q2) Design a single stage transistor amplifier with potential divider circuit
(using an npn si transistors) with following specifications.
DESIGN:
IB=IC/ =
VCC=IC(RC+RE)+VCE ;
RE=0.51k V2=VBE+ICRE ;
V2=I1R2 ; R2=V2/(I1=10IB) ;
I1=VCC/(R1+R2) ; (R1+R2)=
PROCEDURE: Rig up the circuit using multisim software and verify the
analysis
DC
Q3) Cascade above two stages and find overall gain (choose C c=4.7f,
Ce=470f, hfe=50) find the frequency response, DC operating points and
parameter sweep of load resister.
ANALYSIS:
Av2= -AI2*RL2/Ri2 ;
Stage -1: RL1
AI1 =
Ri1 =
Av1 =
CIRCUIT DIAGRAM:
PROCEDURE:- 1. Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate----analysis ---- DC operating
point)
2. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate ---- analysis ----- AC analysis)
3..Rig up the circuit using multisim software and verify the results using
Oscilloscope
EXPECTED WAVEFORMS:
RESULT:
AIM: Design
DESIGN PROCEDURE:
I
I
I
A I IR
C2
B2
C1
B1
S
C2
hFE 50,
hFE 50
B2
C1
B1
C2
CR1
C1
C1
I2
IB1
R hie
AI
D 1 AI
A
IF
D =
I
R
A
C2
C2
VF
VS
IS R S
IF
RS
CIRCUIT DIAGRAM:
PROCEDURE:- 1. Rig up the circuit using multisim software and verify the
results using DC operating point analysis (simulate----analysis ---- DC operating
point)
2. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate ---- analysis ----- AC analysis)
3..Rig up the circuit using multisim software and verify the results using
Oscilloscope
EXPECTED WAVEFORMS:
RESULT:
F
Capacitors - 10
wires.
DESIGN PROCEDURE:
Formula f =1/2(R1C1R2C2)
Given R=10k, C=0.01uf
If R1=R2 ; C1=C2
fT = 1/ 2RC
CIRCUITDIAGRAM:
PROCEDURE:
1. Connections are made as per the circuit diagram
2. Feed the output of the oscillator to a C.R.O by making adjustments in the
Potentiometer connected in the +ve feedback loop, try to obtain a stable
sine Wave.
3. Measure the time period of the waveform obtained on CRO. & calculate
the Frequency of oscillations.
4. Repeat the procedure for different values of capacitance.
MODEL WAVE FORM:
RESULT:
AIM:
Obtain hfe for the above designed value for AV > - 29, R 2 RC.
DESIGN PROCEDURE:
A) Let R = 10K
Fr
1
___________
2Rc(6+4K)
WHERE K=Rc/R
CIRCUIT DIAGRAM:
VCC
12V
VCC
R1
R3
100kohm
4kohm
C2
10
C1
Q2
4
2N2222A
10uF
R2
11
100uF
22kohm
R4
1kohm
C6
C5
C4
R7
R6
R5
PROCEDURE: Rig up the circuit using multisim software and verify the results
using Oscilloscope.
RESULT:
AIM :
To study the operation of Class A, Class AB, Class B, Class C power amplifiers.
APPARATUS:
CIRCUIT DIAGRAM:
V2
12V
R2
R5
1kohm
1kohm
47uFC2
R3
XSC1
Q1
47uF
30kohm
R1
PN2369A
C1
A
B
100ohm
V1
R4
50mV
100ohm
35.36mV_rms
1000Hz
0Deg
THEORY:
1.Class A
2.Class AB
3.Class B
4.Class C
CLASS A:- In class A operation the quiescent point and the input signal are such
that the current in the output circuit (at the collector) flows for all times. Class A
amplifier operates essentially over a linear portion of its characteristic there by
giving rise to minimum of distortion .
CLASS B:- In class B operation , the quiescent point is at an extreme end of the
characteristic , so that under quiescent conditions the power drawn from the dc
power supply is very small .If the input signal is sinusoidal, amplification takes
place for only half cycle.
CLASS AB:- A class AB amplifier is the one that operates between the two
extremes defined for class A and Class B. Hence the output signal exists for more
than 1800 of the input signal.
PROCEDURE:
varying R3 value, observe and record the output waveforms for different classes
of operation.
Also observe the Vi & Vo waveforms using parameter sweep for different classes
of operation.
OBSERVATIONS:
CLASS A:
CLASS AB :
CLASS B :
CLASS C :
RESULT :
AIM - Design a common Base high frequency amplifier with a over all gain of 30
and Lower cut off frequency of 130 Hz and Higher cut frequency 10 MHz .
Transistor Specifications: hib = 22.6, hfb = -0.98, hrb = 2.910-4 , hob = 0.49 s, IC =
1.35ma = -IE, VCE = 5.85V, VEB = 0.6V, VCB = 5.25V.
Verify the DC values (Voltage and current) at various nodes using Multisim software
DESIGN PROCEDURE:
VCB = 5.25V
KVL to Input:
KVL to Output :
RC =
1.To find Cb
f L=
_____________
2(Rs + Ri)Cb
To calculate RL
Av = - hfb RL/Ri
RL1= RL// Rc
fh
=
2RL C sh
CIRCUIT DIAGRAM :
XSC1
A
B
T
Rs
Cb
10uF
BC107BP
10uF
Cb1
10
11
12
100ohm
Q1
Rc
Re
V1
5kohm
R5
Csh
1kohm
10mV
15kohm
2pF
7.07mV_rms
7
VEE
12V
1000Hz
2V
0Deg
VCC
PROCEDURE: 1.Rig up the circuit using multisim software and verify the
operating point)
2. Rig up the circuit using multisim software and verify the results using AC
analysis (Simulate--- Analysis--- AC analysis)
RESULTS:
AIM: To study the operation of Class A, Class B, Class AB and Class C power
amplifiers.
EQUIPMENT:
3.C.R.O
CIRCUIT DIAGRAM:
PROCEDURE:
1.Connect the circuit as shown in the circuit diagram, and get the circuit
verified by your Instructor.
Connect the signal generator with sine wave at 1KHz and keep the amplitude
at .5V (peak-to-peak)
Now switch ON the trainer and see that the supply LED glows.
Slowly varying the potentiometer, observe the outputs for the Class
A/B/AB/C amplifiers as shown in fig.
CLASS A:
CLASS B:
CLASS AB:
CLASS C :
RESULT:
AIM:
EQUIPMENT:
Function generator.
C.R.O.
CIRCUIT DIAGRAM:
PROCEDURE:
1.Connect the circuit as shown in fig and get the circuit verified by your Instructor.
2. Connect the signal generator with sine wave at the input and keep the amplitude to
minimum position, and connect a C.R.O at output terminals of the circuit.
Apply the amplitude between 1.6v to 4.4v to get the distortion less output sine wave.
Now, vary the input frequency in steps and observe and record The output voltage.
Calculate the gain of the tuned RF amplifier using the formula Gain = out put voltage/
input voltage.
Graph :-
Gain
Frequency
RESULT:
AIM: To design Hartley and Colpitts Oscillators to have resonant frequency of 1KHz.
APPARATUS:
BJT(BC107),Resistors(2.2k,100k,10k,1k),
Capacitors(10f,100f,0.33 f), Decade inductance box ,RPS.
EQUIPMENT:
SDC kit.
Function generator.
C.R.O.
DESIGN PROCEDURE:
Hartley Oscillator
F = 1 / (2LeqC)
Where Leq=L1+L2
Colpitts Oscillator
F = 1 / (2LCeq)
Where Ceq= (c1*c2) / (c1+c2)
CIRCUIT DIAGRAMS:
HARTLEY OSCILLATOR:
COLPITTS OSCILLATOR:
EXPECTED WAVEFORM:
RESULT:
AIM:
To construct a Darlington current amplifier circuit and to plot the frequency
response characteristics.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
5.
6.
7.
Name
Transistor
Resistor
Capacitor
Function Generator
CRO
Regulated power supply
Bread Board
CIRCUIT DIAGRAM
Range
BC 107
15k,10k,680,6k
0.1F, 47F
(0-3)MHz
30MHz
(0-30)V
Quantity
1
1,1,1,1
2, 1
1
1
1
1
MODEL GRAPH
f1
FIG..2
f2
f (Hz)
THEORY:
In Darlington connection of transistors, emitter of the first transistor is
directly connected to the base of the second transistor .Because of direct coupling
dc output current of the first stage is (1+h fe )Ib1.If Darlington connection for n
transitor is considered, then due to direct coupling the dc output current foe last
stage is (1+hfe ) n times Ib1 .Due to very large amplification factor even two stage
Darlington connection has large output current and output stage may have to be a
power stage. As the power amplifiers are not used in the amplifier circuits it is not
possible to use more than two transistors in the Darlington connection.
In Darlington transistor connection, the leakage current of the first
transistor is amplified by the second transistor and overall leakage current may be
high, Which is not desired.
PROCEDURE: