Reliability simulation in

CMOS 90nm design using Eldo

Chittoor Parthasarathy, Emmanuel Vincent
STMicroelectronics (Crolles)
Philippe Raynaud, Cyril Descleves
Mentor Graphics (Grenoble)

STMicroelectronics

Mentor Graphics

Introduction
Aggressive device performances are required in modern CMOS
technologies
SoC, multiple devices
less degrees of freedom
Overdrive / unscaled Vdd : more performances expected

Reliability margins better quantified, but are narrower than before

Exhaustive OLT (Operational Life Test) of final product is quite
difficult
Products are convergence driven
 difficult to optimize OLT with respect to planning, execution and costs
 expensive to correct any reliability problems occurring at this level.

Intrinsic reliability : move from management at process level

towards a process/design co-management
NBTI is a new limiting failure mode for modern technologies which
requires this co-management intrinsic reliability

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Crolles

Reliability simulation in CMOS 90 nm design using Eldo

Goal of this presentation

To present an open solution for reliability
assessment developed within a circuit
simulator (Eldo from Mentor Graphics)
To discuss some of the features that are useful in
translating different issues of device reliability for
the actual circuit operating conditions.

To present its application to NBTI

degradation in 90nm technology

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Reliability simulation in CMOS 90 nm design using Eldo

Reliability simulation
Spurt of DiR (Design in Reliability) tool development during
early 1990s, in universities (UC,Berkeley[1], UI,UrbanaChampaign[2], University of Southern California[3], as well as
a few companies (TI[4], Philips[5]) lead to automated tools to
check intrinsic reliability.
Hot-carrier, gate oxide, electro migration issues
 Targeted at small circuits.

Activity on further development decreased during the late 90s

 In part due to perception of effective reliability control at technology
level.

Usage of these tools typically confined to specific groups

Detailed analysis of tools can be found for example in [6].

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Reliability simulation in CMOS 90 nm design using Eldo

Reliability simulation
Advanced technologies and newer aging issues (such as
NBTI [7]) have recently renewed interest amongst both
technology and design communities to have a DiR solutions.
Increasingly, there is a push to have reliability analysis
methodology integrated into the design flow.
Designers increasingly aware and uncomfortable with reducing
reliability margins
 Seek more quantitative and relevant reliability guidelines.
 Tools preferred where available.

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Crolles

Reliability simulation in CMOS 90 nm design using Eldo

Reliability simulation integration into

design methodology
Robustness and integration into SPICE models.
SPICE is the sole representative of the actual device that a
designer has.
 Many physical effects have begun to be packed within SPICE
definition (Process corners, mismatch, mechanical stress, )

The device model parameter definition is quite complex

 Uses subcircuits
 Actual parameters are derived from several interlinked
coefficients

The coefficients associated to reliability are an additional but

independent part of SPICE model
 Enable simulation with or without reliability

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Crolles

Reliability simulation in CMOS 90 nm design using Eldo

Reliability Simulation Flow

Reliability model (Eldo UDRM)

Extended model card

Reliability
parameters

Standard BSIM model

Description of
Transistor Stress
as function of
Activity

Description of BSIM
parameters
evolution as
function of Stress

Extra object Library

Simulate Aged

Netlist

Aged Results

Simulate Fresh

Comparison

Model Parameters
(Fresh)

Updated BSIM3/4
parameters

Aging related
commands

Nominal Results

Stress analysis

Eldo

Stress File

Optional

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Reliability simulation in CMOS 90 nm design using Eldo

Stress assessment 1/3

Minimal overhead for the designer
Ease of use: just add the .AGE command
Minimum CPU time impact using on-the-fly processing
 No need to store large amounts of data
 No separate time required for reliability analysis.

Eldo UDRM (User Defined Reliability Model)

Flexible modeling: model implemented via an API and
compiled into an Eldo dynamic library
models can be updated with the latest developments on the
physics/experimental front
 Important, since the physical understanding of the phenomenon
such as NBTI is continuously evolving
 Saturation after long durations of stress
 AC effects
 Spice Degradation components, etc

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Crolles

Reliability simulation in CMOS 90 nm design using Eldo

Eldo UDRM API - access functions

The API provides read access functions to
instance parameters (W, L)
usual quantities (Vdsat, Vth, Isub)
parameters of the stress model (user defined,
unlimited)
parameters of the parameter update model (user
defined, unlimited)
global variables (simulation time, temperature)

and read/write access functions to

model parameters (VTH0, U0)
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Reliability simulation in CMOS 90 nm design using Eldo

Eldo UDRM API - required functions

User-defined functions required to fully define
an aging mechanism :
register parameter names and default values for
the stress model
register parameter names and default values for
the parameter update model
define the equations of the stress model (Eldo
handles the integration automatically)
define the equations of the parameter update
model

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Reliability simulation in CMOS 90 nm design using Eldo

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Stress assessment 2/3

 During reliability simulation, the device parameter evolutions are
computed according to the operating condition, and the transistor is
simulated with the modified SPICE parameter set to represent
degradation.
Simulate for a unit cycle
of the given input vector

Working Principles

Take the operating points and

estimate the degradation(Age)
Stress = t * f(operating conditions)

The Stress is modeled

linearly with respect to t
-ease of integration

LINEARIZATION
INTEGRATION

Extrapolate
degradation at the
requested time

Degradation(t) = (Stress) n

Stress = Age f(operating conditions) dt

T 0
where T is the time of the unit simulation,
and Age is the desired time for the reliability simulation

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Reliability simulation in CMOS 90 nm design using Eldo

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Stress assessment 3/3

Limitless number of stress vectors
Can be used to store additional data during the
stress analysis
 Stress analysis can be made more complete and closer to
the physical reality by storing some important information
during the stress assessment for later sets of simulation runs
 The second set of simulations (performance impact
assessment) are entirely independent from the first simulation,
except for the stress file.
 By storing the conditions of stress, certain decisions can be
made during the second simulation run
e.g., saturation of degradation

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Reliability simulation in CMOS 90 nm design using Eldo

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Design in Reliability Impact Assessment

During the subsequent simulation run(s), the BSIM3 or BSIM4
model parameters specified through the UDRM are updated to
reflect the characteristic of the aged device
Flexibility in analysis: the subsequent simulation can be in a
different operating mode than the first simulation via the stress file
loading
The calculated stress is stored in a simple file and can be used for multiple
aged simulations
For designers, it is helpful to assess performances in different modes of the
circuit
For reliability model developer, it helps to verify impact of model parameter
update.
Simulation Mode 1
Fresh

Simulation Mode 1
Aged

Simulation Mode 2
Aged

Simulation Mode 3
Aged

Stress File

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Reliability simulation in CMOS 90 nm design using Eldo

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Negative Bias Temperature Instability

NBTI is a DC stress

Without any requirement of mobile carriers

Proportional to applied Vgs and Temperature
Causes uniform degradation across the oxide interface
Causes change mainly in the linear parameters (Vth and mobility
related parameters)
No geometry dependence
Phenomenon complicated with evolving findings with respect to
mechanism, behavior and model [8 ],[9 ]
The details of the simpler version of the NBTI model spelt out here.

NBTI Model

D = e Vgs e Ea
T

Integral form
Spice Parameter update
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Stress

= N

( * e Vgs * e

/ kT

Ea
kT

Lm t n

* L m ) 1 / n dt

P = C 1 * ( Stress ) n

Reliability simulation in CMOS 90 nm design using Eldo

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NBTI degradation simulation

Vth evolution with time

DVth (a.u)

Vgs1
Vgs2
Vgs3

Ids(a.u)

I-V linear regime: impact of stress

Fresh Id-Vd
Degraded Id-Vd

0
1

10

100

1000

time(s)

10000

0.2

0.4

100000

0.6

0.8

1.2

Vgs(V)

Vth is used to monitor the degradation

Parameters seen to change (depending on device family)
Vth, u0, ua, nfactor
Saturation regime changes as well as length dependence
seen to arise directly from the changes in the above
parameters

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Reliability simulation in CMOS 90 nm design using Eldo

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Example of simulation results

Tpd fresh

Tpd aged

Delta: 56ps

Buffer - Delay Increase

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Delta
Threshold
>20 mV

IO Input - Threshold change

Reliability simulation in CMOS 90 nm design using Eldo

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Conclusion
Eldo UDRM an open model for reliability simulation
Scope to include effects arising due to specificity of degradation
 Relaxation
 AC effects
 Long term saturation

Implementation for different device families from the

90nm node onwards at ST
Designers can now quantify the reliability assessment of circuit
blocks.

NBTI model evolving. Interface open to consider the

new effects.

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Bibliography
[1] C.Hu,IC reliability simulation, IEEE J.Solid State Circuits, vol.27, March 1992, pp241-246
[2] Y.Leblebici and S.M.Kang, Simulation of MOS circuit performance degradation with
emphasis in VLSI design-for-reliability, Proc.1989 IEEE ICCAD, October 1989, pp492-495
[3] B.J Sheu et al, An integrated circuit simulator RELY, IEEE J.Solid-State Circuits, vol 24,
April 1989, pp.473-477
[4] S.Aur et al, HOTRON A circuit hot electron effect simulator, Proc. 1987 IEEE ICCAD,
November 1987, pp 256-259
[5] MM Lunenborg et al, PRESS, A Reliability Circuit Simulator with Built-In Hot-Carrier
Degradation Model, Conf Proc ESREF, Bordeaux/Arcachon, France, October 1993, pp157161
[6] Y.Leblebici and S M Kang, Hot-carrier reliability of MOS VLSI circuits, Kluwer Academic
Publishers
[7] N.Kimizuka et al, NBTI Enhancement by Nitrogen Incorporation into Ultrathin Gate Oxide
for 0.10-um gate CMOS generation, Symposium on VLSI Technology Digest, 2000, pp.9293
[8] V Huard et al, A thorough investigation of NBTI MOSFET degradation , Special Issue on
NBTI, Microelectronics Reliability, in press
[9] M.Denais et al, On-the-fly characterization of NBTI in ultra-thin gate-oxide PMOSFETs, to
be presented, IEDM 2004.

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Reliability simulation in CMOS 90 nm design using Eldo

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