> 300 URLs WELCOME to williamson-labs.

com --HOME > 90 Subjects

DIGITAL LOGIC

Logic Functions using Doors XOR

Logic Functions using Switches Flip-Flops
Positive & Negative Logic Explained Binary : Decimal Explained
Logic Element Symbols Binary Codes
Positive & Negative Logic In Action Glossary

Real World DOs & DON'Ts ! Various Logic Family Specs

LINKS:
Computers
PC:>
.
AND Logic Function using Doors OR Logic Function

Explanation

AND Logic Function using Switches OR Logic Function

Explanation

......
 ..
Positive Logic, Negative Logic Explained using Doors & Switches

In this animated AND Logic example of Doors Opening and Closing, you can see that in order
for the "Light" to get through the house, the front door AND the back door must be Open.

Same example: if either the front door OR the back door is Closed the light does NOT get
through.

In this animated OR Logic example, you can see that in order to get light through the house: the
left front door OR the right front door (or both) must be Open.

Same example: in order to block the light through the house: the left front door AND the right
front door must be Closed.

..

In order for the Output of an AND Logical Function to be TRUE: input (1) AND input (2) must
both be TRUE. This is Positive Logic. Hint: TRUE is when the switch is closed, applying power to the LED. FALSE is when the
switch is open, NOT applying power to the LED)

Truth Table->
A & B are the Input switches
C is the Output LED

Using the Same Function --It is also correct to say: If either input (1) OR input (2) (or both) is
NOT TRUE the Output Will be FALSE. This is Negative Logic.
In order for the Output of an OR Logical Function to be TRUE: either
input (1) OR input (2) (or both) must be TRUE. This is Positive Logic.

Truth Table->
A & B are the Input switches
C is the Output LED

Using the Same Function --It is also correct to say: In order for the Output to be FALSE: input
(1) AND input (2) must both be FALSE. This is Negative Logic.

..

Remember:
1) A Positive AND gate is a Negative OR gate
2) A Positive OR gate is a Negative AND gate

Logic Element Symbols

..
Positive Logic Gates Animate Me Negative Logic Gates TOP
 ..
Exclusive OR (XOR)
In order for the Output of an XOR Logical Function to be TRUE: input (1) & input (2) must both
Different 01, 10. This is Positive Logic.

Truth Table->
A & B are the Input switches
C is the Output LED

Using the Same Function --It is also correct to say: In order for the Output to be FALSE: input (1)
& input (2) must both be Identical 11, 00. This is Negative Logic.

..
Flip-Flop in-- Flip-Flop in-- Flip-Flop in--

Set Reset Mode Toggle Mode Data Mode

..
Binary-Decimal-Real Values
 ..
Binary Codes
Number Decimal Two's One's Sign + Offset
fraction complement complement magnitude binary

+7 +7/8 0111 0111 0111 1111

+6 +6/8 0110 0110 0110 1110
+5 +5/8 0101 0101 0101 1101
+4 +4/8 0100 0100 0100 1100
+3 +3/8 0011 0011 0011 1011
+2 +2/8 0010 0010 0010 1010
+1 +1/8 0001 0001 0001 1001

0+ 0000 0000 0000 1000

0- 0000) 1111 1000 1000)

-1 -1/8 1111 1110 1001 0111

-2 -2/8 1110 1101 1010 0110
 -3 -3/8 1101 1100 1011 0101
-4 -4/8 1100 1011 1100 0100
-5 -5/8 1011 1010 1101 0011
-6 -6/8 1010 1001 1110 0010
-7 -7/8 1001 1000 1111 0001
-8 -8/8 1000) 0000)

..

Glossary TOP

TRUE = 1 = YES = POSITIVE = MARK

FALSE = 0 = NO = NEGATIVE = SPACE

NOT = INVERSION
That is: if a FALSE is Inverted (NOT), it becomes a TRUE
Likewise: if a TRUE is Inverted (NOT), it becomes a FALSE.
A NOT or Inversion is usually indicated by a Bubble, on either the input or the output of a logic
gate symbol.
The convention (which is not always adhered to) is that a POSITIVE Gate Inversion is indicated
by a bubble on the output, and with Negative logic the bubble is at the input.
See Symbol Examples

..
Logic Families' Propagation Delay Specs TOP
 by Charles Toth

..
"Real World" DOs & DON'Ts

What should I do with the UNUSED INPUTS?

TTL devices normally default to a logic ONE if the input is allowed to FLOAT.
However, depending on many factors, these inputs can act as an antenna, and pick up NOISE
which can cause mischief to the circuit. The worst case is, the device will act as an uncontrolled
intermittent OSCILLATOR. --This is BAD!
Therefore:
ALL unused inputs of TTL logic devices IDEALLY should be returned to either a logic ONE or
logic ZERO. Certain devices--74XX and earlier 74LS--the logic ONE (Vcc) should be a ~ 1k
resistor to Vcc; or alternatively, connected directly to ground (ZERO). Most/All other logic
devices, the resistor is UNNECESSARY.
In the case of CMOS devices, there is NO input DEFAULT; CMOS input impedance is on the
order of thousands of MEGOHMS and will cause EXTREME FAILURES if allowed to
FLOAT.
To make this point: if you put your finger or a scope probe on or NEAR an un-terminated CMOS
input, it can cause a logic CHANGE!! If allowed to float, some CMOS devices can oscillate so
fast, that it exceeds the device power rating and will literally destroy itself.
 Unused Outputs: tri-state[1], and open collector devices, etc., DO NOT require any attention.
NOTE: In the case of the tri-state control pin, it should be treated as an INPUT.
Notes [1] Tri-state: Zero, One, Open.

WARNING:
NEVER EVER USE the original generic 7400 DEVICE.
INSTEAD: Use anything else, e.g., 74LS, 74ALS, etc.
The older devices require five to ten times the drive power and force very LARGE amounts of
NOISE on to the Vcc rail! --This is NOT GOOD!
Remember, the newer the technology the happier the circuit will be--well almost!

© Copyright 1999 -- 2007 Questions or Comments: webmaster@williamson-labs.com .

Suggestions are Solicited, P l e a s e !

Chapter 3 Notes
1. 3.1 Representation of binary values
○ Real logic devices receive input and produce output in the form of
voltages.
○ Necessary to define a voltage representation for binary logic values 0
and 1.
○ Positive logic represents True or 1 with a high voltage and False or 0
with a low voltage.
○ Negative logic represents True or 1 with a low voltage and False or 0
with a high voltage.
○ The following repeats the Light switch example, adding voltage
representation.
○ Positive
Negative
○ A B |LIGHT A B| LIGHT Ab Bb| LIGHTb A B| LIGHT A B|
LIGHT
○ Down Down| OFF F F| F 0 0 | 0 L L| L H H|
H
 ○ Down Up | ON F T| T 0 1 | 1 L H| H H L|
L
○ Up Down| ON T F| T 1 0 | 1 H L| H L H|
L
Up Up | OFF T T| F 1 1 | 0 H H| L L L|
H
○ Interestingly, a positive logic OR device also implements a negative
logic AND as seen in the following:
○ Input Output Positive Negative
○ Voltage Voltage Logic Logic
○ x y | z x y | z x y | z
○ L L | L 0 0 | 0 1 1 | 1
○ L H | H 0 1 | 1 1 0 | 0
○ H L | H 1 0 | 1 0 1 | 0
○ H H | H 1 1 | 1 0 0 | 0
OR AND
2. 3.2 Structure and Operation of CMOS gates
○ Can model transistor operation as switch that is opened or closed by a
control voltage. In the left diagram, with the gate to Ground open there
is greater resistance to Ground than to positive Vdd voltage, the
voltage at Output is Vdd. In the right diagram, with the gate to Ground
closed there is less resistance to the Ground than to positive Vdd
voltage, the voltage at Output is low.

Behavior of transistors can be modeled by adding a control voltage to

open or close the gate as in the diagram below. When a high is applied
to the Gate Control Input the gate is closed and Output is connected to
the Ground. When the Gate Control Input is low, the gate is open and
Output is connected to positive Vdd. The two figures below are
equivalent, the right figure replacing the switch representation with
that of a transistor.
○ 3.2.2 Inverter or NOT gate - In the above diagram, a high input
results in a low output, a low input results in a high output. The device
acts as a voltage inverter. Using positive logic the voltage
representation and graphics symbol would be:

○ Gate Control Input | Output x | z

○ H | L 1 | 0
L | H 0 | 1
○ Circles are commonly used to represent an active low input. In the
below diagram, the circle on the Gate Control Input indicates that
when the input voltage is low the gate is closed and when high the
gate is open. This notation is for an p-MOS transistor. The notation for
an n-MOS transistor has no circle as in the above diagram.

○ 3.2.3 Other Logic - Other popular logic devices such as AND, OR,
NAND, NOR, etc. can be constructed. The following device must have
both A and B input high to connect the Output to Ground or low. If
either A or B is low, then Output is connected to Vdd or high voltage.
Using positive logic it is a NAND gate, negative logic it acts as a NOR.
AND OR NAND NOR

+ | - - | + + | + - | -
Voltage
A B | A B | A B | A B |
A B | Output
Output Output Output Output
L L | H
0 0 | 0 1 1 | 1 0 0 | 1 1 1 | 0
L H | H
0 1 | 0 1 0 | 1 0 1 | 1 1 0 | 0
H L | H
1 0 | 0 0 1 | 1 1 0 | 1 0 1 | 0
H H | L
1 1 | 1 0 0 | 0 1 1 | 0 0 0 | 1
○ The following device, when either A or B are high, Output is low. Using
positive logic it is a NOR gate, negative logic it acts as a NAND.

OR NOR NAND
AND

- | - |
+ -
A B | A B |
+ | - + | +
Voltage Output Output
A B | A B |
A B | Output 1 1 | 1 1 |
Output Output
L L | H 1 0
0 0 | 0 0 0 | 1
L H | L 1 0 | 1 0 |
0 1 | 1 0 1 | 0
H L | L 0 1
1 0 | 1 1 0 | 0
H H | L 0 1 | 0 1 |
1 1 | 1 1 1 | 0
0 1
0 0 | 0 0 |
0 1

○ 3.2.4 Positive Logic AND and OR - Constructed by adding an

inverter to a positive logic NAND or NOR.
AND OR
○ 3.3 Propagation Delays, Transition Times, and Effect of Load
Propagation delay is the time between when the device input changes
to when its output changes. For a NOT gate, when the input is 1 the
output is 0, if the input changes to 0 the output changes to 1.
However, the change is not instantaneous, depending upon the
technology used for the gate, it the gate responds at different rates.
The technology mostly used for this course has a propagation delay for
a NOT gate of 7.5 nanoseconds as illustrated in the following
simulation diagram. The input A changes and the output NOT A does
not change for 7.5 ns.

○ In contrast to the
simulation
showing that input
and output
voltages change
instantly from low
to high or high
to low, due to
capacitance
(charging and
discharging of the
device), the inputs
and outputs require time to reach low or high voltage. The time to
propagate a high to low change is tpHL and the time to propagate a low
to high change is tpLH. The propagation time usually considered the
interval from 50% of the input signal change to 50% of the output
signal change. The diagram of A input and NOT A output at right
illustrates this behavior. Because device charge and discharge times
may differ, tpHL and tpLH may differ, though generally the greater the
capacitance, the greater the propagation delay.
○ Unfortunately propagation delays are cumulative in a series of gates. If one NOT
gate delays the signal change by 7.5 ns., two NOT gates in series delay the signal
change by 15 ns., three by 22.5 ns., 4 by 30 ns., etc.

○ Input and Output Loading - An output must drive a voltage for

every connected input. For the same reason that one can connect only
a limited number of appliances to a wall plug before surprising things
begin to happen, logic device outputs can only provide power for a
limited number of device inputs.
○ Fanout - The maximum number of inputs that a device can drive. TTL
(Transistor Transistor Logic) compatible device outputs generally can
drive 10 TTL inputs, CMOS outputs can drive12 CMOS inputs. Individual
device fanout is stated in terms of standard loads, a TTL device with 2
standard loads could drive 20 inputs, a CMOS device with 3 standard
loads could drive 36 CMOS inputs.
○ Fanin - The number of inputs to a device, a two-input AND gate has a
fanin of two. Usually, the larger the number of inputs, the larger the
delay.
○ 3.4 - Voltage Variations and Noise Margin - Devices can operate
reliably only within fixed ranges of input voltages. For CMOS, a high is
above 2.0 volts, a low is below 0.8 volts. In between is forbidden for
reliable operation so during voltage transitions the output is unreliable.

The noise margin is the voltage difference between what the input will tolerate
and what the output produces. A device that requires a minimum high voltage for
input of 2.0 volts and outputs a high voltage of 3.0 volts has a noise margin of 1.0
volts for high.

○ 3.6 Buses and Three-state Drivers - For the devices seen so far,
outputs cannot be connected together. But for busing applications
several devices must supply input on a common wire (computer
systems have many devices connected to the CPU via a common bus).
The devices, in addition to the two binary states where 0 or 1 is output,
can be disconnected from the output. As long as only a single device is
connected to the common wire at a time, there is no conflict. These
very useful devices are known as three or tri-state devices since they
have 0 or 1 state when selected and disconnect state when not
selected (disconnect is represented by Z for high-impedence). The

symbol for a tri-state driver is .

The truth table for a device that outputs its input (0 or 1) when
enabled or disconnects when not enabled is: below on the left, the
device itself is on the right.
 Enabled Input |
Output
0 0 |
Z
0 1 |
Z
1 0 |
0
1 1 |
1

○ Busing - An example of using tri-state devices to connect several

outputs A0, A1, and A2 to the common Output is given below. When
Enable2 = 1, Enable0 = 0, Enable1 = 0, Output is the value of A2
input.