This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2404825, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A Zero-Voltage-Transition Bidirectional
DC/DC
Converter
Serkan Dusmez, Student Member, IEEE, Alireza Khaligh, Senior Member, IEEE, and A. Hasanzadeh
Abstract A three-level (TL) bidirectional dc/dc converter is a
suitable choice for power electronic systems with high voltage dc
link, as the voltage stress on the switches is half and inductor

iS1

S1

vS1

D1
current ripple frequency is twice of the converters switching
frequency. This study proposes a zero-voltage-transition (ZVT)
TL dc/dc converter to enable operation with higher switching
frequency in order to achieve higher power density and enhance
efficiency. Two identical ZVT cells, each one composed of two
resonant inductors, a capacitor, and an auxiliary switch are
integrated with the conventional TL topology to enable softswitching in all four switches in both buck and boost operation
modes. In addition, a variable dead-time control is proposed to
increase the effective duty ratio at heavy loads. The proposed
soft-switching feature has been demonstrated under different

loading conditions. A 650W prototype is designed and fabricated,

which exhibits 95.5% at full load.

Lr

iLi

Lin

1 Sa1

Lr2

va

Co
1

Vco1

Da1

iLr
2

iS2

Vin

S2

D
2

S3

D3

vS2

Vo

+
vS3

ZVT Circuit 2

transition cell, non-isolated dc/dc converter, power electronics.

Lr3

INTRODUCTION

In bidirectional non-isolated buck/boost dc/dc converter

applications, a two-quadrant non-isolated buck/boost
converter has been preferred in many studies due to its simple
two-switch structure, low cost, and high efficiency [1]-[6].
However, in high-voltage (400V-600V) and medium to high
power applications such as the dc/dc bidirectional converter in
electric vehicles (EV), two-switch structure exhibits several
shortcomings; 1) low efficiency at light load due to high
power losses associated with the parasitic capacitances of the
switches, 2) utilization of IGBTs instead of MOSFETs in high
voltage applications, while switching frequency of converter is
limited by the IGBTs maximum switching frequency under
hard-switching. As a result, the passive components such as
the inductors and capacitors render a large volume. To
increase the input current ripple frequency, interleaved
structures are studied [7]-[9]. Interleaving reduces the size of
the passive components, however; still requires high voltage

vcr

Cr

Index Terms--Bidirectional three-level converter, zero-voltage-

I.

ZVT Circuit 1
icr1
iLr1

Lr

Co

vcr2

Cr
2

Sa2

Da2

Vco2

va2

S4

D4

vS4

Electrical and Computer Engineering Department, University of Maryland,

College Park, MD 20742 USA.
A. Hasanzadeh was with the Power Electronics, Energy Harvesting and
Renewable Energies Laboratory, Electrical and Computer Engineering
Department, University of Maryland, College Park, MD 20742 USA.

Manuscript received June 22, 2014; revised September 22, 2014;

accepted October 12, 2014.
Copyright 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
This work was supported in part by the NSF ECCS under Grant 1307228,
and the Genovation Cars Inc, which are gratefully acknowledged.
S. Dusmez was with the Power Electronics, Energy Harvesting and
Renewable Energies Laboratory, Electrical and Computer Engineering
Department, University of Maryland. He is now with the Electrical and
Computer Engineering Department, University of Texas at Dallas,
Richardson, TX 75080 USA.
A. Khaligh is the Director of the Power Electronics, Energy Harvesting
and Renewable Energies Laboratory, Institute for System Research and
0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2404825, IEEE Transactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Fig. 1. Proposed bidirectional three-level dc/dc converter with auxiliary

ZVT cell.

rating switches. In order to equally distribute the voltage

stress among the switches, and to use MOSFETs at high
voltages while still increasing the inductor current ripple
frequency to twice of the switching frequency, a threelevel (TL) output voltage buck/boost dc/dc converter
has been proposed and suggested for use in high voltage
applications [10].
To increase power density through higher switching
frequencies without sacrificing converter efficiency, softswitching techniques are employed [11]-[13]. A common
way to achieve soft-switching is to use interleaving
circuits where the stored energy in the interleaving
inductor is used to discharge the parasitic capacitances of

2
the switches [14]-[17]. Similarly, an auxiliary inductor can
be coupled to the main inductor to reduce the cost of the
circuit [18]-[23].
Another method to effectively achieve soft-switching is
through employing auxiliary switch to store the switching
energy in the auxiliary capacitor, which is then used to softswitch the main switch either during turn-on or turn-off
instants. Soft-switching cells, consisting of an auxiliary
switch, a resonant inductor and a capacitor, are common [24][27]. In [24], the soft-switching cell is used to turn off the
switch under zero current, and turn on the auxiliary switch
under near zero current. Another ZCS was introduced in [25]
for boost converter, which is then generalized for other
converter types such as buck, buck/boost, SEPIC, and Cuk. In
[26], unified analysis for these soft-switching cells was

0278-0046 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

Lin

Lin
Lr2

Sa1

S2

C2

S3

C3

Vin

S2

Lr3

C2

D1

Sa1

C2

S3

Lin

D1

S3

D3

Sa1

Lr2

Vin

Lr3

(d)

D1

S1

Cr

Lr1

Da1

Lr2

S2

Co

C2

(c)

S1

Cr

S2

Vin

D3

(b)

Lr1

Da1

Lr2

Lr3

(a)

Lin

Sa1

Da1

Co1

Cr

Lr1

D3

Lr3

S1

Lin

Sa1

S3

Co

Cr

Lr2

Vin

D1

S1

Lr1

Da1

S2
C2
S3

Vin

Lin

Lr2

Vin

Co

Cr

Lr1

D1

S1

C1

S1

Co

Lin

Sa1

Da1

S2
C2

Cr

Lr1

Lr2

Vin

S2
D2

S3

D3

Lr3

Lr3

(f)

(e)

Co

Lin

D3

Lr3

(g)

Co1

Sa1

Da1

Lr2

S2
S3

S3

Cr

Lr1

Vin

D3

D1

S1

Da1

D2
D3

Lr3

(h)

Fig. 2. Operation intervals and equivalent circuits; (a) Operation interval 1: t<t0, (b) Operation interval 2: t0<t<t1, (c) Operation interval 3: t1<t<t2, (d) Operation
interval 4: t2<t<t3, (e) Operation interval 5: t3<t<t4, (f) Operation interval 6: t4<t<t5, (g) Operation interval 7: t5<t<t6, (h) Operation interval 8: t6<t<t7.
TABLE I. SUMMARY OF THE ZVT OPERATION.

Boost mode
Buck mode

Resonant
Inductor

Auxiliary
Switch

ZVT
Switch

Lr2

Sa1

S2

Lr3

Sa2

S3

Lr4

Sa2

S4

Lr1

Sa1

S1

explored. In [27], a similar soft-switching cell used in this

paper has been proposed for bidirectional non-isolated

switching cells are deployed for each pair of switches,

ensuring that all four switches are turned on under zerovoltage in both boost and buck modes. Thus, the proposed
ZVT TL converter can be operated at higher switching
frequencies, the input current ripple frequency can be doubled,
and the size of the inductor can be significantly reduced.
The common issue with the soft-switching converters is the
limited soft-switching operation range due to the output
buck/boost dc/dc converter. Yet, no soft-switched non-isolated
TL converter has been explored in literature.

Reducing the switching losses is critical to achieve higher

efficiency. In this regard, this manuscript proposes a zerovoltage-transition TL bidirectional dc/dc converter for wide
load range, as illustrated in Fig. 1. Two identical soft-

current dependency of the soft-switching operation. When the

ZVT cell designed for light load condition operates under
heavy load, the effective on-time of the switches becomes less
than the reference. To partially compensate this negative effect
on the duty ratio of the main switch, the auxiliary switch is
controlled through adjusting the dead-time with respect to
peak inductor current. The improvement on the effective duty
ratio using the proposed variable dead-time control is analyzed

t01 t
1

t23

t34 t45

t67

t5
6

vgs2
vgsa1
iS1
iS2
iCr1

iLr1
iLr2
vS1
vS2
vCr1
vLr1

vLr2
t0 t1 t2

t3 t4 t5 t6 t7

Fig. 3. The switching scheme and circuit waveforms of the proposed ZVT converter.

and compared with the conventional fixed dead-time approach

within the content of the manuscript. Even though, the
improvement on the duty ratio is analyzed in this paper, the
proposed technique is a possible solution for secondary
control objectives, such as capacitor voltage balancing.
II.

PROPOSED BIDIRECTIONAL ZVT TL DC/DC CONVERTER

The proposed converter achieves ZVT for all the switches

during turn-on instants in all operation modes. The ZVT cell
contains two resonant inductors, one resonant capacitor and an
auxiliary switch to eliminate the turn-on losses of switches by
creating a resonance between the inductor and capacitor. The
energy stored in the auxiliary inductor during the normal
operation, is transferred to the capacitor when the main switch
is turned off. This energy is then recycled through the bodydiode of the main switch before it is turned on. An identical
ZVT cell is placed between switches S3 and S4 to soft switch
the bottom two switches. The basic operation principle of the
ZVT cell is identical in each transition mode for both boost

and buck operations. Table I summarizes the ZVT cell

operation depending on the buck and boost modes, used
resonant inductor, auxiliary switch and soft-switched
MOSFET.
The equivalent circuits and operation waveforms are given
in Fig. 2 and Fig. 3, respectively. Here, the operation principle
will be given for turning-on instant of S2 in boost mode when
d>0.5. It should be noted that Lr3 is not involved during this
switching-state transition and can be assumed as an additional
contributing inductance to Lin. For the sake of the symmetrical
operation, the resonant inductors are chosen equal, Lr1=Lr2
Lr3=Lr4=Lr.
Operation interval 1 [t < t0]: Before t0, both S2 and S3 are on,
Lin stores energy, and converter operates in boost operation
mode of the TL converter. In this mode, iLr1(t0)=0. If on-time
of the auxiliary switch is equal to the quarter of the resonance
period, the resonant capacitor voltage becomes zero at t0,
(vCr1(t0)=0). This will be explained in latter sections. The
current of Lr2 is equal to

iLr 2 t
i

Li

t7 n

Lr
2

(1)

Vin
t

2Lr

This time interval is determined by the effective on-time duty

ratio of S2.
Operation interval 2 [t0 t < t1]: At t=t0, S2 is turned off. The
current of Lr2 begins to resonate in the resonance tank
composed of Lr1-Lr2-Cr1. The sum of the voltages of the
inductors vL1+vL2 is equal to vcr1. During this short time
interval, the parasitic capacitance of the upper switch, C1,
discharges over the output capacitor, and transfers its energy
while C2 is charged as vS1(to)=Vo/2, and vS1+vCr1+vS2 =Vo/2
during t01. The initial conditions can be noted as
i

Lr 2

Lr 2

Vin

t
2

2L

L
in

iLr1 t0 0

Operation interval 5 [t3 t < t4]: Before S2 is turned on, the

auxiliary switch, Sa1, is turned on to transfer the energy stored

in the capacitor to the resonant inductor, iLr2. Sa1 is turned on

under zero-current, thus there is no switching turn-on loss for
the auxiliary switches. vLr2 is half of the vCr1 and iLr2 increases
sinusoidally. C2 is first quickly charged to vCr1+Vo/2, then is
discharged as vCr1 decreases. At t=t3, the initial conditions are
as follows; iLr2(t3)=0, vcr1(t3)=vcr1(t2). In this interval, the
resonant inductor currents and capacitor voltage are
vCr1 t vCr1 t3 cost
(13)

iLr 2 t CrvCr1 t3

70
r

vCr1 t0 0

(4)

get charged. This interval occurs very quickly as C1 is

typically in the order of several hundreds of pF, and is not
included in the calculations for simplicity. The energy stored
in Lr2 is transferred to resonant capacitor Cr1 through Da1. For
this interval, the resonant inductor currents can be expressed
as
(6)

(8)

Cr1

34

t sint

Cr1

(15)

(16)

At the end of this mode,

vCr1(t4)=vCr1(t0)=0.
Operation interval 6 [t4 t < t5]: When the energy stored in
the resonant capacitor is completely transferred via Sa1, C2
quickly discharges to zero. This time interval can be expressed
as

t45 2Lr iLr

2

CV2
2 o
2L

iLr t
2

t4

(17)

Vo

At t=t5, the current of D1 increases to approximately twice of

the load current.
Operation interval 7 [t5 t < t6]: When vS2 reaches to -0.7V,
the body diode of S2 conducts. This time period is the ZVT
period. S2 can be turned-on at any time during this interval. At
t=t5, the initial conditions are
2

C v

Lr1

r1

5 Lr1 4
Lr 2

t i

Cr1

r1 Cr1
2L 4

(18)

t sin
t

(19)

Vo

(20)

t
4Lr
V
Lr1
t5 o

(21)

t C
v

vLr2 is equal to Vo/4, and iLr2 decreases linearly.

At t=t2, iLr2 becomes zero as it transfers all its energy to the

resonant capacitor.

From this final state condition, t02 can be found as

(7)

Cr1

iLr2 t2 0

Lr1

(3)

Operation interval 3 [t1 t < t2]: C1 is discharged completely

at the end of operation interval 2, as current begins
commutating from Lr2 to Lr1, and D1 conducts. C2 continues to

cost
iLr1 t iLr 2 t0 1
cost
i t0 be written as

The resonant capacitor

v sint voltage
t
Lr 2 can

vt C

Lr1

The natural frequency of the resonant tank is expressed

(5)
as
1

2Lr Cr1

iLr 2 t iLr 2 t0

sint

i i
t

(2)

(14)

(9)

iLr 2 t iLr t5

iLr1 t

t
02

4Lr

(10)

Operation interval 4 [t2 t < t3]: At t=t2, the resonant

inductor current iLr1 is same as iLr2(t0). The resonant capacitor
voltage can be found from the energy transfer between vcr1 and
iLr2 as
v t
2
2Lr
t
(11)
Cr1

i
Cr1

Lr 2

Operation interval 8 [t6 t < t7]: This interval starts after the
main switch S2 is turned on. At t=t6, the main switch S2 is
turned on while its body diode is conducting. The zerovoltage-transition can be achieved at this instant. With the
assumption of negligible t45 in comparison to t56, t46 t56; the
ZVT time interval can be expressed as
4Lr iLr 2 t6 iLr 2 t5
t56

(22)

V
o

The energy stored in vcr1 will be used to achieve soft-switching

in latter stage. In this time interval, the resonant inductor
current iLr1 can be written as

First, the current of the body diode of S2 reaches to zero. In

this time interval, S2 begins to conduct, and input current
commutes from Lr1 to Lr2. At t=t6, iLr1 is
iLr1 t6 iLr t5 V t56
(23)

4
L
i
Lr1

t i
t

Lr1

2t

Vo / 2 Vin

L L

in
r

(12)

The resonant inductor currents for this interval can be

expressed as

iLr1 t

Lr1

t
iLr 2 i

t
t

Lr
2

(24)

Vo

tdt=0
Fixed Dead-time

t67 = DLTS

t45

4Lr
V
t6 o
t

(25)

Vgs2
Vgsa1
tm
(a)

At t=t7, the input current commutation from Lr1 to Lr2 is

completed, and iLr1 becomes zero. This time interval can be
expressed as
4Lr iLr 2 t7 iLr 2 t6
(26)
t67

Vo
III. DESIGN CONSIDERATIONS FOR ZVT FEATURE

The time between the turning-off action of Sa1 and turningon action of the main switch S2, denoted by t46, should be as
short as possible to achieve ZVT with smallest amount of
energy stored in the resonance tank. This would minimize the
size of the resonant tank elements and allows achieving higher
efficiency as the circulating current in the resonant tank would
be less. To achieve ZVT, the auxiliary switch should be turned
on at least t36 before the main switch is turned on. It should be
highlighted that t34 is the time duration in which the stored
energy in the auxiliary capacitor is transferred to the auxiliary

Is1
Is2

Vgs2

t45
tm=0
Variable Dead-time Control

Vga
Is1
Is2
t67 = DLTS
tdt
(b)
Fig. 4. Illustration of ZVT operation with fixed and variable dead-times for
evaluation of t67; (a) fixed dead time, (b) variable dead-time.

2L

(30)
inductor, t45 is the time required to discharge the parasitic
vcr1 t2 iLr 2 t0
Cr1
capacitance of the switch. For ideal case, the minimum
required time is t35. t56 is the time duration added to guarantee
B. Variable Power Loads:
the soft-switching of the main switch taking the mismatch
From Eq. (27), it can be observed that the ZVT feature is
between the actual and datasheet values of the switch.
dependent on the load current as it determines the stored
Considering this added time margin, the auxiliary switch
energy in the resonant inductor. Therefore, for wide load range
should be turned on at least t36 before the main switch is
applications, the minimum input current at which ZVT feature
turned on. Once t46 is determined, Lr can be calculated
is desired should be determined for the given application.
accordingly.

tZVS tdt
tm

A. Constant Power Loads:

(31)

The minimum value of Lr can be determined for constant

power loads with predefined Po, Vo, Vin, Lin, and steady-state
duty ratio (D). For simplicity in calculations, it is assumed that
iLr2 does not vary during t45, and |iLr2(t5)|=|iLr2(t0)|, which
yields to
Vo
L
t
r
46
(27)
4i t

where, tdt denotes the selected dead-time, and tm is the time

margin, representing the time from turn-on instant of the main
switch till iLr2 becomes zero, and should be included in the
calculations ensuring that the switch is switched under zerovoltage. Minimum Lr for variable power loads can be
determined as
V
o
(32)
Lr
t tZVT
4i

In order to have zero voltage across Cr1 from t=t4 to t=t0, the
reverse resonance time, t34, should be equal to the one fourth
of the natural resonance period, t02, which is initiated by
turning on Sa1. If t34 is forced to be shorter than t02, vCr1(t0)
would be higher than zero. Cr1 can be calculated from Eq. (5)
and Eq. (10), by equalizing t34 and t02 time periods, as

In case the auxiliary switch is turned off tdt seconds before the
main switch is turned on, D1 would conduct for the time
duration of tZVT.
The selected Lr should be sufficiently large to achieve softswitching for S2 at minimum load current. However, the
selected Lr would cause losing effective on-time of the switch
as the load gets heavier. This issue has been illustrated in Fig.
4(a). Here, it is assumed that the load current is larger than
I_min, and Lr is found using Eq. (27) for the ideal case,
assuming tdt=0. As it can be seen from the figure, the
reduction in the duty ratio, denoted by DL, increases under

Lr 2
0

Cr 1

(28)
L
Since two quarter resonance periods take place during the offtime of the switch, the sum of them should be shorter than (1D)Ts, where Ts represents the switching period.
r

t 02

Lr 2

t 02

Ts 1
D

(29)

As the quarter resonance period t02 increases, the required

capacitance also increases while the voltage stress on S2
reduces. The additional voltage stress across S2 is equal to that
of vcr1(t2), and can be expressed as

heavy load. The reduction in the duty cycle should be

compensated similar to dead-time compensation applied in
three-phase inverters [28]. To reduce this effect, the phase of
the gating signal of the auxiliary switch should be varied such
that the main switch is turned on right before the current of the
main switches body diode reaches to zero.
In this regard, a variable dead-time control is proposed in
this paper, as shown in Fig. 4(b). The gating signals for the

TABLE II. DESIGN PARA METERS

Output Power (Po)
Output Voltage (Vo)
Input Voltage (Vin)
Input Inductor (Lin)
Switch Parasitic Capacitance (Coss)
Switching Frequency

several nanoseconds. The variation of t45 at minimum load

current according to Lr is plotted in Fig. 5(a) for maximum and
minimum output voltages. As the output voltage increases,
more energy is stored in the parasitic capacitances of the
switches, which extends the discharge time to 5 ns. At
Po=250W, the dead-time, tdt, is chosen as 30 ns. This would be
5 ns for ideal case; however, it is reasonable to insert a deadtime to ensure that soft-switching will be robust to the

650W-250W
200V-180V
100V
100H
120pF
200kHz

TABLE III. ACQUIRED DATA FOR ZVT OPERATION

t57/2 [ns]
D [%]
Fixed Dead-time
tdt [ns]
t67 [ns]
DL [%]
Variable Dead-time
tdt [ns]
t67 [ns]
DL [%]

Vo,min
Po,min
55
44

Vo,min
Po,max
145
44

Vo,max
Po,min
50
50

Vo,max
Po,max
130
50

30
80
3.6

30
260
11.6

30
70
2.8

30
230
9.2

35
75
3.4

125
165
7.4

30
70
2.8

1
1

auxiliary switches are practically achieved by right-aligned

pulse-width-modulation (PWM) signal with inserted fixed
dead-time. At heavy loads, instead of turning off the auxiliary
switch with fixed tdt seconds, before the main switch is turned
on, the discharging of resonant capacitor can be initiated
earlier by adjusting the dead-time between the main and
auxiliary switch signals. Hence, the resonant inductor current
crosses zero tm seconds after the main switch is turned on. At
ideal case, tm=0, this could reduce DL to DL/2 as illustrated in
Fig. 4(b).
It is important note that the proposed variable dead-time
approach can be used for achieving supplementary control
objectives such as dc link capacitor voltage balancing. The
variable dead-time has not been considered in any softswitching literature because it may not be necessary in twolevel converters. One of the difficulties in three-level
converters is the unbalanced dc link capacitor voltages, which
may occur due to the unsymmetrical circuit layout, differences
in the ESR of capacitors, delays in the gate driver circuit, etc.
The unbalanced voltage problem could be solved by
controlling the duty cycles of the main switches
independently, letting capacitors charge/discharge more or less
with respect to the other dc link capacitor. However, the
common approach is to use the same PWM duty cycle
generator for both of the switches due to its simple control and
more importantly for stable operation. In this regard,
developed secondary variable dead-time control can be
adopted to balance the dc link capacitors as well as contribute
to the duty cycle compensation, correcting the unbalanced
ZVT current injection due to unsymmetrical ZVT circuit
parameters and so on. However, in this paper, only partial duty
cycle compensation has been studied and capacitor voltage
balancing is out of the scope of the paper.
C. Example Application
This section provides a ZVT cell design procedure for a
variable power load. The example design specifications are
provided in Table II. The converter operates in CCM at full
load range.

mismatch of the actual and datasheet values as well as to

compensate the previous simplifications. Since the switching
period is 5 s and considering the turn-on and turn-off time of
MOSFETs, tm is chosen as 20 ns to ensure the auxiliary switch
turns off 30 ns before the main switch is turned on. In this
way, the resonant current will become zero after tm+tdt=50 ns.
The ZVT time period corresponds to 1% of the switching
period. The reduction in the duty cycle, t67/DTs, can be
expressed as
tdt 2tm
D
L

DT

(33)

To find Lr, worst condition should be considered; that is

Po=Po,min and Vo=Vo,max. Assuming that Lin is large enough and
input current is constant, iLr2(t0) in Eq. (32) can be
approximately equal to the input current. For this example, Lr
is calculated as 1 H. The highest ZVT time, t57/2, is 50 ns for
minimum load at Vo=Vo,max. At maximum load, the ZVT
period increases to 130 ns. For Vo=Vo,min, the ZVT period for
minimum load is 55 ns, and at maximum output power it
increases up to 145 ns. The same amount of time is required
for the main switch current to reach to the input current, t57/2.
For a fixed tdt of 30 ns, t67 can be calculated using t57-tdt as 70
ns and 230 ns for lightest and heaviest load conditions at
Vo=Vo,max, respectively. Similarly, when Vo=Vo,min, t67 becomes
80 ns and 260 ns for lightest and heaviest load conditions,
respectively.
In CCM mode, the duty ratios for Vo=Vo,min and Vo=Vo,max
are 44% (corresponding to 2.22 s) and 50% (corresponding
to 2.5 s). Using Eq. (33), DL is calculated as 3.6% and 11.6%
for light and heavy load conditions at Vo=Vo,min, respectively.
Similarly, for Vo=Vo,max it is calculated as 2.8% and 9.6%,
respectively. Using the proposed variable dead- time
approach, DL can be reduced effectively as shown in Fig. 5(b).
The dead-time curve used to accomplish DL reduction is given
in Fig. 5(c).
The acquired data is summarized in Table III. It can be seen
that DL is reduced from 11.6% to 7.4% for low output voltage
and heavy load conditions. If tm is chosen smaller at the initial
step, DL can be reduced even further, to half of DL value with
fixed dead-time at ideal case, when tm=0. However, further
duty cycle compensation is still required.
Once tdt and Lr are determined, Cr can be determined from
Eq. (28) and Eq. (29). As mentioned before, the pulse-width of
Sa1 should be equal to t02 to have zero voltage across vcr at t=t0.
When a dead-time is inserted, Eq. (29) should be modified to
incorporate tdt.

The first design parameter to be determined is the tZVT. As

discussed previously, t45 is relatively short, in the order of

t02

Ts 1D

t
dt
2

(34)

12
Vo,max

5
Vo,min
4

dtc:dead time
compensation

10

Vo,max(w/o dtc)

8 Vo,min(w/o dtc)
6

4
3
0

0.5

1.0
1.5
Lr [H]
(a)

2.0

2.5

dtc:dead time
compensation

140
Required dead-time [ns]

Duty Cycle (DL) [%]

Discharge Time of Parasitic Switch, t45 [ns]

Vo,max(with dtc)
Vo,min(with dtc)

120
dtc)

80
60
40

20
0

2
250 300 350 400 450 500 550 600
Output Power [W]
(b)

Vo,min(with

100

Vo,max(with dtc)
100

200

300
400
500
Output Power [W]
(c)

600

Fig. 5. Curves for the ZVT operation; (a) Switch parasitic capacitance discharge time according to various Lr, (b) reduction in effective duty ratio for various
output powers when Lr=1 H, (c) required dead-time for the proposed variable dead-time control at various output powers.

200
TABLE IV. COMPONENT PARAMETERS

250
160

200

VCr [V]

120
150 Cr
[n

80

300

500
700
t02 [ns]

900

Aux switch
Sa1&Sa2
-

50

D1&D4

1100

Fig. 6. Capacitance and voltage stress variation of the resonant capacitor at

various t02 values.

The highest tdt is achieved when output power is maximum,

and output voltage is lowest. However, for this case, Ts(1D)/2-tdt for Vo=Vo,max condition is smaller; hence, t02 should be
determined based on maximum output voltage. This
determines the upper bound for choosing t02, which is
calculated as 1.14 s. The variation of capacitance value and
voltage stress of resonant capacitor for various t02 from 0.1 s
1.14 s, is given for heaviest load condition in Fig. 6. Here,
Cr can be determined based on the tradeoff between the
capacitance value and the voltage stress. In addition, there
should be sufficient margin for duty cycle compensation. Once
t02 is determined, the duty ratio of Sa1 can be found by dividing
t02 by Ts.
IV. SIMULATION AND EXPERIMENTAL RESULTS

In this section, simulation and experimental results are

provided to verify the operation of the converter. The
switching frequency of the main and auxiliary switches is 200
kHz, where the frequency of the inductor and output capacitor
current ripples is 400 kHz. The resonant inductors, Lr, are 1
H and the resonant capacitors, Cr, are 100 nF each. Only
boost operation mode is presented in here, as buck operation is

Soft-Switched ThreeLevel Converter

FQPF16N25
250V/9.5A

FQPF16N
25
250V/9.5
A
FQPF6N25

Main switch
S2&S3

100 F]

40

Hard-Switched ThreeLevel Converter

250V/4A
Body Diodes

Lin

100uH

100uH

Co

470uF x 2

470uF x 2

Lr

1uH x 4

Cr

100nF x2

capacitor voltage is almost zero. The simulation waveforms

agree with the theoretical analysis.
The simulation waveforms for boost operation utilizing
non-ideal switches when d=0.4, are presented in Fig. 7(c).
From the figures, it can be clearly seen that Coss of the
switches, particularly that of the auxiliary switches, causes to
form a resonant tank between Lr - Lr - Cr - Coss. Without
including the internal resistances, this oscillation keeps
circulating back and forth. As seen from the input inductor
voltage, this oscillation causes inductor current to have a small
oscillating current in addition to the linearly increasing
current.
A 650W proof-of-concept prototype, shown in Fig 8, is
designed to serve as a proof-of-concept and to show ZVT
operation of the circuit. The circuit parameters are same as of
the simulation. The current ratings of the switches are chosen
based on the rms value. As the ZVT circuit does not impose
additional current stress on the main switches, the main switch
rms current can be found as in traditional three-level converter
[10]. The voltage rating of the main switches is the sum of the
half of the output voltage and the resonant capacitor voltage,
which was given in Eq. (30). It can be expressed as
V
o i

2Lr
(35)
while body diodes of S1 and SC4r1conduct. The additional voltage
V

similar to boost operation.

The simulation waveforms for d=0.53 and d=0.4 using
ideal switches are given in Fig. 7(a) and Fig. 7(b),
respectively. In boost operation only S2 and S3 are switched

Body Diodes

main

Lr 2

On the other hand, the current rating of the auxiliary

switch is equal to
stress on the main switches can be clearly observed. The duty
ratio of the auxiliary switch calculated from the analysis match
with one fourth of the resonant period, such that the resonant

Iaux iLr 2 t0

(36)

Gate Voltages of S2-S3 [V]

S2
S3

15

Gate Voltages of S2-S3 [V]

15

Gate Voltages of Sa1-Sa2 [V]

Gate Voltages of Sa1-Sa2 [V]

15

0
[V]

icr2
vcr2

icr1
vcr1

Auxiliary Switch Voltages [V]

vdsa1

8
0
4

[A] [V]
4
2
0
0
0
4

vdsa2

Inductor Current [A]

4
6
Time [s]
(a)

ids2 10
6
2

10

Resonant Capacitor Voltage-Current

i
vcr1
cr1

Auxiliary Switch Voltages [V]

[A]
12
ids2
vds2 8
4
0

80
40
0

-40
-80
[A] [V]

-2
-6

S3 Drain-Source Voltage-Current

i
8
vds3
ds3
4
0

-40
-80

-4
-8

Resonant Capacitor Voltage-Current

i

cr

[A]
4
0
4

Auxiliary Switch Voltages

[V]

8
0
6
0
4
0
2
0

Inductor Voltage [V]

-4
-8
[A]

80
40
0

[A] [V]
4
2
0
0
0

vdsa2
vdsa1

v
dv
d

Inductor Voltage [V]

40
0
-40
-80
5.6

Inductor Current [A]

5.4

5.4

5.3
5.2

5.2

S2 Drain-Source Voltage-Current

-2
-6

20
0
-20
-40
-60
-80
5.7
5.5

Inductor Voltage [V]

40
20
0
-20
-40

vds2

8
6
4
2
0

5.0
4.8
4.6
4.4
4.2
4.0
0

[V]
[A] 120

S3 Drain-Source Voltage-Current
[A] [V]
ids3 10
ids3 12
vds3
100 8vds3 6
6
4 2
2
0
0
-20
-4
-60

Resonant Capacitor Voltage-Current

2
0
0
2

S2 Drain-Source Voltage-Current

ids2 12 100
vds2 8
6
4
0
2
0 0
-20
-4
-60

-40
[V]

0
[A] [V]

S3 Drain-Source Voltage-Current

Sa1
Sa2

15

15

S2 Drain-Source Voltage-Current

120
8
0
4
0 0
-40
[V]
120
80
40
0

Gate Voltages of Sa1-Sa2 [V]

Sa1
Sa2

Sa1
Sa2

S2
S3

15
0

Gate Voltages of S2-S3 [V]

S2
S3

4
6
Time [s]
(b)

10

5.0

Inductor Current [A]

4
6
Time [s]
(c)

10

Fig. 7. Simulation waveforms for boost operation mode; (a) d=0.53 with ideal switches, (b) d=0.4 with ideal switches, (c) d=0.4 with non-ideal switches.

The component parameters used in the experiments are

given in Table IV. Fig. 9 presents the input inductor current
waveform and gate-source voltages of S2 and S3. This figure
illustrates the boost mode operation of the three-level
converter, where the current ripple frequency is twice of the
switching frequency.
The ZVT operation of the converter has been presented in
the experimental results provided in Figs. (10)-(11). Fig. 10
presents the ZVT operation during boost mode of operation
for d<0.5 under low current. The peak value of IS2 is
approximately 2.2A. As depicted before, the auxiliary switch
is turned on before the main switch is turned on to conduct the
body diode of the main switch. The ZVT can be clearly
observed from Fig. 10(b). In Fig. 10(c), auxiliary current and

voltage waveforms are presented, from which ZCS operation

can be clearly seen. The experimental waveforms are agrees
with the simulation results presented in Fig. 7(c). Different
than simulation, the oscillations are damped due to the internal
resistances of the components in the experiments. Likewise,

ZVT operation for boost mode for d<0.5 under higher

current (peak switch current of 4A) profile is given in Fig.
11.
It should be noted that the proposed ZVT cell causes
some undesirable oscillations on the drain-source voltage
as well as the current of the main switches. These
oscillations are due to output parasitic capacitance of the
auxiliary switches, Coss. In the experiments, a low Coss
switch with rated Coss of 140pF at Vds=200V is utilized to
minimize the oscillation amplitude and increase the

resonance frequency. Yet, these oscillations are inevitable

as there is Lr - Lr - Cr - Coss resonant network. Meantime,
half of the output voltage is equal to the sum of Vs1, Vs2, Vcr1,
and Vsa1. Therefore, any oscillation within the resonant
network affects the switch voltage and current waveforms.
Nevertheless, this energy keeps oscillating back and forth
until it is damped by the internal resistances of the resonant
tank components.
The equivalent capacitance involving in the oscillations is
equal to (Cr*Coss)/(Cr+Coss), which makes it close to the value

vDS2

iS2

vGS2

vGSa1

Fig. 8. Photo of the designed experimental prototype.

(a)

iL

vDS2
vGS3

iS2

vGS2

vGSa1

ZVT

vGS2

(a)

(b)

vDSa1
iSa1
vGS2

vGSa1

(b)
Fig. 9. Experimental waveforms of normal boost operation; gate-source
voltages S2 and S3, and inductor current for, a) d<0.5, b) d>0.5.

of Coss. The energy stored in Coss, starts to resonate.

Considering its capacitance, the stored energy is very small.
The voltage of Cr, which can be observed from the additional
voltage stress on the main switches, remains almost the same
between charging and discharging instants of Cr, which also
shows that energy is conserved and not wasted. This can also
be observed from the auxiliary switch current given in Fig. 10
(c), and Fig. 11 (c), which is same as the resonant capacitor
current. The peak values of the resonant capacitor current are
same for charging and discharging instants. This also verifies
that this oscillation does not cause significant power loss.
Consequently, it can be concluded as this oscillation 1) does
not create any additional voltage stress on the components, 2)
causes very small current stress on the inductors and switches,
3) the circulating energy is very small, yet, most of it is not
wasted.
In addition, the very high frequency oscillation observed on

(c)
Fig. 10. Experimental waveforms of ZVT operation boost mode when d<0.5
(low current); (a) gate-source and drain-source voltages and current of S2, and
gate-source voltage of Sa1 for two switching periods, (b) zoom-in snapshot, c)
gate-source and drain-source voltages and current of Sa1, and gate-source
voltage of S2.

the gate signals is due to the high parasitic capacitance of the

differential probe. Since the grounds of the probes should be
isolated, a regular and a differential voltage probe are used for
sensing gates of the signals. To prove this claim, the regular
and differential probes have been connected to the gate-source
terminal of S2 (purple waveform) and Sa1 (green waveform) in
Fig. 10(b), respectively. As it can be seen, the very high
frequency oscillations are only on the Sa1 gate signal. In Fig.
10(c), these two probes are replaced. This time, the
oscillations are observed on the S2 gate signal. Thus, the high

96

vDS2

iS2

vGS2

94
Efficiency [% ]

vGSa1

Soft-switched
Vo=180V

92

Vo=220V

90

Vo=180V
Hard-switched

88

(a)

86
100

vDS2

iS2

vGSa1

ZVT

vGS2

200

Level Converter

D1&D4

iSa1
vGSa1

vGS2

(c)
Fig. 11. Experimental waveforms of ZVT operation boost mode when d<0.5
(high current); (a) gate-source and drain-source voltages and current of S2, and
gate-source voltage of Sa1 for two switching periods, (b) zoom-in snapshot, c)
gate-source and drain-source voltages and current of Sa1, and gate-source
voltage of S2.

frequency oscillations on the gate signals are completely due

to the differential probe parasitics.
The efficiency curves for two different output voltage
levels, along with hard-switched converter efficiency, are
presented in Fig. 12. It can be seen that the designed prototype
exhibits 95.5% at full load, while the peak efficiency of hardswitched converter is 91%. The individual losses of
semiconductors are presented in Table V. Considering the

700

TABLE V. LOSS COMPARISON OF HARD-SWITCHED AND SOFTSWITCHED CONVERTERS AT Vo=180V AND Po=650W
Soft-Switched ThreeHard-Switched Three-

Aux switch
Sa1&Sa2

vDSa1

600

Fig. 12. Efficiency curve of; a) proposed topology at Vo=180V and Vo=220V,
b) hard-switched three-level converter.

Main
switch
S2&S3

(b)

300
400
500
Output Power [W]

Level Converter

Pswt
[W]

Pcon
[W]

Pswt
[W]

Pcon
[W]

38

8.1

5.3

3.2

2.8

12

12.6

typical efficiencies of industrial non-isolated bidirectional dc/dc

converters, which are between 90-95%, the proposed ZVT
converter provides competitive efficiency to its

counterparts. In addition, it should be noted that the

proposed ZVT converter inherently reduces the
required input boost inductance and output filter
capacitance by half due to the three-level structure, in
comparison
to the state-of-the-art
converters.
Moreover, it allows using low-voltage rated switched.
V.

CONCLUSION

In this paper, a ZVT bidirectional TL dc/dc converter,

employing two identical ZVT cells to fully soft-switch
all four switches in bidirectional power flow during
turning on instants of the main switches, is introduced.
The design procedures of the ZVT cell components are
provided. Furthermore, an actively controlled variable
dead-time approach has been introduced to minimize

the reduction in the duty ratio due to the soft-switching

period, during converters operation under heavy loads. A
650W prototype has been designed to demonstrate the
operation of the converter. The peak efficiency at 200 kHz
switching frequency is recorded as 95.5%.
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Serkan Dusmez (S11) received the B.S.
(Hons) and M.S. degrees in electrical
engineering
from
Yildiz
Technical
University, Istanbul, Turkey, in 2009 and
2011, respectively. He received the M.S.
degree in electrical engineering from Illinois
Institute of Technology, Chicago, in 2013.
He is currently working toward the Ph.D.
degree at the University of Texas at Dallas.
From 2012-2013, he worked as a Faculty
Research Assistant in the Power Electronics,
Energy Harvesting and Renewable Energies
Laboratory in the Electrical and Computer Engineering Department at the
University of Maryland at College Park. He is the author/co-author of over
35 journal and conference papers. His research interests include design of
power electronic interfaces and energy management strategies for
renewable energy sources, integrated power electronic converters for plugin electric vehicles, and real-time fault diagnosis of power converters.
Alireza Khaligh (S04M06SM09) is
the Director of Power Electronics, Energy
Harvesting and Renewable Energies
Laboratory at the Electrical and Computer
Engineering (ECE) Department and the
Institute for Systems Research in the
University of Maryland (UMD). He is an
author/coauthor of over 130 journal and
conference papers.
Dr. Khaligh is the recipient of various
awards and recognitions including the
2013 George Corcoran Memorial Award
from the ECE Department of UMD, 2013
Best Vehicular Electronics Awards from
the IEEE Vehicular Technology Society (VTS), and 2010 Ralph R. Teetor
Educational Award from the Society of Automotive Engineers. He is the
Program Chair of the 2015 IEEE Applied Power Electronics Conference
and Exposition. He was the General Chair of the 2013 IEEE Transportation
Electrification Conference and Exposition, and Program Chair of the 2011
IEEE Vehicle Power and Propulsion Conference. He is an Editor of IEEE
Transactions on Vehicular Technology (TVT) and an Associate Editor for
IEEE Transactions on Transportation Electrification. Dr. Khaligh was a
Guest Editor or a Guest Associate Editor for various IEEE Transactions
including IEEE Transactions on Power Electronics and IEEE Transactions
on Industrial Electronics.
Amin Hasanzadeh was a Post-Doctoral Research Associate at the Power
Electronics, Energy Harvesting and Renewable Energies Laboratory at the
Electrical and Computer Engineering Department in the University of
Maryland.