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DECLARATION
BHAVYA.CHINTHA
(13481A0423)
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ACKNOWLEDGEMENT
We wish to take this opportunity to express our deep gratitude to all those who helped,
encouraged, motivated and have extended their cooperation in various ways during our
project work. It is our pleasure to acknowledgement the help of all those individuals who was
responsible for foreseeing the successful completion of our project.
We would like to thank Mr. L. VASUDEVA MURTHY (Head, CED) and express
our gratitude with great admiration and respect to our project guide Mr. CH .GOUTHAM
RAJ for their valuable advice and help throughout the development of this project by
providing us with required information without whose guidance, cooperation and
encouragement, this project couldnt have been materialized.
Last but not the least we would like to thank the entire respondents for extending their
help in all circumstances.
BHAVYA.CHINTHA
(13481A0423)
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ABSTRACT
Multiprocessor system on chip is emerging as a new trend for
system on chip design but the wire and power design constraints are
forcing adoption of new design methodologies. Researchers pursued a
scalable solution to this problem i.e. Network on Chip (NOC).
Network on chip architecture better supports the integration
of SOC consists of on chip packet switched network. Thus the idea is
borrowed from large scale multiprocessors and wide area network
domain and envisions on chip routers based network. Cores access the
network by means of proper interfaces and have their packets
forwarded to destination through multichip routing path.
In order to implement a competitive NOC architecture, the
router should be efficiently design as it is the central component of
NOC architecture. In this paper we implement a parallel router which
can support five requests simultaneously. Thus the speed of
communication can be increased after reducing communication
bottleneck by suing simplest routing mechanism, flow mechanism and
decoding logic.
Design and verify the functionality of the Design and
verification of four port router for network on chip IP core using
the latest verification methodologies, Hardware verification languages
and EDA tools and qualify the IP for synthesis an implementation.
90% of ASIC resins are due to functional bugs. As the functional
verification decides the quality of the silicon, we spend 60% of the
design cycle time only for the verification/simulation. In order to
avoid the delay and meet the TTM, we use the latest verification
methodologies and technologies and accelerate the verification
process.
This project helps one to understand the complete
functional verification process of complex ASICs an Socs and it gives
opportunity to try the latest verification methodologies, programming
concepts like object oriented programming of Hardware Verification
Languages and sophisticated EDA tools, for the high quality
verification.
The design and verification plan is based on verilog
Hardware verification Language. The methodology used for
verification is constraint random coverage driven verification.
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Organization profile
ECIL was setup under the department of Atomic Energy in the
year 1967 with a view to generate a strong indigenous capability in the
field of professional grade electronic. The initial accent was on selfreliance and ECIL was engaged in the Design Development
Manufacture and Marketing of several products emphasis on three
technology lines viz. Computers, control systems and
communications. ECIL thus evolved as a multi-product company
serving multiple sectors of Indian economy with emphasis on import
of country substitution and development of products and services that
are of economic and strategic significance to the country.
Electronics Corporation of India Limited (ECIL) entered into
collaboration with OSI Systems Inc. (www.osi-systems.com) and set
up a joint venture "ECIL_RAPSICAN LIMITED". This Joint Venture
manufacture the equipments manufactured by RAPSICAN, U.K,
U.S.A with the same state of art Technology, Requisite Technology is
supplied by RAPSICAN and the final product is manufactured at
ECIL facility.
Recognizing the need for generating quality IT professionals
and to meet the growing demand of IT industry, a separate division
namely CED has been established to impart quality and professional
IT training under the brand name of ECIT. ECIT, the prestigious
offshoot of ECIL is an emerging winner and is at the fore front of IT
education in the country.
Mission
ECILs mission is to consolidate its status as a valued national
asset in the area of strategic electronics with specific focus on Atomic
Energy, Defense, Security and such critical sectors of strategic
national importance.
Objectives
Divisions
The Company is organized into divisions serving various
sectors, national and Commercial Importance. They are Divisions
serving nuclear sector like Control & Automation Division (CAD),
Instruments & Systems Division (ISD), Divisions Serving defence
sector like Communications Division (CND), Antenna Products
Division (APD), Servo Systems Division (SSD) etc., Divisions
handling Commercial Products are Telecom Division (TCD),
Customer Support Division (CSD), Computer Education Division
(CED).
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Exports
ECIL is currently operating in major business EXPORT
segments like Instruments and systems design, Industrial/Nuclear,
Servo Systems, Antenna Products, Communication, Control and
Automation and several other components.
Services
The company played a very significant role in the training and
growth of high calibre technical and managerial manpower especially
in the fields of Computers and Information Technology. Though the
initial thrust was on meeting the Control & Instrumentation
requirements of the Nuclear Power Program, the expanded scope of
self-reliance pursued by ECIL enabled the company to develop
various products to cater to the needs of Defence, Civil Aviation,
Information & Broadcasting, Tele communications, etc.
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