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mechanism
Solution:
Each vector requires four consecutive bytes of memory for
storage. Therefore, its address can be found by multiplying the type
number by 4. Since CS50 and IP50 represent the words of the type
50 interrupt pointer, we get
Address = 4 x 50 = 200
converting to binary form gives
Address = 110010002 = C816
Therefore, IP50 is stored at 000C816 and CS50 at 000CA16.
Meaning
Format
Operation
Flags affected
CLI
CLI
0 (IF)
IF
STI
STI
1 (IF)
IF
INT n
Type n software
interrupt
INT n
(Flags) ((SP)-2)
0 TF, IF
(CS) ((SP) 4)
(2+4xn) (CS)
(IP) ((SP) 6 )
(4xn) (IP)
TF, IF
IRET
Interrupt return
IRET
((SP)) (IP)
((SP)+2) (CS)
((SP)+4) (Flags)
(SP) + 6 (SP)
All
INTO
Interrupt on overflow
INTO
INT 4 steps
TF, IF
HLT
Halt
HLT
None
WAIT
Wait
WAIT
YES
NO
YES
NMI
NO
YES
INTR
1
IF
NO
READ TYPE
NUMBER
0
1
TF
ACKNOWLEDGE
INTERRUPT
COMPLET CURRENT
INSTRUCTION
0
EXECUTE NEXT
INSTRUCTION
LET TEMP = TF
PUSH CS & IP
CALL INTERRUPT
SERVICE ROUTINE
EXECUTE USER
INTERRUPT ROUTINE
POP IP & CS
POP FLAGS
RESUME INTERRUPT
PROCEDURE
PUSH XX
PUSH YY
PUSH ZZ
.
.
.
.
.
POP ZZ
POP YY
POP XX
IRET
10
b.
11
SRVRTN
Save processor
status
Set up the
interrupt vector
Increment
the count
Enable
interrupts
Restore processor
status
Wait for
interrupt
Return
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13
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IN CASCADE
MODE
YES (SNGL=0)
ICW3
NO (IC4=0)
IS ICW4
NEEDED
YES (IC4=1)
ICW4
Initialization sequence of
the 82C59A
READY TO ACCEPT
INTERRUPT REQUESTS
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Solution:
Since ICW4 is to be initialized, D0 must be logic 1, D0 = 1
For cascaded mode of operation, D1 must be 0, D1 = 0
And for level-sensitive inputs, D3 must be 1, D3 = 1
Bits D2 and D5 through D7 are dont-care states and are 0.
D2 = D5 = D6 = D7 = 0
Moreover, D4 must be fixed at the 1 logic level, D4 = 1
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000110012 = 1916
17
Solution:
To set the 82C59A up so that type numbers are in the range of F016
through F716, its device code bits must be
D7D6D5D4D3 = 111102
The lower three bits are dont-care states and all can be 0s. This
gives the word
D7D6D5D4D3D2D1D0 = 111100002 = F016
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Solution:
For IR0 through IR3 to be configured to allow direct inputs from
external devices, bits D0 through D3 of ICW3 must be logic 0:
D3D2D1D0 = 00002
The other IR inputs of the master are to be supplied by INT outputs
of slaves. Therefore, their control bits must be all 1:
D7D6D5D4 = 11112
This gives the complete command word
D7D6D5D4D3D2D1D0 = 111100002 = F016
19
Solution:
For IR0 through IR3 to be masked, their corresponding bits in the
mask register must be make logic 1:
D3D2D1D0 = 11112
On the other hand, for IR4 through IR7 to be unmasked, D4 through
D7 must be logic 0:
D7D6D5D4 = 00002
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000011112 = 0F16
20
Solution:
To enable the rotate on nonspecific EOI command priority scheme,
bits D7 through D5 must be set to 101. Since a specific level does
not have to be considered, the rest of the bits in the command word
can be 0. This gives OCW2 as
D7D6D5D4D3D2D1D0 = 101000002 = A016
21
Solution:
Since the 82C59A resides in the memory address space, we can
use a series of move instructions to write the initialization command
words into its registers. Note that the memory address for an ICW is
A00016 if A0 = 0, and it is A00116 if A0 = 1. However, before doing
this, we must first disable interrupts. This is don with the instruction
CLI
; Disable interrupts
22
Minimum-mode interrupt interface for the 8088 microcomputer using the 82C59A
23
Minimum-mode interrupt interface for the 8086 microcomputer using the 82C59A
24
Maximum-mode interrupt interface for the 8088 microcomputer using the 82C59A
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26
SRV72
Save processor
status
Set up the
interrupt vector
Increment
the count
Initialize
82C59A
Restore processor
status
Enable interrupts
Return
Wait for
interrupt
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DX, 0FF00H
AL, 13H
DX, AL
DX, 0FF02H
AL, 48H
DX, AL
AL, 03H
DX, AL
AL, 0FEH
DX, AL
;ICW1 address
;Edge trig input, single 8259A
;ICW2, ICW4, OCW1 address
;ICW2, type 72
;ICW4, AEOI, nonbuf mode
;OCW1, mask all but IR0
;Enable the interrupts
PUSH
MOV
INC
DAA
MOV
POP
IRET
AX
AL, [COUNT]
AL
[COUNT], AL
AX
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hardware.
Differences between NMI and other external interrupts:
NMI can not be masked out with the interrupt flag.
Request for NMI service are signaled to the 8088/8086
microprocessor by applying logic 1 at the NMI input, not the
INTR input.
NMI input is positive edge-triggered. Therefore, a request for
NMI is automatically latched internal to the MPU.
NMI automatically vectors from the type 2 vector location
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11.11 Reset
The RESET input of the 8088 and 8086
11.11 Reset
Bus and control signal status of the 8088/8086 during system reset
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11.11 Reset
When the MPU recognizes the RESET input, it
CONTENT
Flags
Clear
Instruction pointer
0000H
CS Register
FFFFH
DS Register
0000H
SS Register
0000H
ES Register
0000H
Queue
Empty
11.11 Reset
The external hardware interrupts are disabled after
the initialization.
Program execution begins at address FFFF016 after
reset. This storage location contains an instruction
that will cause a jump to the startup (boot-strap)
program that is used to initialize the reset of the
microcomputer systems resources, such as I/O ports,
the interrupt flag, and data memory.
After the system-level initialization is complete,
another jump can be performed to the starting point
of the microcomputers operating system or
application program.
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