Project Report

Physical Design Implementation of

Torpedo Sub-system
By
N. Achyuth
K. Pramod Kumar Reddy

Under the guidance of

Mr. Srinath B K
senior Physical Design engg.

Project Report - Revision history

Version

Name

Date

Comments

V1.0

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Table of Contents
1 -Physical Design Flow.......................................................................................................................1
2 -DESIGN PLANNING......................................................................................................................2
3 -Floor-Planning..................................................................................................................................3
The goals of floor -Planning.............................................................................................................3
Power Planning.................................................................................................................................4
First Floor plan & PNS details:(Horizontal)....................................................................................4
Analysis............................................................................................................................................7
4 -Placement.......................................................................................................................................10
DFT Setup......................................................................................................................................11
5 -Clock Tree Synthesis......................................................................................................................18
6 -Routing...........................................................................................................................................25
7 -Design For Manufacturability (DFM)............................................................................................30
8 -Physical Verification......................................................................................................................32
Design Rule Check.........................................................................................................................33
Layout Vs Schematic......................................................................................................................34
9 -Sign off STA...................................................................................................................................35

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Physical Design Specification

Technology

180nm

Library Vendor

Jazz Semiconductor

Operating Voltage

1.8 V

Clock Frequency

400Mhz

Power Budget

300mw

Max IR drop (VDD + VSS)

5%(90mw)

No. of Macros

32

No. of standard Cells

43275

Functional Clocks

Sys_clk, Sys_rclk

Test Mode Clocks

Scan_clk

Die Area

5.9mm sq

No. of Metal Layers

Standard Cell Height

5.04 um

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1 - Physical Design Flow

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2 - DESIGN PLANNING
In the design planning context, floor-planning is the process of sizing and placing hierarchical cells
and functional block in a manner hat makes later physical design steps more effective. Floor
-planning in hierarchical flows provides a basis for estimating the timing of the top level. A timing
budget allocates the clock cycle time to each block according to the top-level timing estimation.
An effective floor-plan helps ensure timing closure in many ways,such as placing blocks to make
critical paths short,preventing routing congestion that would lead to longer paths, and eliminating
the need for over-the top routing for noise-sensitive blocks. The challenge is to create a floor-plan
with good area efficiency while leaving sufficient area for routing.

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3 - Floor-planning
The Goals of floor-planning :
1.Defining the core area (2450*2450).
2.Creating Ports (Ports. Tcl).
3.Design a floor-plan & Power network of horizontal metal layer such that the total IR Drop must be less
than 5%(VDD + VSS ) For a power Budget of 300 MW.
4.Defining the Placement and Routing Blockages.
Define core area and I/O core spacing,source the verilog file i.e.,Torpedo.v after reading all macros and
standard cells are placed outside the core area as shown in below figure.

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Placing the Macros inside the core area i.e.,the floor-planning. During the floor-planning we have
to follow the steps and techniques to come up with a good floor-plan

Kept the Macros which are communicating with same type of the Macros close together
with the help of fly lines,Colour by hierarchy and data flow diagram.

Avoided the placement of Macros in front of ports.

Arranged the Macros to get contiguous core area .

Reduce the narrow channels between the Macros and provided proper placement.

Placed the Macros with pins towards the core , Macros spacing of 0.28 (M4 Min Spacing).

POWER PLAN :

Power planning is very important stage in physical design during which we synthesize the
power network in order to provide power to all macros and standard cells with in given IR drop i.e.
5% of (VDD+VSS).Study state IR drop is caused by the resistance of the metal wires comprising
the power distribution network. By reducing the voltage difference between the local power and
ground,study state ur drop reduces both the speed and noise immunity of the local cells and
macros.
As vertical power straps are fixed (m6_power.tcl) only we have to modify the horizontal metals
i.e. metal_5 to achieve target ir drop of 90 mv and the power budget of 300mw.
Initial power plan summary w.r.t floor-plan fig 1

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FIRST FLOOR-PLAN & PNS DETAILS :(HORIZONTAL)

Metal 5 strap count 7

Metal 5 width 3.5

Metal 5 offset 677

Metal 5 pitch 3.76

Step Size 298.026

Since the actual placement is not done the tool uses the average power consumed by
each standard cell and macros which is characterized in .lib for this calculation and also
based on the virtual placement it did to find the location of the standard cells.

Placed power hungry macros near to the periphery.

Reduced the stacking level.

Used the macro periphery affectively.

Located hot spot and provided with more than one power straps by adjusting the offset and
step size of metal 5 layer is used.
So modified floor-plan is shown in below figure

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The modified floor-plan gave an IR-DROP of 91.5mv

constraints of

Metal 5 strap count 5

Metal 5 width 3.3

Metal 5 offset 244.00

Metal 5 pitch 3.56

Step size

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292.2

analyse_fp_rail with the PNS

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VDD IR DROP MAP

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VSS IR DROP MAP

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Analysis :
During the power planning we got the floating shape and floating pin errors and are explained
below
Floating-shapes :
During power planning if metal 1 VDD overlaps with metal5 VSS then tool will not connect metal
1 to metal6 so that entire metal 1 becomes floating . Since it is not connected to any straps .If in
case we put a via that lead to short between VDD and VSS and are shown below
We took proper offset and step size as multiples of standard cell height so that metal 5 straps
beingg placed in between the metal 1 pre_routes . After that we did not got any floating shape
errors.

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Floating-pins:
During power planning some macros not got connection to power i.e , tool not connected its VDD
or VSS ring with metal 5 straps through via. Since macro is not connected to VDD or VSS so
those are called as floating pins shown below.

As shown in the figure since metal 4 of macro is overlapped with metal 3 i.e, VDD of macro if
in case tool put via that lead to short we just rearranged macros in order to get power connection.
BLOCKAGE CREATION :
During power planning in some region metal 1 rail is discontinued so during placement tool may
place standard cell over there since those cells will not get power connection in order to prevent
standard cell placement over there create placement blockage as shown below .
FLOOR PLAN SUMMARY
Floor-plan
No. of Errors from
verify_PG_nets

Run1
2 Floating shapes and pins

Run2
No errors

Max voltage Drop(VDD + VSS) 88.9

92.4

No. of standard cells

43275

43275

Placement utilization

67%

67%

No. of Horizontal Straps

Width of Horizontal Straps

3.5

3.3

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4 -PLACEMENT
Design Status before Placement
synthesis is compiled second pass netlist is generated. Data setup is completed. Floor -plan
cell is ready .All the errors related to floating shapes and floating pins should be fixed.
Zero Interconnect Timing Sanity Check
Before starting Placement make sure that Zero interconnect delay is made false .To make ZIC
Delay false set .Set_zero_interconnect_delay_mode false.
Placement setup and checks
IC Compiler Placement Flow

Inputs to Placement

Gate Level Netlist

Synopsys Design Constraints

TLU + (Min,max)

Floor -plan

Blockages

Common Optimizations (don't use , area or power critical range )

Routing Layers

Critical Range Optimization

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Outputs of Placement

Design with all Standard cells placed in core area

Timing reports after Placement

Logs

Placement Set-up and Checks

Fix all macros before placement .If macros are not fixed placement tool will move macros during
timing or congestion optimization. To fix the macros the following command
icc_shell>set_dont_touch_placement all_macro_cells
check for placement Readiness
icc_shell>check_physical_design -stage pre_place_opt
above command checks the readiness of :

Floor -Plan

Netlist

Design Constraints

Enable Multiple Clocks per register

icc_shell>set_false_path -from get_clocks C2 -to get_clocks C1
with the above settings timing analysis considers both C1 and C2 uses faster clock for setup
timing optimizations.

DFT Setup
If your design flow includes DESIGN FOR TEST, the netlist will contain Scan_chains, group of
scan_registers that they are serially connected through SI/SO pins, and inserted during synthesis.
Scan_chain paths are active only during Test_mode , not during Functional_mode. Registers
are typically connected in alphanumeric order during synthesis -irrelevant for DFT, but not optimal
for routing.
Scan chain information is given to IC compiler using scandef file and for place_opt if we given
-optimize_dft the IC compiler will reorder the scan chain based on the functional optimization to
reduce the routing congestion.

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PLACEMENT CEL

To extend flexibility, SCANDEF also supports reordering with partitions across multiple buckets
a PARTITION is a group of SCANDEF chains that may exchange flip-flops during reordering.

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PLACEMENT SUMMARY

Placement

Run1

Run2

WNS(setup :hold)

-1.73:0.00

-1.75:00

TNS(setup :hold)

-19623:0.000

-19256:0.00

Total area of standard cells

526286 sites

526272

No. of standard cells

47928

47906

Placement ?Utilization

76.78%

76.50%

Is placement congestion ok

OK

OK

Are all timing paths fixable for

timing?

NO

NO

Note: Run2 WNS and TNS are less compared to Run1 because after first pass placement we
used critical range to optimize sub_critical paths.

Results and Analysis

IR Drop :
IR drop in placement increases compared floor -plan stage. In Placement all high fanout nets
except clock network to balance and to fix DRC (Design Rule Constraints) and IC compiler will
resize some standard cells during optimization ,by resized cells IR drop increases.
After placement VDD max IR drop increased from 45.6 to 47.00 and VSS max IR drop
increased from 46.2 to 47.0 .We have to take care of the increased IR drop in second iteration of
PD by decreasing acceptable IR drop .Following figures show the IR drop map of VDD and VSS.

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VDD IR DROP MAP

VSS IR DROP MAP

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CONGESTION

Congestion occurs when the number of wires going through a region exceeds the capacity of
that region. This condition is detected by global routing. A congestion map can help you visualize
the quality of placement with respect to the avoidance of routing congestion .The congestion map
shows the borders between global congestion cells highlighted with different colours that respect
different levels of overflow. The overflow values shown in congestion map are determined by
combing the overflow and underflow of all selected layers . For Example , in below figure the light
blue colour highlighted on the edge of the global routing cell shows 10/9.This means there are 9
wire tracks available, but 10 tracks are needed.
CONGESTION MAP

Timing Analysis :

During first run we got 22k violations with most violations in REGIN paths due to over
constraining of input to reg paths.

We have analysed some paths which are false paths and reported them to synthesis
Engineer.

We have observed some paths in which macro delays is more than clock period and
reported them to project manager.

During initial design setup we have segregated all timing path to REGIN,REGOUT and
CLOCK groups for better optimization of sub_critical paths.

We gave critical range just greater than WNS to optimize all sub-critical paths and gave
another run observed that TNS reduced.

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5 CLOCK TREE SYNTHESIS

Clock Tree Synthesis is a process of distributing clock Signals to the clock sink pins of each
flop in the Design according to the information given by the Logic synthesis. Up to this step the
clock Signals are considered as ideal that is zero skew, latency, uncertainty and Transition times. In
this step the CTS will synthesize the clock tree by using clock inverters or clock buffers and will
balances the skew and it tries to minimise the skew targets, latency and transition times given by the
specifications.
The difference between HFN synthesis during placement and CTS is that the HFN
will balance the load this is not good at balancing skew. And hence clock networks are considered
ideal during placement stage in PD flow.

CTS FLOW

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CTS Specifications
Meet the buffering constraints
Maximum transition delay

Maximum load capacitance

Maximum fan out

Meet the clock tree targets

Maximum skew

Min/Max insertion delay

Meet all Clock tree Design Rule Constraints ( DRC )

If the targets are not met no violations are reported.
Results And Analysis:
The analysis shows the hold fixing after psyn using clock_opt command
QOR Report before hold fixing

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Hold WNS : -12.255

Hold TNS :-1265
No of Hold violations : 14247
QOR Report after hod fixing

Hold WNS : -12.029

Hold TNS :-56.506
No of Hold violations : 316

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Inserting port protection diodes :

Antenna Effect: During manufacturing process in the CMP (Chemical Mechanical Polishing)
will produce high temperatures which will lead long running metal layers will collect the charges
and discharge them through gate of MOS transistor which can destroy the gate of the transistor
this is called as Antenna Effect.
To avoid this we have to add port protection diodes during CTS stage using the command
insert_port_protection_diodes. So that those diodes can protect the ports from Antenna Effect.

port protection diodes

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SYS_CLK

SCAN_CLK

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SYS_RCLK

UART_CLK

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6 - ROUTING
Routing creates the physical connection to all the clock and signal pins through the metal
interconnects. The routing should perform according to the priority as listed
Route clock nets ( Enable non default routing i.e. Double spacing )

Route signal nets ( Enable signal integrity options if needed )

perform route opt

The basic routing will be carried out with the following steps

Global routing

Track Assignment

Detailed routing

Search and Repair

ROUTING FLOW

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Global Routing:
GR assigns nets to specific metal layers and global routing cells (G cells). GR tries to avoid
congested Gcells while minimizing route at congestion areas. Congestion exist if no of tracks
available is less than the required.
The global router divides a design into global routing cells. By default the width of a global
routing cell is same as the height of a standard cell and is aligned with the standard cell rows.

FIG: G CELL

Global routing done in two phase

The initial routing phase ( phase 0 ), in which the tool routes the unconnected nets and
calculate the overflow for each global routing cells with overflows

the routing phases, in which the tool tries to reduce congestion by ripping up and rerouteing
nets around global routing cells with overflows.

The size of GRC is equal to the height of the average standard cell.

Track assignment:
This process assigns each net to specific track and lays down the actual metal traces. It
attempts to make long, straight traces. And reduces no of vias. It does not follow DRC rules.

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Detailed routing:
Input channels and approximate routing from the global routing phase Determine the exact
route and layers for each net
Objective:
valid routing, minimize area (congestion), meet timing constraints minimum via, power.

search and repair:

This step in the flow will fixes the remaining DRC violations through multiple loops using
progressively larger S-box sizes

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RESULTS AND ANALYSIS :

CLOCK ROUTE

SIGNAL ROUTE

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DETAILED ROUTING CONGESTION

TRACK ASSIGNMENT CONGESTION

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7 DESIGN FOR MANUFACTURABILITY

DFM or DFY ( Design for Yield ) is needed to increase the yielding while tape out and to decrease the
defects in the manufacturing process. The DFM steps includes
Gate Oxide integrity antenna fixing

Via resistance and reliability extra contacts

Random Particle defect Wire spreading

Metal erosion metal slotting

Metal lift-off metal slotting

Metal over etching metal fill

Antenna violation:
The antenna will be violated when long running metal can collect the charge during CMP
( chemical mechanical polishing ) and can destroy the gate of MOS transistor (or) if the antenna
ratio is violated which is given by the fab. The antenna ratio is defined as
Antenna ratio= Am /Ag

where

Am = area of metal connected to gate

Ag = total area of the gate

Antenna fixing
Antenna can be fixed in two ways
1. Metal jog ( metal jumping )
2. Inserting reverse biased diode near gate of MOS

1.Metal jog:
The figures below shows antenna violation and fixing it by metal jog

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2.Fixing antenna with diode:

The figures below shows antenna violation fixing it with inserting diode.

There are two ways to fix antenna.

1. First method is to insert_diode -no_auto_cell_selection -diode_cells antenna -nets [get_nets
<net name>]
2. Second method

create_cell <desired instance name of antenna cell. Ex: antenna1> scgp_ss/antenna

connect_net <net name failing antenna check> antenna1/A

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ANTENNA VIOLATIONS IN HIGHLIGHTED NETS

ANTENNA FIXING USING DIODES

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Via doubling:
Replacing one via with multiple vias can improve yield & timing ( series R reduction ). the
tool inserts multiple vias without re-routing. insert_redundant_vias is used to create multiple vias .

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wire spreading and widening:

Random missing or extra material causes opens or shorts during the fabrication process.

Metal slotting:
Metal slotting can avoid the metal lift and metal erosion during the fabrication process. Slotting wide
wires reduces the metal density and it minimizes stresses build-up, reducing lift-off
tendency .
Primarily used on Power and Ground traces Can apply to any other net if wide enough Slotting
parameters can be set per layer

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8 - PHYSICAL VERIFICATION
Design Rule Check
Design rules are series of parameters provided by semiconductor manufactures that enables the
designer to verify the correctness of a mask set. Design rules are specific to a manufacturing
process. A design rule set specifies certain geometric and connectivity restrictions to ensure
sufficient margins to account variability during manufacturing process so that most of the design
parts work correctly.
In PD we can check only subset of rules there in DRC rule deck, these subset of rules are
related tp metal layers and vias. The rules are present in technology file. The rules include
minimum spacing, minimum area, minimum width etc. Some of the errors we have encountered in
our block are given below.

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Layout vs Schematic
A successful design rule check ensures the layout confirms to the rules required for
faultless fabrication. However it does not guarantee is it really represent the circuit you desire to
fabricate. This is where an LVS check is used.

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9-SIGN OFF STA

IC Compiler is an implementation engine, StarRC and Prime Time are sign off engines. In general
, the implementation engine and the sign-off engine are well correlated with each other.
However,small variations can occur because of the following :

Prime Time and StarRC , as sign-off tools are more accurate.

Prime Time has reduced Signal Integrity pessimism.

IC Compiler might have implementation margin

IC Compiler might have fewer corners

These differences can cause timing violations during final sign-off. Prime Time supports the use of
timing models to represent chip sub-modules. A timing model contains information about the timing
characteristics, but not the logical functionality of a sub-module.
Prime Time can generate a timing model from a sub-module netlist , and then use that model in
place of the original netlist for timing analysis at higher levels of hierarchy. This technique makes
whole chip analysis run much faster.
To perform stage delay calculation accurately and efficiently, Prime Time uses models to represent
the driver, RC Network and capacity load on the net. An ideal model would produce exactly the
same delays and slews as a SPICE simulation at the output of the driver and at the input of each
receiver.
To perform Static Timing Analysis, PrimeTime must accurately calculate the delay and slew
(transition time ) at each stage of each timing path. A stage consists of a driving cell, the annotated
RC network at the output of the cell and the capacitive load of the network load pins. The goal is to
compute the response at the driver output and at the network load pins, given the input slew or
waveform at the driver input using the least amount of runtime necessary to get accurate results.
To perform stage delay calculation accurately and efficiently, PrimeTime uses models to represent
the driver, RC network and Capacitive load on the net. An ideal model would produce exactly the
same delays and slews as a SPICE simulation at the output of the driver and at the input of each
receiver.
The driver model is intended to reproduce the response of the driving cell's underlying transistor
circuitry when connected to an arbitrary RC network given for a specific input slew. The reduced
order network model is a simplified representation of the full annotated network that has really the
same response characteristics as the original network. PrimeTime uses the Arnoldi reduction
method to create this model.

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