ECE646

FPGA Based System Design

L T P C
3 0 2 4

Version No.: 2.00

Prerequisite:
Objectives:
This course covers the advanced design and analysis of digital circuits with HDL. The primary goal
is to provide in depth understanding of logic and system design. The course enables students to
apply their knowledge for the design of advanced digital hardware systems with help of FPGA tools.
Expected Outcome:
Upon successful completion of this course, students will be able to:
1. Design and manually optimize complex combinational and sequential digital circuits
2. Model combinational and sequential digital circuits by Verilog HDL
3. Design and model digital circuits with Verilog HDL at behavioral, structural, and RTL Levels
4. Develop test benches to simulate combinational and sequential circuits.
Unit I
Verilog HDL Coding Style:
Lexical Conventions - Ports and Modules Operators - Gate Level Modeling - System Tasks &
Compiler Directives - Test Bench - Data Flow Modeling - Behavioral level Modeling -Tasks &
Functions.
Unit II
Verilog Modeling of Combinational & Sequential Circuits:
Behavioral, Data Flow and Structural Realization Adders Multipliers- Comparators - Flip Flops Realization of Shift Register - Realization of a Counter- Synchronous and Asynchronous FIFO
Single port and Dual port RAM Pseudo Random LFSR Cyclic Redundancy Check.
Unit III
Synchronous Sequential Circuit:
State diagram-state table state assignment-choice of flip-flops Timing diagram One hot
encoding- Mealy and Moore state machines Design of serial adder using Mealy and Moore state
machines - State minimization Sequence detection- Design of vending machine using One Hot
Controller
Unit IV
FPGA and its Architecture:
Types of Programmable Logic Devices- PLA & PAL- FPGA Generic Architecture. ALTERA
Cyclone II Architecture Timing Analysis and Power analysis using Quartus-II- SOPC BuilderNIOS-II Soft-core Processor- System Design Examples using ALTERA FPGAs Traffic light
Controller, Real Time Clock - Interfacing using FPGA: VGA, Keyboard, LCD.
Textbooks:
1. S. Ramachandran, Digital VLSI System Design: A Design Manual for implementation of
Projects on FPGAs and ASICs Using Verilog Springer Publication, 2007.
2. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis Prentice Hall, Second
Edition, 2003.
Reference Books:
1. Charles H Roth, Jr Digital Systems design using VHDL, Thomson Books/Cole.
2. Wayne Wolf , FPGA Based System Design, Prentices Hall Modern Semiconductor Design
Series.
3. Mark Balch, Complete Digital design A Comprehensive Guide to Digital Electronics and
Computer system Architecture, McGraw Hill, 2003.
4. Stephen Brown & Zvonko Vranesic, Digital Logic Design with VerilogHDL TATA McGraw
Hill Ltd. 2nd Edition 2007.
5. ALTERA Quartus II Handbook Ver 10.0.
CAT- I & II, Assignments/ Quiz, Term End Examination
Mode of Evaluation:

Proceedings of the 29th Academic Council [26.4.2013]

257

ECE646

FPGA Based System Design Lab

Objectives:
This course is introduced for designing digital logic using Verilog HDL. It provides the students
with advanced concepts of design such as: interfacing between systems on different clocks, FPGA
interface with external devices and performance analysis of the system.
List of Experiments:
1. Design and Implementation of Combinational Circuits
a. Basic Gates Using Dataflow, Structural, Behavioral Modeling
b. Half-Adder and Full-Adder using structural Modeling
c. Half-Subtractor and Full-Subtractor using dataflow modeling.
d. Decoder and Encoder using case, casex and casez statements.
e. Code Convertor & parity generators using reduction operators
f. Multiplexer and De-multiplexer using nested if-else construct
2. Design and Implementation of Sequential Circuits
a. Flip-Flop using behavioral modeling
b. Serial-In Serial Out, Parallel-In Parallel Out Shift register using Structural Modeling
c. Serial-In Parallel Out, Parallel-In Serial Out Shift register using behavior level
Modeling
d. Ring Counter and Johnson counter using behavior level Modeling and structural level
modeling.
3. Design and Implementation of FSM
a. Sequence detector using FSM
b. Traffic Light Controller using FSM
c. Vending machine problem using FSM
4. FPGA Interfacing using Quartus-II
a. Displaying given string (Using LCD Interface )
b. Displaying given string on LCD (Using Keyboard Interface)
5. System Design using SOPC and NIOS-II
a. Real time video display on Monitor ( Using camera interface)
b. RGB to Gray Scale Conversion
EDA Tools:
i. ALTERA Quartus II,
ii. NIOS-II IDE
iii. SOPC Builder
Hardware:
ALTERA DE2 Board
Interfaces:
5.1 Megapixel Camera
PS2 Keyboard
LCD Display

Proceedings of the 29th Academic Council [26.4.2013]

258