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21 vizualizări8 paginiDesign and Analysis of Class E/F3 Power
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at Nonoptimum Operation.

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Design and Analysis of Class E/F3 Power
Amplifier with Nonlinear Shunt Capacitance
at Nonoptimum Operation.

© All Rights Reserved

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21 vizualizări8 paginiDesign and Analysis of Class E/F3 Power
Amplifier with Nonlinear Shunt Capacitance
at Nonoptimum Operation.

© All Rights Reserved

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2, FEBRUARY 2015

727

Amplifier with Nonlinear Shunt Capacitance

at Nonoptimum Operation

Mohsen Hayati, Akram Sheikhi, and Andrei Grebennikov, Senior Member, IEEE

Class-E/F3 power amplifier with a nonlinear shunt capacitor for

satisfying the nonoptimum condition at 50% duty ratio. The design parameters for achieving the nonoptimum condition are expressed as a function of the phase shift and dc supply voltage. The

Class-E/F3 amplifier with nonoptimum condition increases one

design degree of freedom compared with the optimum conditions.

Because of the increase in the design degree of freedom, one more

relationship can be specified as a design specification. The following

parameters series reactance, peak switch voltage, output power capability, and maximum operating frequency are presented. Based

on analytical results, an example of the Class E/F3 at operating

frequency of 4 MHz is analyzed. The PSpice simulation and measured results agree with the analytical expressions, which show the

validity of our analytical expressions at zero-voltage switching.

Index TermsMixed mode, nonlinear capacitance, nonoptimum

operation and zero-voltage switching (ZVS), power amplifier.

I. INTRODUCTION

HE nonoptimum operation of the amplifier occurs when

the zero-voltage switching (ZVS) condition is satisfied,

but the zero-voltage-derivative switching (ZDS) is not equal to

zero at the switch turns ON instant. The concept of nonoptimum

operation of the Class-E amplifier was defined in the beginning

of the Class-E history [1][4]. The first research on nonoptimum

operation has been done by Raab [1]. In this paper, the degree

of freedom for the design amplifier was increased, and the ZDS

condition was removed. The mixed-mode power amplifiers are

the good choice for obtaining high-power and high conversion

efficiency. The optimum conditions of the mixed-mode power

amplifier families with a shunt capacitor have been presented

in [5][7]. But the exact analysis on switch mode PAs are not presented. However, all of the Class-E/F amplifier analyses focus

on how to achieve the optimum operation. Many power electronic devices only need to ZVS or zero-current switching (ZCS)

condition [8][20]. In order to reach a Class E power amplifier

Manuscript received December 26, 2013; revised January 19, 2014; accepted

February 13, 2014. Date of publication February 25, 2014; date of current

version October 7, 2014. Recommended for publication by Associate Editor

T. J. Liang.

M. Hayati and A. Sheikhi are with the Department of Electrical Engineering,

Faculty of Engineering, Razi University, Tagh-E-Bostan, Kermanshah-67149,

Iran (e-mail: mohsen_hayati@yahoo.com; akram.sheikhi2008@gmail.com).

A. Grebennikov is with the Bell Laboratories, Alcatel-Lucent, Dublin 15,

Ireland (e-mail: grandrei@ieee.org).

Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2014.2308280

implemented. The first method employs the push/pull topology

to Class E in order to short odd harmonic like inverse Class F

(demonstrated Class E/F PA). This configuration improved the

amplifier performance such as maximum operating frequency

and caused the reduction of maximum switching voltage to have

maximum output power capability [21], which only in the ZVS

is considered. But the nonoptimum condition in the push/pull

topology is considered with linear shunt capacitance. The second method is harmonic tuning in which a resonance network is

inserted between the drain node and ground. In comparison with

Class E amplifier, the performance of the power amplifier can

be improved at the cost of the complicated circuit design [6].

Besides the aforementioned methods, some Class E amplifiers

consist of resonance networks tuned at nonharmonic frequencies. Nonharmonic resonance network consists of parallel finite

dc feed inductor and parallel drain to source capacitor [22], [23]

and the series parallel resonance network at the drain node [24].

In [25], a parallel LC resonator, tuned to the second harmonic

of the switching frequency, is added into the load network of

the Class-E amplifier, in which the significant improvement in

output power capability is achieved. Up to 10 MHz, the power

amplifier with nonoptimum condition can reach high power

conversion efficiency, so the analysis of the power amplifier at

nonoptimum condition is very important.

In this paper, the analytical expressions of the Class-E/F3

power amplifier with a shunt capacitor at the nonoptimum operation are presented. For the verification of our analytical expressions, design examples of the Class-E/F3 ZVS amplifier are

presented. The design equations, switch, and output waveforms

are obtained as a function of the phase shift and dc supply voltage. By changing the peak switch voltage and the peak switch

current, the phase shift is changed, so these two parameters

can be considered as a design specification. The measurement

and PSpice-simulation results are in good agreement with the

analytical results. Design procedures are given for one example

of Class E/F3 amplifiers for nonoptimum operation. In the example, operating frequency, input dc supply voltage, load resistance, and peak switch voltage are given as design specifications.

In the nominal circuit, only three parameters such as operating

frequency, input dc supply voltage, and load resistance can be

designated. On the contrary, the example procedures presented

here have four given parameters. The additional parameters,

peak switch voltage or peak switch current can be taken into

account in the design procedure. This power amplifier is implemented with the IRF510 MOSFET. From the breakdown voltage

0885-8993 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.

See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

728

iM OS () = ID D In sin(n) IM sin( + )

(5)

as

iM OS () = is () + iC ds () for 0 < < .

(6)

MOSFET is depicted as

Fig. 1.

Cj 0 dvs

iM OS () = iC ds () =

1 + Vvbsi d

device.

II. CIRCUIT ANALYSIS

The circuit analyzed in this paper is a Class E/F3 amplifier

which shown in Fig. 1. The shunt capacitance of the amplifier

consists only of the MOSFET output parasitic capacitance which

is nonlinear. The derivations of design equations are carried out

under the following assumptions:

1) the inductance of the choke LRFC is large enough to neglect its current ripple;

2) the loaded quality factor Q of the output resonance circuit

is high enough so that the output current can be considered

as a sine wave;

3) the on and off resistance of the MOSFET is zero and

infinite, respectively;

4) the shunt capacitance Cds is entirely composed of the

MOSFET output capacitance. The grading coefficient of

the MOSFET output capacitance is 0.5. The shunt capacitance is described by

Cds =

Cj 0

1+

vs

Vb i

(1)

to 0.9 V, vs is the switch voltage, and Cj 0 is the capacitance

at vs (0) = 0;

5) the loaded quality factor Q of the output resonant circuit

is defined as

L

.

(2)

Q=

R

The quality factor Q is high enough to generate a sinusoidal

output current

io = IM sin( + )

(3)

the angular switching frequency, and is a phase-shift between

the gate-to-source voltage and the output current. The current

through the shunt capacitance produces the switch voltage. The

switch-voltage waveform satisfies the ZVS conditions at the

switch turn-on instant. We assume that the switch for 0 < <

is OFF, so we have

vs () = 0.

(4)

(7)

capacitance. From (7) and vs (0) = 0, we obtain

vs

C

j 0 dvs , for 0 < < .

iM OS ( ) d =

0

0

1 + Vvbsi

(8)

By substituting (6) into (8), we have

[ID D In sin(n) IM sin( + )] d

0

vs

=

0

Cj 0

1+

v s

Vb i

vs () = Vbi [(h() + 1)2 1]

(10)

where

(cos(n) 1)+IM (cos( + ) cos())

.

2Vbi Cj o

(11)

By substituting = and (4) into (10), we obtain

h() =

ID D +

In

n

In

(cos(n) 1) 2IM cos() = 0.

(12)

n

The relative amplitude of the nth harmonic component for

any n can be obtained [7] as

ID D +

4ID D

.

n

By substituting (13) into (12), for n = 3, we have

ID D =

In =

(13)

18

IM cos().

9 2 8

(14)

PI = VD D ID D

(15)

2

R IM

.

2

The power conversion efficiency is

Po =

2

Po

R IM

=

= 1.

PI

2 ID D VD D

(16)

(17)

Fig. 2.

729

It is assumed that there is no power losses in the circuit since, in any cases different from optimum Class E with

zero-voltage and zero voltage-derivative conditions, there exists

a nonzero value of current through the drain-source capacitance

at t = , which means that the existing nonzero voltage across

the capacitance should be discharged instantaneously through

the ideal switch with zero resistance.

From (14) and (17), the amplitude of the output current is

36 VD D cos()

9 2 8

R

and the amplitude of the output voltage

IM =

VM = RIM =

36

VD D cos()

9 2 8

2

18

2VD D cos2 ()

.

ID D =

9 2 8

R

(18)

(19)

(20)

is a function of the phase shift and it decreased as phase shift

increased. The dc-supply and output power is

2

18

2 VD2 D cos2 ()

PI = Po = ID D VD D =

. (21)

2

9 8

R

(b) > o p tim u m , and (c) = o p tim u m .

obtained as

iC ()| = = ID D IM sin(+)In sin(n) = ID D +IM sin()

18

18

VD D

cos()

=2

cos()+sin()

.

9 2 8

R

9 2 8

(22)

The normalized switch voltage for different value of , is

shown in Fig. 3. The switch turns ON with the switch voltage declining and the ZVS condition is satisfied. As can be

seen from Fig. 3(a) and (b), when < optimum and >

optimum , the switch turns OFF and the ZVS condition is satisfied but ZDS condition is not satisfied. But at optimum condition = optimum , the ZVS and ZDS conditions are achieved.

The normalized output current amplitude IM R/VD D , output

power Po R/VD2 D , and shunt capacitance current RiC /VD D

P o R/V D2 D and shunt capacitance current R iC /V D D as a function of .

in Fig. 4. For nonoptimum operation, the operating range is

/2 < < 0.61 rad. The output power Po is zero at /2.

In this case, the dc input current ID D is zero and the switch voltage waveform is a part of a sinusoidal waveform. The switch

730

Fig. 6.

Fig. 5.

In this case, the amplifier achieves the optimum operation and

the product of the output power Po and the load resistance R

reaches the maximum value.

The average value of the switch voltage is equal to the dcsupply voltage VD D

VD D

1

=

2

0

1

vs ()d =

2

and 1 is

Vbi [(h() + 1) 1]d.

9 cos()

Cj 0 R =

(9 2 8)

2

4 VD D (27 4 198 2 +152) + 2 VD D cos(2 ) 0.5

2 sin(2 )

.

(9 2 8)

(24)

The variation of Cj 0 R as a function of VD D and is shown

in Fig. 5. The maximum value is obtained when VD D is increased. On the other hand, when VD D = 100 V and = 0.83,

the maximum value for Cj 0 R is obtained. As can be seen from

Fig. 1, the voltage across the reactance Lx is expressed as

vL x = Lx

2

Lx

V1 = VM 1 +

R

(23)

Solving this equation, one obtains the Cj 0 R as a function

of VD D and . Equation (23) has two solutions. One solution

is not suitable for this circuit because Cj 0 R is negative when

/2 < < 0.1. The other solution of (23) for Cj 0 R is

obtained as

dio

Lx VM

= Lx IM cos( + ) =

cos( + )

dt

R

for 0 < < 2. (25)

1 = + tan1

vs 1 () = vo () + vL x ()

= VM

Lx VM

cos(+) = V1 sin(+1 ) (26)

sin(+)+

R

Lx

R

.

(28)

The output voltage of the resonant circuit vs1 has only the

fundamental frequency component of the switch voltage vs .

Therefore

1 2

vs () cos( + 1 )d = 0.

(29)

0

From (29), we obtain

vs () cos()d

tan 1 = 0

0 vs () sin()d

Vbi [(h() + 1)2 1] cos()d

= 0

2

0 Vbi [(h() + 1) 1] sin()d

(30)

Lx = X = R tan(1 ).

(31)

be seen that the variation of VD D cause a little change in X/R,

but this ratio decreased when increased.

From the definition of the loaded quality factor Q, L is obtained as

L=

(27)

RQ

.

(32)

Lr = L Lx =

R

[Q tan(1 )].

(33)

Fig. 7.

731

Fig. 8.

Fig. 9.

C=

1

2 Lr

1

.

R[Q tan(1 )]

(34)

The definition of output power capability Cp is

Cp =

VD D ID D

=

|Vs m ax |Is m ax ||

1

|V s m a x | |I s m a x |

VD D

ID D

(35)

at the MOSFET. The peak switch voltage appears in the range

of 0 < < . Therefore, we have

|vs (m ax )|

Vbi

|Vs m ax |

=

=

[(h(m ax ) + 1)2 1]. (36)

VD D

VD D

VD D

In the peak value of the voltage, the derivative value of the

switch voltage is zero. So, from (6) and (8) for n = 3, we

obtained

ID D I3 sin(3 m ax ) IM sin(m ax + ) = 0.

(37)

4

9 2 8

sin(m ax + ) = 0. (38)

1

sin(3m ax ) +

3

18

Fig. 7 shows the ratio VS M AX /VD D as a function of and

VD D . This ratio increases from 3.5 to about 3.8 as VD D increases

from 0 to 100 V. On the other hand, the peak switch current

appears during the on-state. So, we have

IS M AX

I3

IM

=1

sin(3)

sin( + ).

ID D

ID D

ID D

(39)

Fig. 8 shows normalized maximum switch current IS M R as

a function of . It can be seen that the normalized maximum

switch current IS M R increase as increases from 1.57 to

0.61 rad. Fig. 9 shows the output power capability Cp as

a function of and VD D . It can be seen that Cp increases

as increases. The other parameter to evaluate the amplifier

performance is maximum operating frequency. This parameter

causes the limitation on all the parameters of the power amplifier.

Fig. 10.

increases as VD D increases. On the other hand, it is increased

as increase up to 0.61 rad and decreased from 0.61 up to

0.1 rad.

732

TABLE I

THE VALUES OF THE ELEMENTS FOR THE NONOPTIMUM DESIGN EXAMPLE

A. Design Peocessure

The design specifications for the amplifiers are f = 4 MHz,

VD D = 25 V, Pout = 10.7 W, VS M = 98 V, Q = 10, and D =

0.5.

From (36), we have = 0.21 rad. From (24), R is calculated

as 54.58 . From (32), L is obtained 21.72 H. From (31), we

obtained Lx = 1.68 H. From (33), Lr = 20.05 H. From (34),

the resonant capacitor is obtained C = 78.96 pF. The series

resonant circuit C3 L3 has the effect on shaping the transistor

current and voltage waveforms. The initial value for resonant

circuit C3 L3 is obtained as: L3 = 14 H and C3 = 12.56 pF.

The practical transistor is not an ideal switch, so an optimization

process should be done. The parameters before and after optimization is shown in Table I. The inductance of the RF choke

was selected as Lf = 30 H. From (45), IS M AX = 0.62 A could

be obtained. From (23), we obtained ID D = 0.42 A.

Fig. 11. (a) Class E/F3 power amplifier used for the nonoptimum operation.

(b) The photograph of the fabricated power amplifier.

TABLE II

THE VALUES OF THE ELEMENTS AND POWER RELATION FOR THE DESIGN

EXAMPLE AT NONOPTIMUM CONDITION

The theoretical results have been verified experimentally using the circuit of Class E/F3 in Fig. 11(a). The photograph of the

fabricated power amplifier is shown in Fig. 11(b). In the PSpice

simulation, the device model of IRF510 from the vendors website [26] is used. It is driven by the gate-driver IC 1XDN414P,

its dc supply passes through two parallel capacitors 100 F

and 10 nF. The transistor is mounted directly to a backside aluminum heatsink. The equivalent series resistance (ESR) values

of passive elements were measured by a HP-4284A, and the on

resistance of the IRF510 was obtained from PSpice model.

The following results were obtained: LRFC = 30 H (ferrite

core inductor with air gap), RLRFC = 0.2 (dc parasitic resistance), C3 = 11.89 pF (silver mica capacitors), L3 = 14.1 H

(ferrite core inductor with air gap), RL3 = 0.116 (parasitic

resistance at 12 MHz) C = 78.96 pF (silver mica capacitors),

L = 21.72 H (ferrite core inductor with air gap), RL =

44.67 m (parasitic resistance measured at 4 MHz), and R

= 54.7 (resistance of load network). The power losses of all

capacitors were negligible. A Tektronix TDS3014B digital oscilloscope was used for recording voltage waveform. The output

power POut can be obtained based on the dc power PD C , the

transistor losses PT , the supply current ID C , the currents IC3

and IOut , and the parasitic resistances RLRFC , RL, and RL3 .

POut = PDC PL 3 PL PT

= 10.7 W 0.02 W 0.5 W 0.282 W = 10 W.

The power gain is obtained as

G = 10 log10

Po

Pin

(40)

733

93.45% power conversion efficiency at 4 MHz and output power

10.3 and 10 W, respectively. We will address the analysis of the

Class-E/Fn amplifier for any n with nonlinear shunt capacitance

in the future works.

REFERENCES

Fig. 12. Waveforms obtained from (a) the PSpice Simulation, and (b) the

experimental results for the nonoptimum operation.

where Pin and Pout are the input and output power, respectively.

Also, the total harmonic distortion (THD) is

THD =

n =2

2

Von

Vo1

(41)

in the output voltage vo . The measured values of the power

gain and THD are 25.38 dB and 4.35%, respectively. The value

of the elements, and all the powers are shown in Table II. The

waveform obtained from Pspice and measured results are shown

in Fig. 12(a) and (b), respectively.

V. CONCLUSION

This paper has introduced analytical expressions of the

Class-E/F3 power amplifier with shunt capacitance for the

nonoptimum operation. The design values for achieving the

nonoptimum condition are expressed as a function of the phase

shift between the input and output voltage and dc-supply voltage. The Class-E/F3 amplifier with nonoptimum condition increases one design degree of freedom. Because of the increase

in the design degree of freedom, peak switch voltage and current can be specified as a design specification. This paper has

given the circuit design example based on our proposed design

expression by specifying the peak switch voltage. The measurement and PSpice simulation results are in agreement with the

analytical expressions quantitatively, which show the validity

of our analytical expressions. In the circuit simulation and ex-

Proc. RF Technol. Expo., Santa Clara, CA, USA, Feb. 1989, pp. 8598.

[2] T. Suetsugu and M. K. Kazimierczuk, Analysis of subnominal operation

of Class-E amplifier, presented at the IEEE Midwest Symp. Circuits

Syst., Cairo, Egypt, Dec. 2003.

[3] T. Suetsugu and M. K. Kazimierczuk, Design procedure of class-E amplifier for off-nominal operation at 50% duty ratio, IEEE Trans. Circuits

Syst. I, Reg. Papers, vol. 53, no. 7, pp. 14681476, Jul. 2006.

[4] T. Suetsugu and M. K. Kazimierczuk, Design equations for suboptimum

operation of class E amplifier with nonlinear shunt capacitance, in Proc.

IEEE Midwest Symp. Circuits Syst., vol. 5, Vancouver, Canada, May 2004,

pp. 560563.

[5] Z. Kaczmarczyk, High-efficiency class E, E/F, and E/F inverters, IEEE

Trans. Ind. Electron., vol. 53, no. 10, pp. 15841593, Oct. 2006.

[6] F. You, S. He, X. Tang, and X. Deng, High-efficiency single-ended

Class-E/F2 power amplifier with finite dc feed inductor, IEEE Trans.

Microw. Theory Tech., vol. MTT-58, no. 1, pp. 3240, Jan. 2010.

[7] A. Grebennikov, High-efficiency class E/F lumped and transmissionline power amplifiers, IEEE Trans. Microw. Theory Tech., vol. 59, no. 6,

pp. 15791588, Jun. 2011.

[8] B. Yuan, X. Yang, D. Li, Y. Pei, J. Duan, and J. Zhai, A current-fed multi

resonant converter with low circulating energy and zero-current switching

for high step-up power conversion, IEEE Trans. Power Electron., vol. 26,

no. 6, pp. 16131619, Jun. 2011.

[9] Y.-T. Chen, S. Shiu, and R. Liang, Analysis and design of a zero-voltage

switching and zero-current-switching interleaved boost converter, IEEE

Trans. Power Electron., vol. 27, no. 1, pp. 161173, Jan. 2012.

[10] H. Wang, H. Chung, and A. Ioinovici, A new concept of high-voltage

DCDC conversion using asymmetric voltage distribution on the switch

pairs and hybrid ZVSZCS scheme, IEEE Trans. Power Electron.,

vol. 27, no. 5, pp. 22422259, May 2012.

[11] T.-H. Hsia, H.-Y. Tsai, D. Chen, M. Lee, and C.-S. Huang, Interleaved

active-clamping converter with ZVS/ZCS features, IEEE Trans. Power

Electron., vol. 26, no. 1, pp. 2937, Jan. 2011.

[12] A. Mousavi, P. Das, and G. Moschopoulos, A comparative study of a

new ZCS DCDC full-bridge boost converter with a ZVS active-clamp

converter, IEEE Trans. Power Electron., vol. 27, no. 3, pp. 13471358,

Mar. 2012.

[13] B-R. Lin and P.-J. Cheng, New ZVS DCDC Converter With SeriesConnected Transformers to Balance the Output Currents, IEEE Trans.

Power Electron., vol. 29, no. 1, pp. 246255, Jan. 2014.

[14] A. Safaee, D. Yazdani, A. Bakhshai, and P. K. Jain, Multiblock soft

switched bidirectional ACAC converter using a single loss-less active

snubber block, IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2260

2272, May 2012.

[15] M. Acar, A. J. Annema, and B. Nauta, Generalized design equations for

Class-E power amplifiers with finite DC feed inductance, in Proc. 36th

Eur. Microw. Conf., Manchester, U.K., Sep. 2006, pp. 13021305.

[16] D. K. Choi and S. I. Long, Finite DC feed inductor in Class E power

amplifiersA simplified approach, in Proc. IEEE MTT-S Int. Microw.

Symp. Dig., 2002, pp. 16431646.

[17] S. Bin, Z. Junming, and L. Zhengyu, Totem-pole boost bridgeless PFC

rectifier with simple zero-current detection and full-range ZVS Operating

at the Boundary of DCM/CCM, IEEE Trans. Power Electron., vol. 26,

no. 2, pp. 427435, Feb. 2011.

[18] W. Li, P. Li, H. Yang, and X. He, Three-level forwardflyback phase-shift

ZVS converter with integrated series-connected coupled inductors, IEEE

Trans. Power Electron, vol. 27, no. 6, pp. 28462856, Jun. 2012.

[19] R. Beiranvand, B. Rashidian, M. R. Zolghadri, and S. M. H. Alavi, Optimizing the normalized dead-time and maximum switching frequency

of a wide-adjustable-range llc resonant converter, IEEE Trans. Power

Electron., vol. 26, no. 2, pp. 462472, Feb. 2011.

[20] R. Beiranvand, B. Rashidian, M. R. Zolghadri, and S. M. H. Alavi, A

design procedure for optimizing the lc resonant converter as a wide output range voltage source, IEEE Trans. Power Electron., vol. 27, no. 8,

pp. 37493763, Aug. 2012.

734

of ZVS switching amplifiers, IEEE Trans. Microw. Theory Tech., vol. 51,

no. 6, pp. 16771690, Jun. 2003.

[22] G. H. Smith and R. E. Zulinski, An exact analysis of Class-E amplifiers

with finite DC-feed inductance at any output-Q, IEEE Trans. Circuits

Syst., vol. 37, no. 4, pp. 530534, Apr. 1990.

[23] M. Acar, A. J. Annema, and B. Nauta, Analytical design equations for

Class-E power amplifiers, IEEE Trans. Circuits Syst. I, Reg. Papers,

vol. 54, no. 12, pp. 27062717, Dec. 2007.

[24] F. You, S. He, X. Tang, and T. Cao, Performance study of a

Class-E power amplifier with tuned series-parallel resonance network,

IEEE Trans. Microw. Theory Tech., vol. 56, no. 10, pp. 21902200, Oct.

2008.

[25] A. Mediano and N. O. Sokal, A Class-E RF Power amplifier with a flattop transistor-voltage waveform, IEEE Trans. Power Electron., vol. 28,

no. 11, pp. 52155221, Nov. 2013.

[26] International Rectifier. (2011, Jun.). [Online]. Available: http://www.irf.

com/productinfo/models

Mohsen Hayati received the B.E. degree in electronics and communication engineering from Nagarjuna University, Guntur, India, in 1985, and the M.E.

and Ph.D. degrees in electronics engineering from

Delhi University, Delhi, India, in 1987 and 1992,

respectively.

He joined the Department of Electrical Engineering, Razi University, Kermanshah, Iran, as an Assistant Professor in 1993, and currently, as an Associate

Professor. He has published more than 140 papers in

international and domestic journals and conferences.

His current research interests include microwave and millimeter wave devices

and circuits, application of computational intelligence, artificial neural networks,

fuzzy systems, neuro-fuzzy systems, electronic circuit synthesis, and modeling

and simulations.

Shariaty University, Tehran, Iran, in 2007, and the

M.Sc. degree in electronics engineering from the Department of Electrical Engineering, Razi University,

Kermanshah, Iran, in 2010. She is currently working

toward the Ph.D. degree in electronics engineering in

the Razi University,.

Her research interests include microwave filter, high-frequency high-efficiency switching mixedmode power amplifiers, and numerical analysis of

nonlinear circuits.

Dipl. Eng. degree in radio electronics from Moscow

Institute of Physics and Technology, Moscow,

Russia, in 1980, and the Ph.D. degree in radio engineering from Moscow Technical University of Communications and Informatics, Moscow, Russia, in

1991.

He obtained a long-term academic and industrial experience working with the Moscow

Technical University of Communications and Informatics; the Institute of Microelectronics, Singapore; M/A-COM, Cork, Ireland; Infineon Technologies, Munich,

Germany, and Linz, Austria; and Bell Labs, Alcatel-Lucent, Dublin, Ireland,

as an Engineer, Researcher, Lecturer, and Educator. He has lectured as a Guest

Professor with the University of Linz, Linz, Austria, and presented short courses

and tutorials as an Invited Speaker at the IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposia (IMS), European

and Asia-Pacific Microwave Conferences, the Institute of Microelectronics,

Singapore, Motorola Design Centre, Penang, Malaysia, the Tomsk State University of Control Systems and Radio electronics, Tomsk, Russia, and the Aachen

Technical University, Aachen, Germany. He is an author and coauthor of more

than 100 papers, holds 30 European and US patents and patent applications, and

authored six books dedicated to RF and microwave circuit design.