10CS 33 LOGIC DESIGN UNIT - 2 Combinational Logic Circuits

10CS 33 LOGIC DESIGN
UNIT 2 Combinational Logic Circuits
Unit 2
Session - 8
Combinational Logic Circuits
Objectives
Review of combinational logic circuit design methods

Analyze hazards in logic circuit and provide solution for them
Problem Solving with Multiple Methods

We can simplify a given Boolean expression using one of following different methods:
Boolean algebra
Karnaugh map
Entered variable map
Quine-McClusky method
Example:
Get a minimized expression for
Y
= f (A, B, C) = m(0, 1, 3, 5)
= ABC + ABC + ABC + ABC
Method 1: Using Boolean Algebra

Y
= ABC + ABC + ABC + ABC

= (ABC + ABC) + (ABC + ABC) + (ABC + ABC)
= AB(C + C) + AC(B + B) + BC(A + A)
= AB.1 + AC.1 + BC.1
= AB+ AC + BC
(using Boolean Axioms: X = X + X and X + X =1)
B. S. Umashankar, BNMIT
Page 1
Method 2: Karnaugh Map

The truth table for the given expression:
Page 2
Method 3: Entered Variable Map

A
Y
1
3 Variable truth table reduces to 2 variable truth table.

A
The entered variable map is obtained as shown below:
Page 3
Simplification of EVM
Method 4: Quine McCluskey Method

Y = f (A, B, C) = m(0, 1, 3, 5)
Minterms
Binary rep.
No. of 1s
000
001
011
101
Determination of Prime Implicants
Page 4
Prime Implicant Chart
Hazards and Hazard Covers

Simplification techniques give minimal expressions for a logic equation
equation. Simplified equations can be
realized using minimum hardware. But to overcome some practical problems, in certain cases we may
prefer to include more terms in the simplified equation
equation. Practical logic circuits do not generate outputs
instantaneously. Theree is a finite propagation delay. This propagation delay gives rise to several
hazards.
Hazard covers are additional terms in a logic equation that prevents hazards
hazards.. For combinational
logic circuits hazard may go unnoticed but in sequential logic circuit
circuitss it may cause major malfunctioning.
malfunctioning
Page 5
Types of Hazards
Static Hazard
A static hazard exists if an output signal is supposed to remain at a particular logic value when an input
variable changes its value, but instead the signal undergoes a momentary chan
change
ge in its required value.
value
Static-1 Hazard
This type of hazard occurs when Y = A + A type of situation appears
ppears for a logic circuit for certain
combination of other inputs and A makes a transition 1 0.
An A + A condition should always generate logic 1 at the output, i. e. static -1
A
Y = A + A
1+0=1
0+1=1
Consider a simple logic circuit as shown:
The NOT gate output takes finite time to become logic 1 following 1 0 transition at the input A.
A The
OR gate output goes to logic 0 for a small duration which is unwanted
unwanted.
Y = A + A
1+0=1
0+0=0
0+1=1
The width of this logic 0 output is in nanoseconds and is called a glitch as shown in the figure next.
Page 6
Glitch
Static-1 Hazard Cover

Consider an example Y = AC + BC.. Corresponding logic circuit is as shown:
Consider input A = 1, B = 1, and C makes a transition 1 0. The output has a glitch and hence the circuit
has static-1 hazard.
Consider the Karnaugh map simplification
simplification.
Page 7
The additional term AB ensures Y = 1 for A = 1 and B = 1 and a 1 0 transition at C does not affect the
output. The circuit free from static--1 hazard is as shown below:
Static-0 Hazard
This type of hazard occurs when Y = A . A type of situation appears for a logic ccircuit
ircuit for certain
combination
ombination of other inputs and A makes a transition 0 1. An A . A condition should always generate
logic 0 at the output, i. e. static-0.
Y = A . A
0.1=0
1.0=0
Consider a simple logic circuit as shown:
The NOT gate output takes finite time to become logic 0 following 0 1 transition at the input A.
A The
AND gate output goes to logic 1 for a ssmall duration which is unwanted.
A
Y = A . A
0.1=0
1. 1 = 1
1.0=0
The width of this logic 1 output is in nanoseconds and is called a glitch as shown in the figure next.
Page 8
Glitch
Static-0 Hazard Cover

Consider an example Y = (B + C).(A + C)
C). Corresponding logic circuit is as shown:
Consider the Karnaugh map simplification

simplification.
The additional term (A + B) ensures Y = 0 for A = 0, B = 0 and a 0 1 transition at C does not affect the
output.. The hazard free circuit is as shown next:
Page 9
Dynamic Hazard
Dynamic hazard causes glitches on 0 1 or 1 0 transitions of an output signal.
signal When only one
transition is required, the output makes multiple transitions
transitions. It is caused
aused by the structure of the logic
circuit, where there exists multiple paths for a given signal change to propagate along
along..
Dynamic hazards are encountered in multi
multi-level circuits. They are not easy to detect.
detect They can be
avoided simply by using two-level
level circuits and ensuring that there are no static hazards.
hazards
Questions
1. Explain static-0 and static-11 hazard with example.
2. How do you eliminate static hazard? G
Give an example.
3. What is dynamic hazard? Where do you encounter dynamic hazards?
Page 10

10CS 33 LOGIC DESIGN UNIT - 2 Combinational Logic Circuits

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10CS 33 LOGIC DESIGN

UNIT 2 Combinational Logic Circuits

Review of combinational logic circuit design methods

Problem Solving with Multiple Methods

Method 1: Using Boolean Algebra

= ABC + ABC + ABC + ABC