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Objectives
Summary
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Summary
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Summary
m(t)sin(0 t)
m(t)
LPF
sin(0 t)
Data: m(t) = 1 , Carrier Frequency: 0
Introduction
Objectives
Summary
Residual Carrier
Transmit a residual carrier and use a phase lock loop with narrow
loop bandwidth to obtain reference carrier:
Data
Introduction
Objectives
Summary
PLL
sin(0 t)
cos(0 t + )
sin(0 t)
cos(0 t + )
1
2 sin()
LPF
Loop Filter
Feedback
z}|{
cos(0 t + )
VCO
Introduction
Objectives
Problems:
Data power interferes with residual carrier SNR.
Carrier power could be used towards transmitting data
Summary
Introduction
Objectives
Summary
Supressed Carrier
y (t) = 2Pm(t)sin(0 t)
Problem: PLL needs a carrier reference to track!
Solution: Use Costas Loop which can reconstruct carrier reference
for tracking (a special kind of PLL).
Introduction
Objectives
Summary
Costas Loop
1
m(t) {cos()
2
1
m(t)cos()
2
cos(20 t + )}
LPF
sin(0 t + )
m(t)sin(0 t)
1 2
m (t)sin(2)
8
VCO
Loop Filter
=
cos(0 t + )
1
sin(2)
8
LPF
1
m(t) {sin()
2
+ sin(20 t + )}
1
m(t)sin()
2
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Summary
1
2 m(t)
cos(20 t)}
LPF
sin(0 t)
m(t)sin(0 t)
VCO
Loop Filter
cos(0 t)
LPF
1
m(t) {sin(0)
2
+ sin(20 t)}
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Clock Extraction
Summary
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
FPGAs
Flexible digital circuits
Comprised of logic blocks and routing channels
Actel FPGAs: Use fuses instead of SRAM to avoid EM
interference
Programmed using VHDL/Verilog and synthesis tools
Summary
Introduction
Objectives
Summary
Objectives
Primary Objective
To implement supressed carrier BPSK demodulation using a Type
II Costas Loop on a Microsemi Actel FPGA (Field Programmable
Array) for 8-16KHz carrier signal and data rate of 2-4 kbps.
Introduction
Objectives
Summary
Objectives
Secondary Objectives
The secondary outcomes are the following features in the Costas
Loop:
Subcarrier lock: To indicate subcarrier lock has been achieved
Clock and bit sync lock: A clock in sync with the demod data
of 50 % duty cycle, and a bit sync lock indication to indicate
synchronization between your data and clock outputs (The
clock should be such that after initial sync, even if continuous
0s or 1s are given for 40 bits and then alternate 0 and 1s are
restored, the clock should not loose sync.)
Infinite Impulse Response filter implementation (aside from
use of FIR filters)
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Summary
Clock
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
Summary
Introduction
Objectives
NCO
Summary
Introduction
Objectives
Summary
Introduction
Objectives
Summary
Arm Filters
Low pass filters to remove the component of 20 .
Implemented using 10th Order Least Squares Method Optimization
FIR
order = 10;
Fpass = 6000;
Fstop = 8000;
Wpass = 1;
Wstop = 0.05;
arm coeffs = firls(order, [0 Fpass Fstop f sampling/2]/
(f sampling/2), [1 1 0 0], [Wpass Wstop]);
Coefficients are Q1.17 fixed point.
Introduction
Objectives
Summary
Arm Filters
Used MATLABs filter design toolbox to visualize filters and
created a class for simulating FIR filter fixed point implementation.
Introduction
Objectives
Summary
(t)
Loop Filter
VCO
F (s)
1
s
Transfer function
F (s)
s
(s)
F (s)
H(s) =
=
(s)
s + F (s)
G (s) =
(t)
Introduction
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Summary
Introduction
Objectives
PI Loop Filter
s
s +
= G (s) =
s2
F (s) = +
2 1 z 1
T 1 + z 1
Summary
Introduction
Objectives
Outline
1
Introduction
BPSK and NRZ
BPSK Supressed Carrier
BPSK Demodulator
Symbol Synchronization
FPGAs
Objectives
Summary
Introduction
Objectives
MATLAB Simulation
Summary
Introduction
Objectives
Summary
Summary