8.

3 GALLIUM ARSENIDE (GaAs) FRAMs

Section 8.2 discussed FRAMs based on ferroelectric
film capacitors integrated with conventional
silicon CMOS processing. Ferroelectric
element processing also has been combined
with GaAs technology to produce ferroelectric
nonvolatile memory (or FERRAM) prototypes
with 2K/4K bit density levels . A common
design approach for FE processing combined
with the GaAs JFET has been the placement of a
capacitor alongside the transistor structure

size of FE capacitors and their compatibility

with semiconductor processes used are the
major limitations toward the development of
practical memory circuits with commercial
yields. Another critical control parameter is the
uniformity of FE properties of thin film which
must be maintained over the entire chip surface
and wafer area.

ANALOG MEMORIES
A conventional electronic data memory, volatile
or nonvolatile, usually refers to the storage of
digital bits of information as logic "O"s and" 1"s.
Analog signal data storage also requires digitization
using analog-to-digital (NO) converters
and some digital signal processing. A recent development
of the "analog memory" concept
refers to direct analog storage without intennediate
digital manipulation. A company called Information
Storage Devices, Inc. (ISD) has
developed a single-chip voice message system
ISD 1200/1400 series family which includes several
device types that can provide 10-20 s of
high-quality recording and playback of the
human voice
without transforming the sound into digital form.

Ferroelectric element processingcombined with GaAs JFET technology

FERRAM memory circuit which can be externally

switched for operation in either 2K (256
word X 8b) single-cell mode, or4K (512 word X
8b) dual-cell operation. The reference capacitors
are ignored when the dual-cell option is
selected. Since the readout operation is destructive,
an automatic rewrite circuitry is included
in the design.
The memory array is divided into four
quadrants, each containing 64 word X 8 b for a
2K and 128 word X 8 b for a 4K density mode.
Each of these quadrants contains a different size
FE capacitor for the determination of optimum
capacitor size. For the single-cell devices, each
quadrant has different size reference capacitors,
which allows for various reference capacitor
versus memory cell capacitor ratios. The physical

MAGNETORESISTIVE RANDOM ACCESS

MEMORIES (MRAMs)
Magnetoresistive (MRAMs) are based upon the
principle that a material's magnetoresistance
will change due to the presence of a magnetic
field. A resistor made out a of common ferromagnetic
material will have a resistive component
(R) which varies as the square of the cosine
of the angle between the magnetization (M) and
the current. This means that for a larger angle,
the resistance component is large, and for a
smaller angle, the resistance component is
small. This magnetoresistive effect is utilized in
the fabrication of Honeywell MRAMs which
use a magnetic thin film sandwich configured in
two-dimensional arrays in RICMOSTM (radiation
insensitive CMOS), n-well bulk CMOS
technology [32]. This technology incorporates
additional magnetoresistive processing to produce
nonvolatile MRAM prototypes of 16K and
64K densities, and with 256K and 1 Mb circuits

under development.

EXPERIMENTAL MEMORY DEVICES

(a) Characteristic I-V curve for a RHET

device. (b) Equivalent circuit for an
RTD-based SRAM cell

8.6.1 Quantum-Mechanical
Switch Memories

AGaAs n-p-n-p Thyristor/JFET

Memory Cell

Quantum-mechanical switch-based devices

such as resonant-tunneling diodes (RTDs)
and resonant-tunneling hot-electron transistors
(RHETs) are being investigated for possible development
of gigabit memory densities [35].
These devices are based upon the negative resistance
property (or negative differential conductance)
which causes a decrease in current for an
increase in voltage. Figure 8-16(a) shows the
characteristic I-V curve for an RHET device
which exhibits normal resistance characteristics
at low voltage, similar to a normal transistor.
However, when the collector voltage reaches a
certain threshold, the RHET device shows negative
resistance, and the collector current drops
off with an increase in the collector voltage.
This effect has been used in the development
of a SRAM cell that uses two RTDs and
one ordinary tunnel diode (TD) for the complete
cell. This cell configuration produces considerably
higher densities than the devices fabricated
with a conventional six-transistor SRAM cell.

An experimental GaAs homojunction storage

device has been reported, which is based
upon the merger of a JFET sense channel with a
p-n-p storage capacitor. This approach has been
used to fabricate an integrated GaAs n-p-n-p
thyristor-junction field-effect transistor (JFET)
structure which displays a memory characteristic
by storing charge on the thyristor reverse-biased
junctions [40]. The device can be electrically
programmed and erased through a single terminal.
A buried p-channel, which also functions as
the thyristor anode, is used to read the stored
charge nondestructively over a small range of
applied drain voltages (:t 1.5 V). The thyristor
memory cell cross-section is shown in Figure
8-17. The n-p-n-p storage element is vertically
integrated with the p-Iayer charge sense channel.
A positive gate-to-source voltage less than the
breakdown voltage value is applied to program a

Neuron-MOS Multiple-Valued
(MV) Memory Technology
In real-time image processing applications,
the analog signals are taken into a 2-D
array of image sensors, converted to digital
data, and then processed by a digital computer.

Single-Electron Memory
A team of researchers from Hitachi and
Cambridge University's Cavendish Laboratory
in the United Kingdom have used the quantum
tunneling effects in GaAs material at extremely
low temperatures (0.1 K) to demonstrate that, in
principle, one bit of information can be stored
by one electron in a semiconductor memory.
The development is based on the device structure
that used side-gated structures in deltadoped
GaAs material to form a multiple-tunnel
junction (MTJ), as shown in Figure 8-18(a)
[41]. This design allows control over single
electrons through a phenomenon known as the
"Coulomb blockade effect,"

However, due to the increasing number of pixels

and enormous volumes of binary information,
a new scheme for data storage and
computation is needed to perform completely
parallel processing of analog or multiple-valued(MV)

MEMORY HYBRIDS AND MCMs (2-D)

This section gives several examples of commercially
available memory modules. Plasticpackaged
memories hold a high share of the
commercial market because of lower material
and processing costs. Several concepts for plastic
packaging of LSI memory modules have
been developed, such as lead-on-chip (LOC) by
IBM and chip-on-lead (COL) by Hitachi [3]. In
military and space applications, high-density
memory custom MCMs were developed by
Honeywell Inc. for the Advanced Spaceborne
Computer Module (ASCM) program, and VLSI
chip on silicon (VCOS) processing by IBM as
an extension of very high-speed integrated circuit
(VHSIC) technology.

9.2.1 Memory Modules (Commercial)

Figure 9-3 shows the packaging configuration
and pin diagram of a commercially available,
l68-pin dual in-line. memory module,

9.2.2 Memory MCMs (Honeywell ASCM)

The Honeywell ASCM is a generalpurpose
Advanced Spacebome Computer Module
based on MIL-STD-1750A [6] processor
design with very high throughput and large
memory requirements. It uses three types of
MCMs. One MCM contains Honeywell's

Generic VHSIC Spacebome Computer (GVSC)

five-chip set. The second MCM is a memory
module with 64K X 8 b architecture and containing
nine 8K X 8 SRAMs. The third MCM is
a cache memory containing six 8K X 8 SRAM
dies and a cache controller chip. These MCMs
have been fabricated in both copper/polyimide
thin-film multilayer (MCM-D) and cofired ceramic
technology (MCM-C).

9.2.3VLSI Chip-on-Silicon (VCOSj

Technology
The MCM technology called VLSI chiponsilicon (VeaS) developed by IBM Federal
Systems combines high-density silicon interconnect
technology with the flip-chip, C4
(controlled-collapse chip connect) die attach.
VCOS technology provides high I/O chip capacity
and low thermal resistance by the area
array of C4 solder bumps that permit wiring directly
beneath the chip [7]. The VCOS package
consists of a multilayer ceramic substrate, a silicon
interconnect wafer (SIW) on which all the
active elements are attached, IC chips (or dies),
and a protective cover to provide hermeticity.
The SIW is fabricated with the same process as
the 1.0 urn (or 0.8 urn) CMOS chip design.

MEMORY STACKS AND MCMs (3-D)

Three-dimensional (3-D) memory packaging
and interconnectivity, which can be considered
as an extension of 2-D MCM technology, provides
higher packaging density and improved
electrical performance because of lower interconnect
parasitics. The 3-D approach also reduces
the substrate size, module weight, and
volume. The footprints for 3-D packages vary
from a single die to MCMs. Three fundamental
packaging techniques have been developed for
3-D memory chip assemblies: packaged chips,
bare chips, and MCMs. There are other experimental
techniques such as stacked wafers and
folded flex circuitry that have not been commercialized
yet [10].

30 Memory Slacks (Irvine

Sensors Corporation)
In 1985, the Irvine Sensors Corporation
(ISe) began exploring 3-D die-on-edge stacking
technology as a more efficient alternative to the
existing planar Ie packaging approach. Subsequently,

two memory chip stacking technologies

were developed: short stacks and full stacks
[12]. The short stack puts 4-16 memory chips in

a "stack-of-pancakes" configuration to produce

a thick IC with typical dimensions of 1.25 X
0.65 X 0.025 ern'. The full stack can place up to
100 memory chips in a "loaf-of-bread" configuration,
with typical dimensionsof 2.5 X 1.25 X
0.65 em'. This full stack is typically interconnected
to the next higher level of assembly by
bump-bonding to a substrate or a wire-bonding
into a deep, custom-designed package. The
short stack is designed for wire-bonding or TAB
interconnection into the standard packages,
SMT, or chip-on-board mounting. The ISC process for
3-D memory modules begins by procuring chips to be
stacked in waferforms, and then applying a new
metallization layerto reroutethe chip leadsto the edge
of a device.The waferis then testedand thinned to 7 mil
or more. Then the IC chips aredicedout and laminated
to form short stacks or large stacks. The
stacked chips and stacking fixture are placed in
an ovenand bakedat the curing temperature.
9.3.3 3-0 Memory MCMs (GE-HOIITI)
GE-HOI technology, which was OrIgInally
applicable to 2-D MCMs, was extended to
3-D through a program for memory densification
by the application of z-plane lithography
(MDAZL). This was a collaborative effort between
ISC and Texas Instruments (TI), sponsored
by the Strategic Defensive Initiative
Organization (SOlO) [18]. The goals of the
MOAZL program were aimed at ISC to package
four memory chips in a short stack (with a form
factor of a single chip but thicker) and GE to integrate
those test assemblies into a hybrid wafer
scale integration (WSI) process. The MOAZL
approach used a modified configuration of the
ISC 3-0 traditional stacking process (discussed
earlier), in which the edges of individual chips
are perpendicularto the substrate and the "memory
cube" is interfaced to a mounting substrate
by a solder bump array laid down on the interconnect
face. In the MOAZL approach, the
stack consists of four chips (or more, if needed)

and a top surface ceramic interconnect cap chip.

The MOAZL stack and cap are mounted in a
planar fashion, similar to the ISC short stack
configuration

9.4 MEMORY MCM TESTING

AND RELIABILITY ISSUES
Memory MCM technology from the testability
and reliability points of view lies somewhere
between the chips and a board level system.
Therefore, a well-defined test strategy and reliability
screens are important for high-yield and
reliable MCMs. The availability of "knowngooddie" (KGD) fully tested and burned in for
memory and control logic functions is essential
for minimizing the rework and repair of final
MCM assembly. The yield of bare die currently
available for MCM assembly may vary widely,
depending upon the extent of wafer level testing,
device geometry and complexity, and the
semiconductor manufacturing process maturity.
In general, the effect of a memory die yield on a
projected MCM yield can be expressed by the
following equation.

where Yc = chip yield

NC = number of chips in MCM
assembly.
This means that even with memory (or
other logic control) die yields as high as 97%,
the chance of finding a defective chip in a 20chip MCM assembly is about 50:50. In addition
to the KGD requirements, known-goodsubstrate
(KGS) is also an important issue.
Some other strategies for high-yield and reliable
MCMs include the use of process monitors
(PMs) and other reliability test structures, design
for testability (DFT) and robust circuit design
techniques, high fault coverage testing and
accurate and efficient diagnostics. The MCM
test structures have been developed for process
verification and monitoring in terms of material
characterization, geometric tolerances, thermal

9.5 MEMORY CARDS

Memory cards are lightweight plastic and metal
cards containing the memory chips and associated
circuitry for use in notebook PCs and mobile
mobile
communication applications. They are intended
to serve as alternatives to the traditional
hard disks and floppy drives, and offer significant
advantages in size, weight, speed, and
power consumption. The standardization at the
hardware and data interchange level is provided
by the Personal Computers Memory Card International
Association (PCMCIA), and the Japan
Electronic Industry Development Association
(JEIDA) established memory card standards.
Additional applications for the memory cards
include printers, copiers, camcorders, medical
instrumentation, and industrial controllers.

9.5.1 CMOS SRAM Card (Example)

Hitachi developed a high-density CMOS
SRAM card organized as 1 Mword X 8 b or
512 k word X 16 b [36]. It consists of eight
pieces of 1 Mb SRAM devices sealed in TSOP
packages and mounted on a memory card
housed in a 68-pin, two-piece connector package.
Figure 9-23 shows the pinout and pin description
of this package [36]. Figure 9-24
shows a block diagram of this 8 Mb SRAM card
[36]. It operates from a single +5 V supply, has
a write protection switch, and conforms to
JEIDA 4.1IPCMCIA interfacing standards.

9.5.2 Flash Memory Cards

The combination of nonvolatility and reprogrammability
makes flash memory cards an
attractive alternative for low-power, portable,
and high-performance system applications. An
example is the Intel 4 Mbyte flash memory card
which conforms to PCMCIA 1.0 International
Standard, and provides standardization at the
hardware and data interchange level [39]. It uses
Intel's ETOX II flash memories, has 5 V read
operation, and 12 V EraselWrite operation. The
maximum specified time for a read operation
is 200 ns, and 10 J.1S is the typical byte write

9.6 HIGH-DENSITY MEMORY PACKAGING

FUTURE DIRECTIONS
ARPA has sponsored a project called UltraDense, in which the goal is to achieve high performance
through high packaging density for
high-throughput computing requirements [42].
In this parallel digital signal processing system
design, silicon-on-silicon MCM technology was
used for first-level packaging of lCs. Subsequently,
conductive adhesives are used for 3-D
implementation of the system that included a
digital signal processing (DSP) chip, an ASIC,
and 8 of 256K SRAMs.
Memory MCM and 3-D (memory cubing)
techniques are being used to increase memory
density for high-performance computer and
telecommunication systems, and in the military/
space environment. The future trend is toward
further memory densification using the
largest memory chips available (e.g., 4 Mb
SRAMs and 16 Mb DRAMs). Irvine Sensors
Corporation (ISC) has signed an agreement to
integrate their 3-D memory cubing process with
IBM's silicon-on-silicon technology. A feasibility
study was performed by using modified I~C
cubing process to fabricate DRAM cubes that
used 18-20 IBM 1 Mb DRAM chips. This cube
interconnected to the substrate by IBM flip-chip
technology was packaged in a metallized ceramic/
polyimide pin grid array with 160 I/o pins

8.2 FERROELECTRIC RANDOM ACCESS

MEMORIES (FRAMs)
8.2.1 Basic Theory
FRAMs utilize the ferroelectric effect,
which is the tendency of dipoles (small electrically
asymmetric elements) within certain crystals
to spontaneously polarize (align in parallel)
under the influence of an externally applied
electric field, and these elements remain polarized
after the electric field is removed. Then reversing
the electric field causes spontaneous
polarization (i.e., alignment of the dipoles) in
the opposite direction. Thus, ferroelectric materials

have two stable polarization states, and can

be modeled as a bistable capacitor with two distinct
polarization voltage thresholds. Since no
external electric field or current is required for
the ferroelectric material to remain polarized in
either state, a memory device can be built for
storing digital (binary) data that does not require
power to retain stored information.

8.2.2 FRAM Cell and Memory Operation

Figure 8-3(a) shows a schematic of a
single-ended FRAM cell that uses one transistor
and one capacitor cell similar to that of a standard
DRAM or EEPROM cell [6]. During a read
operation, the cell element is polarized and
charge transferred is compared to a referenced
cell or other fixed level to determine whether a
"1" or a "0" was stored. Figure 8-3(b) shows the
dual-element differential sense amplifier approach
used by the Ramtron Corporation

FRAM schematic of (a) a single-element memory cell

temperature excursions (e.g., to 125 and

175C) were found to cause a reduction in the

8.2.3 FRAM Technology Developments

An example of a commercial FRAM is
Ramtron Corporation's FM 1208S/1608S series
4KJ64K series devices which combine the flexibility
of a low-power SRAM with the nonvolatile
characteristics of an EEPROM. These
are fabricated in a 1.5 urn silicon gate CMOS
technology with the addition of integrated thinfilm
ferroelectric capacitors. These operate from
a single + 5 V power supply, and are TTL/
CMOS compatible on all the input/output pins.
FM 1208has 4K memoryorganizedas 512 X 8 b
and utilizes the JEDEC standard byte-wide
SRAM pinout. This device is specified for
250 ns read access, 500 ns read/write cycle time
and 10 year data retention without power.
A well-defined planarization process before
fabricating the capacitor to obtain a
smooth capacitor structure.
Since the barrier metal layer between
the capacitor bottom electrode and the
underlying layer is easily oxidized during
the annealing, causing increased
contact resistance, the oxygen diffusion
through the bottom electrode should be
eliminated.
The use of a dry etching process to obtain
the fine patterning since the plasma
etch causes capacitor degradation

8.2.4 FRAM Reliability Issues

Ferroelectric memories' major reliability
issues were discussed in Chapter 6 (see Section
6.3.5). Thermal stability, fatigue, and aging of
the ferroelectric RAMs are the key reliability
concerns. A study was performed on the FE film
capacitors to evaluate the effects of thermal excursions
on the remnant polarization level in
polycrystalline films [2)]. The reliability of ferroelectric
nonvolatile memory is limited bydegradation in the
value of suitable remnant polarization.
Typical FRAMs available on the
market are specified for the data storage and operating
temperature range of 0-70C. The elevated

8.2.5 FRAM Radiation Effects

In general, the FE capacitors and memories
made from thin-film PZT have shown high
radiation tolerance characteristics suitable for
space and military applications. Radiation testing
has also been performed on CMOSIFE integrated
devices, including the memories, to
determine whether the additional ferroelectric
processing causes significantdegradation to the
baselineCMOS process. Testresultsfor some of
these studies are summarized below:
In a total dose radiation-induced degradation
of thin-film PZT ferroelectric capacitors
study performed by Sandia
National Laboratories, the FE capacitors
fabricated through different processes
were irradiated using X-ray and Co-60
sourcesto 16 Mrad (Si) dose levels [16].
The capacitors werecharacterized for retained
polarization charge and remnant
polarization both before and after radiation
In a study conducted by Harry Diamond
Laboratories and Arizona State University,
thin-film sol-gel capacitors were irradiated
to 100 Mrad (Si) with 10 keY

X-rays [17].Test results showed that the

PZT FE films fabricated by the sol-gel
techniques degrade very little in terms
of amount of switchedenergy available,
up to 5 Mrad (Si) exposure. Above the
5 Mrad (Si) exposure, somedistortionin
the hysteresis loop was observed, and
there is a gradual loss of switched
charge out to 100 Mrad (Si). The type
and degree of hysteresis loop distortion
depended upon the polarization state
and the applied bias during irradiation.
Some of the postradiation-induced damage
could be annealed by repeated bias
cycling of the FE capacitor.
Another evaluation was performed by
Arizona State University in which solgel
derived PZT thin films were irradiated
to a total dose of 1 Mrad (Si) under
open-circuit bias conditions [18]. Test
results showed that the irradiation
changed the magnitude of the internal
bias fields and produced hysteresis
curve distortion, depending on the polarizationstate
of the capacitorbefore irradiation.
The postirradiation electrical
cycling makes the hysteresis loop symmetric
initially, but eventuallycauses fatigue
effects. Static I-V measurements
showed that irradiation changes the
switching current, but does not degrade the leakage current

FRAMs versus EEPROMs

In nonvolatile memory applications, the
EEPROM is an established technology that is
widely used, whereas FRAM fabrication is in
the development stages. The FRAMs appear to
have a good future potential. However, there
are some major reliability concerns such as
process uniformity control, thermal stability,
fatigue, and aging of the ferroelectric RAMs.
Some of the key differences in the basic storage
mechanisms and operating characteristics of
the two technologies can be summarized as follows:
FRAMs utilize magnetic polarization
storage techniques, in contrast to the
EEPROMs' charge tunneling mechanism,
and use a 5 V supply for all internal
operations instead of the 12-15 V
required by conventional EEPROM
technologies.
For FRAM cell programming, an electric
field is applied for less than 100 ns
to polarize nonvolatile elements,
whereas for standard EEPROMs, 1 ms
or more are needed to generate sufficient
charge storage at the gate element.
In EEPROMs, charge tunneling across
the insulating oxide layers degrades
characteristics of the oxides, causing excessive
trapped charge or catastrophic
breakdown. Therefore, typically, EEPROM
devices are guaranteed for
10,000-100,000 write cycles. According
to the manufacturer's reliabilitytest data,
the FRAMs which utilize the polarization
phenomenon can provide up to 10
billion (1010) write endurance cycles.