A DETAILED APPLICATION OF TL494 PSPICE MODEL IN DESIGNING

SWITCHING REGULATORS: AN EDUCATIONAL APPROACH

Chandra Shetty1, Anil Kadle2, A.B.Raju3, Member IEEE
1

Dept. of Electrical Engg., National Institute of Technology, Karnataka

Dept. of Electrical Engg., Anjuman Institute of Technology and Management, Bhatkal
3
Dept. of Electrical Engg., B.V.B College of Engg. Hubli
E-mail: 1chandra_shetty84@yahoo.com, 2anilkadle@gmail.com, 3abraju@bvb.edu
2

based on the information of the dedicated literatures

about TL494 architecture as the employment of TL494
Pspice model on OrCAD Capture is quite different from
hardware application report. For beginners like
undergraduate students, who would like to work in the
field of switching regulators it is not necessary to master
all the commercial PWM Chips. It is sufficient if the
students have adequate knowledge about at least one
PWM chip, which can be employed to analyze all kind
of switching regulators. All PWM chips have their own
merits and demerits. This paper focuses only on
application of TL494 Pspice simulation model for
switching regulators.
The reported work in [3] focus on inclusion of
soft-soft start characteristic into the Pspice model of
different commercially available PWM chips, but it
doesnt give any information on application of the
simulation model. The Cadence Design System has
furnished a piece of information about the application of
Tl494 Pspice model with OrCAD Capture in its website
[4], which is insufficient for beginners. Students who
are new to the OrCAD Capture find it very difficult to
work with TL494 simulation model without adequate
information about its proper application with the
software while carrying out their academic projects. If a
student becomes familiar with any one of the simulation
model of PWM chips, it would help him to work with
other PWM chips as well, as principle of working of
different PWM chips remain almost same. Considering
all these difficulties to work with the model, we have
made an effort to deal in detail with the application of
TL494 Pspice model.

Abstract: This paper describes the application of

TL494 PSPICE MODEL with OrCAD Capture for
analyzing switching regulators, which can assist
beginners like undergraduate students in understanding
the switching regulators. This paper mainly focuses on
application of simulation model as none of the
literatures provides required information to work with
TL494 simulation model. Although TL494 chip is a
very simple chip as far as hardware is concerned, it is
not easy work with Pspice model of TL494 without
adequate knowledge about the Pspice software. The
application of this chips simulation model with OrCAD
Capture is demonstrated with the help of buck
converter. This application report can also be extended
to other non-isolated as well as isolated converters.
Keywords: TL494 Pspice Model, OrCAD Capture,
convergence, RELTOL, V_PWM, INPUT_VTH,
V_DTC.
INTRODUCTION
Pulse width modulation (PWM) is a very important
aspect in power electronics course. There are many
dedicated commercially available PWM chips like
SG1524, TL494 e.t.c. The most popular one is TL494
due to its low cost, simplicity and robustness. In [1], the
application of architecture of TL494 chip in designing
switching regulators is described, but no attention has
been given towards the application of simulation model.
We can obtain pulse width modulation using analog
behavior modeling (ABM) tool in PSPICE [2], but this
approach does not give any required information about
hardware implementation of the chip. The simulation
model of actual device is very important which can
assist in developing physical converter.
The Pspice model of the TL494 IC can be found
in controller.olb library of the OrCAD software
package. Few websites have provided the Pspice model
of TL494, but none of them has furnished required
information about the detailed application of this model
with the OrCAD Capture. The Pspice model provided
by them cannot be guaranteed that the model is going to
work with OrCAD Capture. It is better to work with
model that is readily available in the Pspice Library of
OrCAD software and tested by Cadence Design System.
We cant directly use Pspice model on schematic page

PSPICE MODEL OF TL494

As it is already mentioned in the introductory part, the
Pspice model of TL494 can be found in controller.olb.
The schematic of this model is shown in Fig. 1. The
attribute V_DTC refers to the dead time control offset
voltage at pin 4 of the controller. This sets the default
dead time controller for the TL494 controller. If there is
a slow ramp connected to the dead time control input,
the dead time between the outputs will change. The
attribute V_PWM refers to the PWM comparator offset
at pin 5 of the controller. The values can range from
minimum = 0.5, typical = 0.7 and maximum 1V. The
attribute PERIOD specifies the time period of the
157

common emitter configuration (Fig. 3). The frequency

considered here is 100 KHz i.e. period equal to 10us.
The required settings for the proper simulation of the
model are shown in Table 1. If we run the simulation
with default settings, the simulation will fail due to
convergence problem. The iteration limit is increased
from 10 to 100 [5]. Few literatures recommend
changing the default value of RELTOL to solve the
convergence problem. We should not change default
relative tolerance RELTOL value 0.001. For TL494
Pspice model, changing this value would result in error
message.

oscillator. INPUT_VTH is the minimum PWM

comparator voltage at pin 3. It produces a duty cycle of
0%. This voltage is sum of the sawtooth voltage and
the comparator offset voltage (V_PWM).
Attributes

Used For

V_DTC

DEAD TIME CONTROL

OFFSET

V_PWM

PWM COMPARATOR OFFSET

INPUT_VTH

MINIMUM PWM
COMPARATOR VOLTAGE

OVERVIEW OF THE SWITCHING SIGNALS

The schematic diagram for producing switching signals
is shown in Fig. 2. The switching signals are shown in
Fig. 3. The switching signal can be obtained either by
emitter follower configuration or common emitter
configuration. The gate signal G1 is obtained from
emitter follower configuration and G2 is obtained from

Fig. 1. Pspice model of TL494.

Fig. 2. Schematic diagram for producing switching signals for a converter.

Fig. 3. Switching signals for the converters operation.

158

Parameter

New Value

Default Value

RELTOL
VNTOL
ABSTOL
CHGTOL
GMIN
ITL1
ITL2
ITL4

0.001
1u
1p
0.01p
1.0E-12
150
20
100

0.001
1u
1p
0.01p
1.0E-12
150
20
10

offset (V_PWM) is set to zero and the parameter

INPUT_VTH is assigned with a value, which is equal to
peak value of the sawtooth wave so that the value of the
dc voltage to be connected at pin no. 3 can be calculated
easily which is described in the above paragraph.
Schematic of the power stage is shown in Fig. 6. The
output voltage is shown in Fig. 7.
CLOSED LOOP CONTROL
Fig. 8 shows Pspice schematic of the PWM stage. For
closed loop control, the main switch should be driven
from the signals taken from emitter follower
configuration. If the synchronous rectifier is used in
place of diodes for rectification, then it must be driven
from the signal taken from common emitter
configuration. The TL494 Pspice model is having two
error amplifiers. Any one of the error amplifier can be
used for regulation with proper compensation. The
unused error amplifier terminals must be grounded. For
the SG1524 family of chips, reference voltage is given
to positive terminal of the error amplifier. For TL494
family of chips, reference voltage must be given to
negative terminal of the error amplifier as it is having
opposite internal sense [7]. The reference
voltage,
which is 3.3V for this example, is obtained from
internal voltage source of 5V by using voltage divider
resistances i.e 1.7k and 3.3k (shown in the Fig. 8).
Soft starting components are also included in the PWM
stage. The procedure for calculation of soft starting
component values can be found in [1]. Pin no. 13 is
grounded for parallel output.

Table 1. Simulation Settings

OPEN LOOP CONTROL
For the open loop control of switching regulators, ON
period of the gate signal i.e. duty ratio must be adjusted
to get the required output that can be accomplished by
varying the DC voltage at pin no. 3. The signal for
driving the switch must be obtained from common
emitter configuration. The unused error amplifier
terminals must be grounded. As the frequency of the
switching regulator is adjusted in the schematic of the
Pspice model, the pin no.5 and 6 can be grounded using
high value resistances [6]. The physical TL494 IC uses
the resistor and capacitor combination to set the
frequency using the following relation:

(1)
Buck converter is used as a design example to
demonstrate the approach. The design specifications of
the converter are shown in Table 2.
Vs

50V

D
Vo
L
C
f

0.4
20V
400uH
100uF
20kHz

20

Buck Converter with Diode Rectifier

The Table 3 shows design specifications for closed loop
buck converter with diode rectifier. The driving signal
for the switch is obtained from emitter follower
configuration. To avoid the convergence problem,
following changes has been made to .OPTIONS
settings
RELTOL=0.001,
VNTOL=10u,
ABSTOL=0.001u, CHGTOL=0.01p, GMIN=0.1n,
ITL1=1000. ITL2=1000, ITL4=1000. If the simulation
carried out with default settings, the simulation will fail
with convergence problem. Here, off page connectors
are used for connecting compensating components to
error amplifier. The power stage of the converter is
shown in Fig. 9. The output voltage is shown in Fig. 10.

Table 2. Design Specifications Of The Buck Converter

The PWM stage of the converter is shown in Fig. 4. The
duty cycle is controlled by adjusting the voltage source
at pin no. 3 in Pspice model. To obtain the desired duty
cycle, the magnitude of the voltage source to be
connected at pin no. 3 is obtained using the following
equation. The required magnitude of the voltage source
= duty cycle peak value of the sawtooth i.e 3V. For
this example, the duty cycle is 0.4. So, the required
value of the magnitude of voltage source to be
connected at pin no. 3 is 0.43=1.2 (Fig. 4). The
corresponding ON period is 20us as shown in Fig. 5. In
the schematic of the Pspice model, PWM comparator

Vs
Vo
L

6V
3.3V
100uH

C
f
R

100uF
100kHz
4

Table 3. Design Specifications

159

Fig. 4. Schematic for producing gate signal for open loop control.

Fig. 5. Switching signal for the converter from common emitter configuration.

Fig. 6. Schematic of the power stage.

Fig. 7. Output voltage.

160

Fig. 8. Schematic of the PWM stage.

Fig. 9. Schematic of the power stage.

161

Fig. 10. Output voltage

Buck Converter with Synchronous Rectifier

the converter, discussed above, as design example and

replacing diode rectifier by synchronous rectifier in the power stage. The PWM stage for this example is same
as above. The driving signal for synchronous rectifier is
obtained by common emitter configuration, described
by the word OFFPAGELEFT-2, as shown in Fig. 11.
The output voltage is shown in Fig. 12.

Synchronous buck converters are employed for the

improved efficiency. The TL494 PWM chip can also be
used to operate switching regulators with synchronous
rectifiers. This concept is demonstrated by considering

Fig. 11. Schematic of the power stage.

Fig. 12. Output voltage.

162

CONCLUSION

[2] Rashid. M.H(1995): SPICE for Circuits and

Electronics Using Pspice, Prentice - Hall.

All the aspects of simulation model of TL494 PWM IC

in designing switching regulators have been addressed
in detail with the examples. As all of the literatures
about TL494 PWM IC converge on architecture of this
chip, this article, specifically focus on simulation model,
would be great helpful for beginners like undergraduate
students who undergo power electronics course. The
reported work can also be extended to other converters.

[3] Fu-Yan Shih, Yie-Tone Chen, Dan Y Chen (1995):

Pspice-Compatible Model of PWM IC for
SwitchingPower
Converters
with
Soft-Start
Characteristic, IEEE Conference on PEDS, Vol.1,
pp. 335-340.

ACKNOWLEDGEMENTS

[4] Orcad.com. (2012) Design community in action.

[Online].
Available:
http://www.orcad.com/
community.pspice.faq.aspx.

National Institute of Technology Karnataka, India,

supported this work.

[5] Daniel.W.Hart (2011): Power Electronics, Tata

Mcgraw Hill.

REFERENCES

[6] Pspice Users Guide (2000), 2nd edition, Cadence

Design System.

[1] Patrick Griffith (2005): Designing switching

regulators with the TL494 (2005), Texas
Instruments.

[7] H. Dean Venable, Venable Industries (1983): The k

factor: a new mathematical tool for stability analysis
and synthesis, Reference Reading #4.

163

A SIMPLIFIED APPROACH TO THE FIRST ORDER APPROXIMATIONS

OF A CLOSED LOOP, NON ISOLATED DC-DC CONVERTER WITH
SYNCHRONOUS RECTIFIER CIRCUIT BEHAVIOR BY USING THE
ORCAD PSPICE
Chandra Shetty1, Anil Kadle2, A.B.Raju3, Member IEEE
1

Dept. of Electrical Engg.,National Institute of Technology Karnataka

Dept. of Electrical Engg., Anjuman Institute of Technology and Management, Bhatkal
3
Dept. of Electrical Engg. B.V.B College of Engg. Hubli
E-mail: 1chandra_shetty84@yahoo.com, 2 anilkadle@gmail.com,
2

abraju@bvb.edu

In some dc-dc converters, the rectifying diodes are

replaced by MOSFETS, known as synchronous
rectifiers, to improve the efficiency of the converter and
this paper describes simplified simulation process only
for closed loop, non-isolated dc-dc converter with
synchronous rectifier circuits. While the reported work
in [1-5] is claimed to emphasize on circuit simulation of
power electronic circuits, little attention has been given
to the detailed simulation of closed loop dc-dc converter
circuits. The proposed approach [6] adopts Pspice A/D
where the circuit is described by statements and analysis
commands, which makes simulation a cumbersome
process. In this paper, the schematic version of Pspice
i.e., ORCAD PSPICE is adopted for the simulation.
ORCAD PSPICE is having all the necessary tools
required for analyzing the power electronic converter
circuits. The device models of most of power electronic
devices are readily available in Pspice library, which
makes the simulation an easy process. The device
models can be used in the schematic capture with the
modifications of certain parameters depending on the
requirement. Model editor tool is also provided along
with this software to edit the model of the devices to
meet the design specifications. User defined libraries
can also be created which is an added advantage of this
software. The device Pspice models can be downloaded
from device manufacturers website if the required
device model is not provided in the Pspice library of the
ORCAD PSPICE as most of the manufacturers provide
Pspice model of their manufactured devices to support
the consumers for simulation and practical
implementation of the device. Some of the websites
such as http://www.orcad.com/, http://www.emaeda.com/ e.t.c. have given, provided by the
manufacturers, the Pspice models of the certain devices
whose Pspice models are not available on the Pspice
library of the few old version of the ORCAD PSPICE.
We can also find information about the application of
these device models with OrCAD capture on these
websites.
A comprehensive survey of ORCAD PSPICE in
the analysis, first order approximations of circuit
behavior, of a closed loop, non-isolated DC-DC

Abstract: In this paper, we present the significance of

computer simulation program, such as ORCAD
PSPICE, in analyzing, first order approximations of
circuit behavior, a closed loop, non-isolated dc-dc
converter with synchronous rectifier circuit. Following
techniques have been adopted to simplify the process of
simulation. They are: (1) Ideal switches are incorporated
in the power stage of the converter to eliminate the gate
diver requirement which in turn reduces the simulation
run time; (2) Diodes are connected in series with
switches, which eliminates dead time control circuit, to
prevent cross conduction of switches and (3) TL494
Pspice model, which is readily available in library of
most of the versions of the ORCAD PSPICE, is
employed for pulse width modulation. As an example,
non-inverting synchronous buck boost converter is
considered for demonstrating the approach. Simulation
was carried out for an input voltage range of 6 to 35V
and load resistance was varied from 12 to 48 Ohms.
Output voltage was regulated at 12V for both input
voltage and load current perturbation. Physical
prototype was implemented and simulation result was
tested for steady state output.
Keywords:
ORCAD
PSPICE,
non-inverting
synchronous buck boost converter, TL494, Sbreak
Switch.
INTRODUCTION
Computer tools cannot replace the traditional methods
for mastering the study of electric circuits. They can,
however, assist in the learning process by providing a
visual representation of a circuits behavior, validating a
calculated solution, reducing the computational burden
of more complex circuits, and iterating toward a desired
solution using parameter variation. This computational
support is often invaluable in the design process.
ORCAD PSPICE is one of the popular computer tool
applied in electrical engineering. This software package
includes different device models required for
simulation.
309

converter with synchronous rectifier circuit presented

with the example, non-inverting synchronous buck
boost converter using voltage mode control. For
simulation purpose, Sbreak switch [7] is employed in
the power stage rather than actual device model for
simplifying the switching and TL494 Pspice model [8]
is used for pulse width modulation. TL494 is one of the
most commonly used chips in power electronics
engineering for pulse width modulation. Actual device
model of TL494 is used for simulation as replacing it
with an equivalent ideal model would not give proper
information
about
TL494
chips
practical
implementation in laboratory. Thus, combining ideal
model with actual device model for simulation offers
few advantages like elimination of cross conduction
without the requirement of dead time control circuit,
exclusion of gate driver requirement, and reduction in
simulation time while keeping the simulation result of
the converter satisfactory.
The model parameters of all the elements used in
the circuit must be adjusted, if required, to meet the
design requirement. The switches and diodes, employed
in the power stage of the converter, are idealized by
setting for the switches and for
the diodes. Transient analysis and parametric sweep
analysis [9] are adopted for carrying out the simulation
process. The experimental result of the converters
steady-state output confirms the simulation result. The
methodology proposed in this paper can also be adopted
for the simulation of other closed loop, non-isolated dcdc converter with synchronous rectifier circuits.

NON- INVERTING
SYNCHRONOUS BUCK
BOOST CONVERTER
The non-inverting synchronous buck boost converter
[10, 11] used as a design example to demonstrate the
significance of ORCAD PSPICE in analyzing a closed
loop, non-isolated dc-dc converter with synchronous
rectifier circuit behavior. The circuit diagram of the
converter is shown in Fig. 1. Converter specifications
are: an input of 6-35V, an output of 12V, a load
resistance of 12-48 Ohms, and f =100 KHz.
Power Stage Design
Selection of Inductor: The value of inductance is
chosen to assure continuous conduction mode and it is
designed for the worst-case input 6V and maximum
current of 1A [12].



(1)
(2)

The voltage across the inductor when the switch is ON

is
  
So the voltsuseconds is

Fig. 1. Non inverting synchronous buck boost converter

310

(3)

  
(8)
 
(9)
 

(10)
 
(11)
 
(12)
 
(13)
 
(14)
From eq. (8) to eq. (14), the compensating component
values obtained are: Boost = , choose
,  ,  ,  ,
 ,  .
4) Verification of above designed component values
for desired phase margin and gain at cross over
frequency using PSPICE simulation.
A Pspice simulation of the control loop in Fig. 4 gives
the desired phase margin of approximately and gain
of approximately 0dB as shown in the Fig. 5, verifying
the design.

(4)
Ds<
Using the equation
  
(5)
  
(6)
Therefore,
   
(7)
Based on eq. (1) to eq. (7), the values obtained
are: , ,
,   for the ripple
factor of ,  since   ,
 .
The value of inductor selected is 47uH.
Selection of Capacitor: The value of capacitor chosen
is 220uF.
ESR of Filter Components: The measured value of the
ESR of the inductor is 0.2ohm. The ESR of the
capacitor is assumed as 0.1ohm.
Feedback Compensation: The K-factor approach [13]
has been adopted for designing the compensation
component values. Type-3 error amplifier is used to get
enough phase boost. The following is a design
procedure for the type3 compensated error amplifier
[14].
1) Choose the Crossover Frequency.
The crossover frequency of the total open-loop transfer
function (the frequency where the gain is 1, or 0 dB)
should be well below the switching frequency. Let
.

Sampling Network
Assume a reference voltage of 2V and choose 
. Using the voltage divider rule,
     
(15)
The obtained value of  is

Fig. 2. The ac circuit used to determine the frequency

response

Fig. 3. Gain and phase plot without compensation

2)A Pspice Simulation to determine the Gain and

Phase angle at  .
The ac circuit used to determine the frequency response
is shown in Fig. 2. AC sweep analysis option from
simulation setting is chosen to obtain the frequency
response by varying the frequency from 10Hz to 100
KHz as shown in Fig. 3. A PSPICE simulation of the
frequency response of the filter with load resistor (Fig.
3) shows that the converter gain at 10 kHz is -11.922dB
and phase angle is. The PWM converter has
a gain of . The combined gain of
the filter and PWM converter is then -11.922dB - 9.5dB
= -21.5dB.
3) Computation of component values of error
amplifier based on the above information.
G = Amplifier gain at cross-over = 21.5dB
M = Desired Phase Margin (degrees) =
P = Modulator Phase Shift (degrees) =

Fig. 4. The ac circuit for determining the frequency

response with compensation
311

Fig. 5. Gain and phase plot with compensation

DISCUSSION ON ORCAD SCHEMATIC OF THE
CONVERTER AND SIMULATION MODELS OF
THE DEVICES

device model. The Pspice model of this chip is available

in controller.olb.
We have to modify the parameters such as
frequency, reference voltage etc as shown in the
schematic of the PWM stage. For the TL494 family
chips, the reference voltage is given to inverting
terminal as they are having opposite internal sense [13,
15]. The reference voltage for error amplifier obtained
using voltage divider circuit from the TL494 internal 5V
reference regulator [15]. Soft start circuit [15] is also
integrated in the PWM stage. The control signals for M1
and M2 are tapped using emitter follower configuration
(OFFPAGELEFT-1). The switching signals for M3 and
M4 are obtained from common emitter configuration
(OFFPAGELEFT-2). The unwanted pins of the chip are
connected to ground with high resistances.

Power Stage
The schematic diagram of power stage of the converter
is shown in Fig. 6. The swiches of converter are
implimented using Sbreak Switch model. The diode is
connected in series with switch to prevent the reverse
conduction of the switch. The series connected diodes
also prevent simultaneous conduction of switches
without the need of additional dead time control circuit,
which reduces the complexity of the design as well as
the simulation run time for steady state output. Off
page connectors [9] are used for connecting the whole
project drawn on different pages.
Sbreak Switch: Sbreak switch Pspice model is give by
.model Sbreak Vswitch Roff=1e6 Ron=0.01 Voff=0.0
Von=1.0. Here we have to edit the Sbreak switch
model to make it an ideal switch.
Diode: For simulation purpose, Dbreak is used which
works approximately as an ideal diode [14] with
emission coefficient n=0.001. The default value of
emission coefficient in the vendor model is n=1.
Capacitor and Inductor: For capacitor and inductors,
we can use PSPICE model from PSPICE library [7]
breakout.olb.

SIMULATION RESULTS
Simulation is carried out for input variation of 6V to
35V and load current variation of 0.25A to 1A. The
simulation run time given is 10ms to get the steady state
output but run time of 5ms would have been enough to
get the steady state output, which would save the time.
To avoid the convergence problem, following changes
has been made to .OPTIONS settings RELTOL=0.001,
VNTOL=10u, ABSTOL= 0.001u, CHGTOL=0.01p,
GMIN=0.1n, ITL1=1000, ITL2=1000, ITL4=1000.
The Fig. 8 shows simulation result for the input range of
6V to 35V (i.e., 6V, 10V, 15V, 20V, 25V, 30V, and
35V) and maximum load current of 1A using transient
and parametric sweep analysis. The similar simulation
results can also be obtained for different load currents
by changing the load resistance in the schematic of the
power stage. Fig. 9 shows load voltage, inductor
current, and capacitor current for maximum load current
and worst-case input. Switching signals for M1, M2,
M3, and M4 for worst-case input 6V and maximum
current
of
1A
is
shown
in
Fig.
10.

PWM Stage
The schematic of the PWM stage is shown in Fig. 7.
Off Page Connectors are used for connecting
compensating elements to the error amplifier of TL494.
We can directly use TL494 Pspice model given by the
software vendors without editing the model except few
required parameters variations on the schematic of the
312

Fig. 6. Pspice schematic of the power stage

313

Fig. 7. Pspice schematic of the PWM Stage

Fig. 8. Simulation result for input range of 6V to 35V (i.e., 6V, 10V, 15V, 20V, 25V, 30V, and 35V) and maximum
current of 1A using transient and parametric sweep analysis

Fig. 9. Load voltage, inductor current, and capacitor current for maximum load current of 1A and worst-case input of
6V

314

amplitude causes a corresponding linear decrease of

output pulse width. The operating waveform is shown
in Fig. 12.
The converter switching frequency is 100Khz.
Choose and substitute in eq. 17 to get
. Soft start circuit [15] is incorporated in
the PWM stage to reduce stress on the switching
transistors at start up.

HARDWARE IMPLEMENTATION
For hardware implementation, TL494 [15] is employed
for pulse width modulation, IR2110 [16] is used as a
gate driver, and IRF150 as a switch.
PWM Module
The TL494 is a fixedfrequency pulse width modulation
control circuit, incorporating the primary building
blocks required for the control of a switching power
supply. The basic circuit diagram is shown in Fig.11.
TL494 has 16 pins. Its operating frequency is
1~300kHz. An internal linear sawtooth oscillator is
frequencyprogrammable by two external components,
RT and CT. The oscillator frequency is determined by:



Driver Circuit
The output of the TL494 cant be used directly to drive
the MOSFETS as the outputs are referenced to the
ground. IR2110 is chosen to drive the MOSFETS. It
can drive the high side MOSFET with the help of
bootstrap circuit, which creates floating supply for the
high side MOSFET from the ground referenced
switching signal, the output of TL494.
Each IR2110 gate driver can drive one high side
MOSFET and one low side MOSFET. Consequently,
two IR2110 gate drivers are required for operating all
the four switches of the converter. Resistor diode
network [16], which introduces dead time, employed for
preventing simultaneous conduction of the low side and
high side MOSFETS. The full schematic diagram of
the experimental prototype is shown in Fig. 13.

(16)

Output pulse width modulation is accomplished by

comparison of the positive saw tooth waveform across
capacitor CT to either of two control signals. The NOR
gates, which drive output transistors Q1 and Q2, are
enabled only when the flipflop clockinput line is in low
state. This happens only during that portion of time
when the saw tooth voltage is greater than the control
signals. Therefore, an increase in controlsignal

Fig. 10. Switching signals for M1, M2, M3, and M4 for worst-case input 6V and maximum current of 1A

315

Fig. 11. The Basic Circuit Diagram of TL494

Fig.12. Operating Waveforms

316

Fig.13. Full schematic diagram of the converter prototype

other closed loop, non-isolated dc-dc converter with

synchronous rectifier circuits. In summary, the
development of the converter has been very comfortable
by using the ORCAD PSPICE with the adaptation of
simple simulation teqniques.

TESTING OF SIMULATION RESULTS

The simulated result was tested, by implementing the
physical prototype converter, for the steady state output.
The regulation is satisfactory for full range of input
voltage with lower load currents. At higher load
currents, regulation is maintained only for higher input
voltages due to practical limitations.

ACKNOWLEDGEMENTS
National Institute of Technology Karnataka, India,
supported this work.

CONCLUSION

REFERENCES

A detailed application of ORCAD PSPICE for

analyzing, first order applications of circuit behavior, a
closed loop non-isolated dc-dc converter with
synchronous rectifier circuit has been presented using
an example. Ideal switches and diodes have been
employed in the power stage of the simulation circuit of
the converter to simplify the process of simulation. As
the ideal switches are used, the simulation results are
first order approximations of circuit behavior, which
gives sufficient data for initial investigation. The
physical prototype converter is implemented and tested
for steady state output. Experimental result is
satisfactory. This approach can also be extended to the

[1] A.B. Raju and S.R. Karnik (2005): SEQUEL: A

Free Circuit Simulation Software as an Aid in
Teaching the Principles of Power Electronics to
Undergraduate Students, ICETET-09, Nagpur,
India, pp.681-686.
[2] Daniel W Hart (1993): Circuit Simulation as an Aid
in Teaching the Principles of Power Electronics,
IEEE Transactions on Education, Vol.36, No.1, pp.
10-16.
317

[9] Pspice Users Guide (2000), 2nd edition, Cadence

Design System.

[3] Ned Mohan, William P Robbins, Tore M Undel and

and Robert Nilssen (1994), Simulation of Power
Electronic and Motion Control Systems,
Proceedings of the IEEE, Vol.82, No.8, pp.12871302.

[10]B. Sahu and G. A. Rincn-Mora (2005): A Low

voltage, Dynamic, Non inverting, Synchronous
buck-boost converter for portable Application,
IEEE Transactions on power electronics, pp.443452.

[4] Mahesh B Patil, Shyama P Das, Avinash Joshi and

Mukul Chandorkar (2002): A New Public-Domain
Simulator for Power Electronic Circuits, IEEE
Transactions on Education, Vol.45, No.1, pp.79-85.

[11]Jaw-Kuen Shaiu,Chun-Jen Cheng (2009): Design

of a non-inverting synchronous buck-boost DC-DC
converter, Elsevier Journal of Robotics and
Computer-Integrated Manufacturing, pp.263267.

[5] Ibrahim Chamas, Mahmoud A El Nokali (2004):

Automated PSpice Simulation as an Effective
Design Tool in Teaching Power Electronics, IEEE
Transactions on Education, Vol. 47, No.3, pp.415421.

[12]Marty Brown: (2007) Power sources and supplies,

world class designs, Newnes press-USA.
[13]H. Dean Venable, Venable Industries: The k
factor: a new mathematical tool for stability analysis
and synthesis, Reference Reading #4.

[6] N.D.Mohammed,
M.R.Rashid,
A.H.MYatim,
N.R.N.Idris (2005): Design of Power Stage and
Controller for DC-DC Converter Systems using
PSPICE, IEEE Conference on PEDS, Malasiya,
Vol. 2, pp. 903-908.
[7] Rashid.M.H(1995): SPICE for Circuits
Electronics Using Pspice, Prentice - Hall.

[14]Daniel.W.Hart (2011): Power Electronics, Tata

Mcgraw Hill.

and
[15]Patrick Griffith (2005): Designing switching
regulators with the TL494, Texas Instruments.

[8] Fu-Yan Shih, Yie-Tone Chen, Dan Y Chen (1995):

Pspice-Compatible Model of PWM IC for
Switching Power Converters with Soft-Start
Characteristic, IEEE Conference on PEDS, Vol.1,
pp. 335-340.

[16]Application note AN-978 (2005), International

Rectifiers.

318

2014 Fourth International Conference on Advances in Computing and Communications

Studying the Dynamics of the Second-Order DC-DC

Converter with Single and Multi-Loop Feedback for
the Optimum Bandwidth
Chandra Shetty, Member, IEEE
Department of Electrical and Electronics Engineering,
National Institute of Technology Karnataka, India
Email:chandra_shetty84@yahoo.com
down converter, example second order converter, is evaluated
with both single loop and multi loop feedback.

AbstractAs far as the complexity of the current mode

control is concerned, illogical choosing of the phase cross over
frequency for a converter doesnt bring any significant
advantages over the voltage mode control. So, one has to select
the bandwidth carefully so that benefits of the current mode
control will trade off with the complexity of implementing the
scheme. The reported work emphasizes on the importance of
choosing the optimum bandwidth in the current mode control
which can claim all the benefits of this complex current mode
control scheme. The advantages are: a) reduction in the order of
the controller due to decreased phase boost demand b) scaling
down in the size of the capacitor, inversely proportional to cross
over frequency, of the compensator network and consequently
demands very less current to drive as a network which prevents
overloading of the output of the operational amplifier and, c)
improved response speed. In this paper, for demonstration
purpose, the dynamic performance of the non inverting
synchronous up down converter, second order converter, is
carried out for both the voltage mode and the current mode
feedback with different cross over frequencies. The simulation is
carried out in Pspice.

Although the voltage mode control is easy for

implementation, it has shortcomings like poor dynamic
performance. On the other hand, the current mode control has
improved dynamic response but demands slope compensation
when the duty is above 0.5, otherwise the converter will enter
into sub harmonic oscillation. There are three types of current
mode control: the peak current mode, the valley current mode
and the average current mode control. In this paper the peak
current mode control has been employed to stabilize the loop.
Since the example converter duty cycle is less than 0.5, the
loop is stabilized without the slope compensation.
An effort has been made through this work to demonstrate
the fact that the current mode control can bring the
considerable amount of benefits into the dc-dc converter
system when proper bandwidth is chosen while designing the
controller for the current feedback. For illustration purpose,
the non inverting synchronous up-down converter [4]-[6] is
considered. The K-factor approach [7] is applied for obtaining
the compensation network for both the current mode control
and the voltage mode control.

Keywords current mode control, non inverting synchronous

up-down converter, pspice, phase cross over frequency, second
order converter, type-II compensation, type III compensation,
voltage mode control.

I.

INTRODUCTION

II.

OR the last few years, a lot of research work has been

carried out, analog or digital domain, about the voltage
mode and the current mode control feedback [1]-[3]. It
has been proven that the performance of current mode control
is better than the voltage mode in spite of its complexity.
However, no literature explain about the best cross over
frequency which makes the current mode control to bring
considerable benefits, including reduced order of the
controller with scaling down of capacitor and hence cost of the
compensator network and better transient performance, into
the converter system over the voltage mode control by
considering the complexity of implementing the scheme.

The converter considered here for illustration purpose is

the non-inverting synchronous up-down converter as shown in
Fig.1. The converter is operated in continuous conduction
mode for both types of controllers. The design specifications
of the converter are shown in Table I.

The published work on the current mode control provides a

range of cross over frequencies for which this type of control
is valid. However, the current mode control is useful only if
one moves to extreme end of this range. In this report the
dynamic performance of the non inverting synchronous up978-1-4799-4363-0/14 $31.00 2014 IEEE
DOI 10.1109/ICACC.2014.89

EXAMPLE CONVERTER

Fig. 1. Noninverting synchronous up down converter.

352

TABLE I

TABLE II
COMPENSATOR COMPONENT VALUES FOR DIFFERENT CROSS
OVER FREQUENCIES

DESIGN SPECIFICATIONS OF THE NON-INVERTING UP-DOWN

CONVERTER

Bandwidth
Parameter

III.

Compensating network elements values

Value

Vs

25V

0.32

Vo

12V

47uH

220uF

100kHz

20

10k

C1=1734pf, C2=135pf,
R3=781ohm

20k

C1=200pf, C2=25pf,
R3=1.25K, C3=2nf

R1=10k,
R1=10k,

R2=34k,
R2=119k,

VOLTAGE MODE CONTROL

Voltage mode control is the most preferred method of

stabilizing the loop due to its simplicity. However, it demands
higher order converter for controlling the loop due to the
additional pole introduced by the inductor of the power stage
which is not present in case of the current mode control since
the inductor current is the directly controlled variable along
with output variable. Bode plots of power stage transfer
function is shown in Fig. 2. Phase margin considered here is
ninety degree. Since the required phase boost is more than 90
degree, third order controller, known as PID controller or type
III compensation, as shown in Fig. 3, is employed for
compensating the power stage frequency response.

(a)

For pulse width modulation, integrated circuit, TL494

PWM chip, is used. The compensator network elements for
different cross over frequencies are shown in Table II.
Corresponding converter dynamic performance is shown in
Fig. 4.
(b)
Fig. 4. Transient response for different cross over frequencies with voltage
mode control: (a) 10kHz and (b) 20kHz.

IV.

CURRENT MODE CONTROL

Because the inductor current is being controlled directly,

the effect of inductor in the feedback loop is eliminated,
converting a second order control system into a first order
system by removing inductor pole from the loop. This makes
the resulting system much easier to stabilize. Other advantage
is current limit protection is easily implemented, by limiting
the maximum value of error signal. However, the current
mode control has several complications like the problem of
instability at a duty cycle greater than 0.5. This difficulty can
be worked out by using the slope compensation to the control
voltage. The bode plot considering inductor current as a state
variable is shown in Fig. 5. The phase cross over frequencies
considered here are 10 kHz, 20 kHz, 40 kHz and 66 kHz.
Since the phase boost is less than 90 degree, with phase
margin 90 degree, at all phase cross over frequencies, type-II

Fig. 2. Bode plot of power stage for voltage mode control.

Fig. 3. Type III network for compensating the power stage in voltage mode
control.

353

compensation, as shown in Fig. 6, is enough shape the

frequency response of the power stage.
The compensator network elements for different cross over
frequencies are shown in Table III. Accordingly, the transient
response is evaluated for different frequencies 10 kHz, 20
kHz, 40 kHz and 66 kHz as shown in Fig. 7. For pulse width
modulation, discrete circuitry, consist of uA741, LM111, SR
flip-flop, is employed.

(b)

(c)

Fig. 5. Frequency response of power stage for the current mode control.

(d)
Fig. 7. Dynamic response for different bandwidths with the current mode
control: (a) 10kHz (b) 20kHz (c) 40kHz and (d) 66kHz.

Fig. 6. Schematic diagram of a type II amplifier.

TABLE III
COMPENSATOR COMPONENT VALUES FOR DIFFERENT CROSS
OVER FREQUENCIES
Bandwidth

Compensating network elements values

10khz

C1=268pf, C2=103pf, R1=10k, R2=112k

20khz

C1=53pf, C2=56pf, R1=10k, R2=105k

40khz

C1=16.6pf, C2=40pf, R1=10k, R2=285k

66khz

C1=4.8pf, C2=24pf, R1=10k, R2=557k

V.

SIMULATION RESULTS AND DISCUSSION

The speed of response for both the voltage mode and the
current mode control with different bandwidth has been shown
in Table IV. It is obvious from the Table IV that the settling
time will decrease with increase in bandwidth, which is a
known fact. There is no appreciable difference in the settling
time as it is moved towards the higher bandwidth. However,
the size of the capacitor of the compensating network will be
scaled down. If we select the bandwidth of 10 kHz for the
current mode control, the complexity of control scheme
implementation will prevail over the benefits of the control
scheme. From the Table IV it is evident that the best suitable
bandwidth for claiming significant advantages of current mode
control is 66 kHz. Although the settling time at this frequency
is not significantly less than neighborhood bandwidth, the
components size will be scaled down considerably.
Consequently, the cost of the capacitor will be reduced as well
as requires less current to drive as a network.

(a)

354

TABLE IV
RESPONSE SPEED FOR DIFFERENT BANDWIDTHS
Type of
control
Current
Mode

Voltage
Mode

VI.

Bandwidth
10Khz
20Khz
40Khz
66Khz
10Khz
20Khz

Settling
Time
1.7ms
1.2ms
1.3ms
1.12ms
1.8ms
2.4ms

CONCLUSION

The dynamic performance of the second order converter,

the non inverting buck boost converter, has been studied with
both single loop and multi loop. It has been demonstrated with
simulation results the importance of bandwidth in current
mode control in claiming all the benefits of current mode
control to trade off the complexities such as slope
compensation and measurement of inductor current. Any
bandwidth, based on standard design guidelines, below
switching frequency can maintain system stability as well as
voltage regulation. However, it is not just enough as far as the
complexity of implementing the current mode control scheme
over voltage control mode is concerned. By carefully choosing
the bandwidth, one can make the current mode control
triumph over the voltage mode control.
ACKNOWLEDGMENT
This work was supported by National Institute of
Technology Karnataka, India.
REFERENCES
[1]

[2]

[3]

[4]

[5]

[6]

[7]

Wei Tang, Fred C Lee, Raymond B. Ridley, Small-signal modeling of

average current-mode control, IEEE transaction on power electronics,
vol. 8, no. 2, pp. 112-119, April 1993.
Alejandra R. Oliva, Simon S. Ang, and Gustavo Eduardo Bortolotto,
Digital control of a voltage mode synchronous buck converter, IEEE
transaction on power electronics, vol. 21, no. 1, pp. 157-163, Jan. 2006.
Souvik Chattopadhya and Somshubhra Das, A Digital Current-Mode
Control Technique for DC-DC Converters, IEEE transaction on power
electronics, vol. 21, no. 6 pp. 1718-1726, Nov. 2006.
B. Sahu and G. A. Rincn-Mora, A Low voltage, Dynamic, Non
inverting, Synchronous buck-boost converter for portable Application,
IEEE Transactions on power electronics, vol. 19, no. 2, pp. 443-452,
March 2004.
Jaw-Kuen Shaiu,Chun-Jen Cheng, Design of a non-inverting
synchronous buck-boost DC-DC converter, Elsevier Journal of
Robotics and Computer-Integrated Manufacturing, pp.263267, 2010.
Jong-Ha Park, Hoon Kim, Hee-Jun Kim, A Current mode non-inverting
CMOS buck-boost dc-dc converter, International conference on
telecommunications energy, pp.1-3, Oct. 2009.
H. Dean Venable, Venable Industries, The k factor: a new
mathematical tool for stability analysis and synthesis, reference reading
#4.

355

IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014),May 09-11,2014,Jaipur,India

Hybrid Simulation Method using

MATLAB/SIMULINK and PSPICE for Studying the
Dynamics of the DC-DC Converters with Linear
Controllers
Chandra Shetty, Member,

IEEE

Department of Electrical and Electronics Engineering,

National Institute of Technology Karnataka, India
Email:chandra_shetty84@yahoo.com
Abstract- There are numerous simulation tools for studying
electrical and electronic circuit system dynamics. Most of the
times, we stick to a specific software package for studying the
behavior of a circuit- it depends either on acquaintance with the
software or on accessibility. However, it is good to carefully
evaluate the advantages and shortcomings of each package prior
to selecting one for a given set of objectives. In this paper, it has
been demonstrated how one can combine both the popular
simulation tools MATLAB/SIMULINK and PSPICE to study the
dynamics of the dc-dc converters. The introduced co-simulation
method has advantages like elimination of the laborious process
of development of transfer function of the power stage for
designing the controller, get rid of convergence problem and
truncation of simulation time. The method proposed can be
adapted by beginners who are very new to the designing of
switching regulators for the quick understanding of dynamics of
the converter. Down converter with voltage mode control is used
to verify the proposed method. This can also be extended to
higher order converters, like Cuk and SEPIC, where deriving the
transfer function of a plant is quite tedious process, apart from
above mentioned second order converter. Also, simulation with
idealized models and detailed models has been discussed in the
paper.

Keywords- down converter; higher order converters; TL494;

MATLAB/SIMULINK, PSPICE; SISOTOOL

I.

INTRODUCTION

ne must be very grateful to tremendous advancement

in the computer technology. Had there not been
improvement in the computer aided design, it would
have been very difficult to analyze the electrical and electronic
systems with pencil and paper. Some of the previously
reported work [1]-[5], specifically focusing on power
electronic course, highlight the importance of simulation tools
in electrical engineering.
Designing feedback control for switching power supplies
has always been a challenging task. In [6], feedback controller
design for switching regulators has been elaborated using
specific software package which will guide the students for
learning linear as well as non-linear controllers.
Co-simulation method [7] has been considered for studying
the dynamics of the dc-dc converters. In this paper, it's been a

[978-1-4799-4040-0/14/$31.00 2014 IEEE]

combination of advantages of both MATLAB/SIMULINK

and PSPICE for learning the behavior of the dc-dc converter.
Two step design process is adopted. PSPICE is used to design
the compensator for the required phase margin and bandwidth
and MATLAB/SIMULINK is used for testing the closed loop
dc-dc converter circuit for the desired transient and steady
state response. MATLAB/SIMULINK can be used for
designing linear controllers using SISOTOOL. It requires the
transfer function of the plant. The transfer function of the plant
can be obtained by measurement or analysis, like state-space
averaging technique [8], which is a time consuming practice.
Type 2 error amplifier is considered as a compensator, which
is having two poles and one zero. Because this amplifier has
two poles, for reference this is called as Type 2 error
amplifier. Type 2 error amplifier is referred as "proportional
plus integral controller (PI)".
OrCAD PSPICE has been employed for obtaining
frequency response, which is required for designing linear
compensator, of the power stage by drawing the schematic of
the plant on the schematic page editor of the capture without
the need of transfer function. Once the compensator is
designed, its performance can be simulated using SIMULINK
to study the dynamics of a dc-dc converter. MATLAB is
chosen for simulating the closed loop plant since PSPICE
exhibits the convergence problem and requires more time for
simulation than MATLAB. However, one can eliminate this
convergence problem by using standard design guidelines in
simulation settings. Most of the students who are new to the
PSPICE will not be aware of this stuff. So, an effort has been
made for combing advantages of both software tools to arrive
at a solution for the beginners who try to design the
compensator for a converter.
For higher order converters, it takes considerable amount of
calculation to arrive at the transfer function, which is essential
for applying frequency response analysis. So, the investigated
study could be a great help for the analysis of these types of
converters. Down converter is considered for demonstrating
the proposed method of simulation.
II.

SMALL SIGNAL MODEL

The advantage of frequency domain over time domain is

that we can modify open loop transfer function of a system for
specified closed loop performance without necessity of the
information about closed loop transfer function. The dc-dc
converters are highly non-linear in nature. For applying
frequency response analysis, it requires linearization of the
power stage i.e small signal model of the plant. The linear
model of the power stage can be developed either by state
space averaging technique or using an average model of the
switch [9]. In this paper, frequency response of the power
stage is obtained by using the schematic of the plant in
OrCAD PSPICE [10]-[12] without the requirement of transfer
function, which can be obtained by above mentioned
linearization techniques. The frequency response can also be
obtained by measurement. However, both are extra burden as
far as quick learning of compensator design is concerned.
III.

COMPENSATOR DESIGN USING PSPICE

To design the compensator, PSPICE is considered as a

viable simulation tool in this paper. The first step in stabilizing
a feedback loop is to determine the transfer function of the
plant. We can develop small signal model of the plant as a
transfer function using state space analysis. Once we have
linearized model of the power stage, there are well known
methods from control theory for designing the controller to
ensure stability and dynamic response.
Since PSPICE doesn't require the transfer function for
obtaining the frequency response of the plant, it saves time in
deriving transfer function and calculating compensating
components. Another advantage is we get the actual value of
compensating components with the help of K-factor approach
[13] unlike in MATLAB. In SISOTOOL design we get only
the transfer function of the compensator, not the actual values
of compensating components. The values of resistors and
capacitors are calculated by comparing the obtained
compensator transfer function of compensator from
SISOTOOL to the standard transfer function of the linear
controllers like P, PI or PID.
The down converter is considered as a design example. The
converter specifications are as follows: Vin=lOV, Vout= 5V,
Switching
frequency=1OOKHz,
phase
margin=45,
bandwidth=lOKHz, Rc=O.5Q, R1=O.IQ, C=100uF, L=100uH
and load resistance is 5Q. The Pspice schematic for obtaining
the frequency response is shown in fig. 1

100uH
10Vac
OVdc

0.1

0.5

Fig. I. Pspice Schematic used to detennine frequency response.

""0

C2

R2

oW.-+---Vc

Fig. 2. Schematic diagram of type II amplifier.

The simulation result of the PSPICE is combined with the

K-factor approach standard design guidelines to arrive at the
transfer function of the compensator. This transfer function
will be used in SIMULINK for the simulation of the closed
loop plant. The transfer function of the type 2 error amplifier
is given by equation (1).

G(S)

(1)

From the simulation result, the gain at 10Khz is -2.24dB

"
and the phase angle is -lOt . The PWM converter has a gain 9.54dB. The total gain of the power stage and PWM converter
is -11.78dB. Based on the above data and equations (2) to (6),
the value of compensated elements are:Rl=lkQ (chosen
value), R2=4.284kQ, Cl=12.26nf, C2=1.24nf. Fig. 4 shows
the schematic for verifying the desired phase margin and
bandwidth after obtaining the values of compensating
elements.

Boost
K

- P - 90

(2)

Tan[(Boost/2) + 45]

C2

1/ (2nfGR J )

CJ

C2 (K

R2

100uf
Vin

From the frequency response, as shown in the fig. 3, it is

apparent that type 2 error amplifier, shown in the fig. 2, is
enough to get the desired phase boost.

(3)
(4)

- 1)

(5)

K/(2nfC1)

(6)

Upon the substitution of compensated component values in

equation (1), the resulting transfer function of the compensator
is given by equation (7).

G(s)

8 X 105 s + l.9 xl04

s s + 1.88 x 105

(7)

 O '--------'---------r--------r---------r-------,r------- -,--------,--------,
:
:
,
----------- -:-- - - - - - - - --- - -- -- -- - - - - - - - - - --- -- -- -- - - - - - - - - - --- -t -- -- -- - - - - - - - - - - -- -- -- -- -t- -------------

M
a

f-___ -____ ____

g
i
t

--

J:

---- -- ==lI-=-=".- +-----+------------r --(lZUen: 5-'Z:'2"'8"')

-----------_________ ________________ ____________ _____________ ___________ .i ___________ _ _l _____________
:
r___
-----------,------------- ------------ ------------- ------------t------------------------r-------
------------ - ----------- ------------ ------------- ------------t -- ----------- ------------ - ------------

__________-___ __---__ _ _-_- _

--____
- - -------------

rl

----

-----

__

40

-L
.... - -- -- - -- .,---- -- -- -- ---- -- - -- -- +------

------

------

------

@]DB(V(R3:2) )

------

--------

------

------

Od,------,---- --==== ----------------------_.

?
h
a
5

___________J _____________ ____________

----------- ------ ------ ------- ----

- 1 00d

-----+------

. . :p(...I=,-o, . i;;j; -. .:. . .

-----+------

--;
====
,
,
___________ _________ __ _ __ __ __ ______ ____ __ __ __ __ _ _ __________ __ __ __ _______ ___________ _____________
,,
,,
----------- ,------------- ------- - ---- ------------- ----- - ----- - , -,
,, ----------------------+------------ ------------ ------------- ------------r------------- -----------+------------oJ.

.1.

,..

.L.

-- -- - - - -- --

- -- -- -- -- -- -r- -

-200d 4-----------L---_+--

EL

100Hz

[:! P (V (R3: 2)

10Hz

1. OKBz

1 0KH z

Fig. 3. Uncompensated open loop frequency response.

r-----i

R4

11L 1

00.1

100utI-J

10Vac

100KHz

F-requency

100u
0_5

C1

R1

[N\+OUT+

11'<

OlJT-

IN--<-, %l1N-)f,(3)
EVAUJE

124nf

R2

1=1
1Nl-

C2

Fig. 4. Pspice schematic to test open loop frequency response with compensation.

100

t==+---=----f-----------I

------------ -------------- ------------ -------------------------+-------------------------------- -------------------------- ------------7--------------

------------t---------------------------r------------ -------__+-CUi -1:"'9"817;--------------

J:..
u

--------------------------------------------------- -------------------------- ------..:.::..----

F\ 1

------------r---------------------------r------------ ------------1-------------- ------------r--------------

SEL:.-:>
-I nn
1 0:\
h
a

SOj

------------t---------------------------r------------ ------------1-------------- ------------t-------------f--------4---=-=--=--- -=--

:::::::::::: ::::::::::::::::::::::::::: =:::::::::

OJ
lOB;::
.;. ?lV(EZ;J

Fig. 5. Frequency response with compensation

100Ez

;,

o::: :;

------------ -------------- -------------lo--------------

::::::: :::::: : :

1.0ITJ1z
'E L t:: U UtlH,; V

10P"Jiz

::::::::::::::

100KHz

CLOSED LOOP PLANT SIMULATION USING

MATLAB

IV.

PSPICE employs nodal analysis method for circuit

simulation. A sudden discontinuity in PSPICE can result in the
program proceeding with extremely small steps and result in a
problem of convergence. Eventually, simulation would stop
with an error message. There are few definite rules to avoid
the solution from failing to converge. However, the proper
simulation settings to avoid convergence during simulation
require experience, which the most students don't possess, in
using PSPICE.

9-r:.:

ICom51
powe:rgui

So, MATLAB is adapted for simulation of closed loop plant.

Moreover, it takes lesser time than the PSPICE to execute the
project. The designed transfer function in PSPICE , given by
equation (7), is realized with the help of the LTI system block
which has been furnished in control system toolbox. The
PWM generation is simulated with the help of relational
operator tool box, as shown in fig. 6. The simulink block
diagram of the plant and the output voltage are shown in fig. 7
and 8 respectively. This simulation take considerably takes
less time than other two simulation methods, which are
discussed in next section. This is an added advantage apart
from having elimination of convergence problem.

Itl C un -en t

Mea """f;::em:;:e=n=t ::::;:=

"B

____
_

MmM'
I
Seoj)+J

-=L

.)J

r-. [
-.L

Diode

L-------1 eM

Voltage

1 14---te5 1 5\.I l 1.B oj+-----{

Oofll)A'nl,u:r

Fig.6. Simulink block diagram of the closed loop plant.

V.
Repeating
Sequence
Fig. 7. PWM Generator block.
l() r--------r----,

SMULATION WITH IDEALIZED CIRCUIT

MODEL IN PSPICE

For comparison purpose, the same converter has also been

considered for simulation using PSPICE. This section is
dedicated for studying the distinction between two simulation
tools in executing a closed loop dc-dc converter. There are
significant differences between the simulation output obtained
from MATLAB and PSPICE as far as steady state and transient
response is considered. The circuit diagram is shown in fig. 9.
Ll

Vin

10V

.,

1'D1

Lbreak
l00uH

'-

OrrPAGC CrT-2

D2
Ubreak

OFFPAGELEFT-1
.

0.1
Cbreak
100u
Cl
R23
0.5

Fig. 8. Output voltage of closed loop plant in MA TLAB/SIMULINK.

(a )

R2
5

Freq= lOOk
Vp=3,

:<

OFF P AG E LEFT-4

Although most of the times we simulate the electrical and

electronic circuits using idealized circuit models, simulation
using hardware chip model has certain advantages, it includes
the assistance in hardware implementation of the converter.
TL494 PWM [14] chip is considered for simulation. The output
voltage is shown in the fig. 11.

OFFPAGELEFT-3

<
O FFPAGELE FT 2

SIMULATION WITH DETAILED MODEL IN

PSPICE

VI.

El

<

p,

Vl=O
V2= {Vp)
TD = O
TR.= {(lJF ... q)-2n}
TF=ln
T=ln
PElt = {lJ(Freq))

Since the PWM chip model takes into consideration various

parameters, it requires considerable CPU time for calculation.
Although it takes considerably more time than the simulation
with idealized circuit models, this simulation with actual chip
model assist in hardware implementation. As mentioned
earlier, here also definite rules are considered to avoid the
solution from failing to converge.

C7
1_24n
C6

5. cv

O fF P AGELEFT- 1

R17
OF FBAGElE .FT -3
----------------
"
Off PAGEl EfT-4
1k
v.

Fig. 9. Schematic of closed loop plant in PSPICE with idealized circuit models:
(a) power stage and (b) PWM stage.

With the idealized circuit models, like ideal switches, the

simulation time is significantly less than the simulation with
detailed PWM chip model, which is discussed in next section.
The simulation with idealized models gives approximate
results since it considers fewer parameters. However, it is
useful for a quick, rough estimate of circuit performance. The
simulation output is shown in fig. lO. Proper design guidelines
have been adopted in the simulation settings to deal with
convergence problem.
:
:--'-: ---,--': --': -'--'
:
--'
:
l C V ,--,:--,:--,: --,: -,,-'--'

! !
PI! iT i i i.. i i Ij i.

SV

--- --:L----;---- -----;-.-.-------- - - ;:-- -- ---;-:.-..----

. ._____
______
-----l------t-----+-----t----- l f l
f + t +
-----1------t-----+-----t----- . -----1----- .-. -1------ --- ------. ----+----t--. -. + ----- ----- ---- ----------- ------ ----

cv

j i j i

j i j
-

--

---- ----

i j i j

----

---

----- ----- - ---- ------ ---- ----- ----- --- ----------- ------ ---- ----- --- ----

Os
o

1.Oms
V ( OFFPAGELEFr- l )

Time

2 . 0ms

Fig. 10. Output voltage with idealized circuit model.

---- ------------ ---

----

cv--------+_--
2.0ms
3.Jms

(b)

--------- ---------

.1:::::;== =FTiIF
I] I i :11

4284k 12.26n

::::: :::::: ::::: :::::: :::::

tl j

--+--.-.-----------.-.-.-. i
+
.- _ir.___ :___'!--------- -+--.-.----_f-----.'-.. .----!-----------+-:+---.-

R1 8

3.0m3

Time

Fig. I I. Output voltage with detailed PWM (using TL494) model.

VII.

CONCLUSION

Co-simulation method has been introduced for studying the

dynamics of the dc-dc converters with linear controller. The
paper has elaborated the advantages of co-simulation method.
It includes tackling the problem of convergence, elimination
of the necessity of transfer function of the plant for controller
design and reduction in simulation time. Although it can't be
claimed as a most efficient method, it can be adopted by
beginners who are having a little acquaintance in both
MATLAB/SIMULINK and PSPICE. However, advanced
learners can also employ this proposed method for higher
order converters with some extra effort.
The importance of simulation with idealized models and
detailed is also dealt in the discussion. If we observe three
different simulated outputs, each one has different steady state
and transient characteristics. Computer simulation should not
be looked upon as a substitute for a hardware prototype. On
the other hand, simulated result would be a great help while
implementing the hardware prototype, which saves time as
well cost of the project.
ACKNOWLEDGMENT
This work was supported
Technology Karnataka, India.

by National Institute of

REFERENCES
[I]

Snejana D Terzieva, Simeon S. Vladov, Valeri M. Mladenov, "Course

project in theoretical foundations of electrical engineering-clear and easy
with PSPICE and MATLAB",IEEE EUROCON, pp.764-767,2005.

[2]

Daniel W Hart,"Circuit simulation as an aid in teaching the principles

of power Electronics", IEEE Transactions on Education, Vo1.36,
no.!,pp. 10-16,1993.

[3]

[4]

Alexander Abramovitz, " Teaching behavioral modeling and simulation

technique for power electronics courses", IEEE Transaction on
Education, vol. 54, no.4, pp.523-530,20II.
A.B. Raju and S.R. Karnik, "SEQUEL: A free circuit simulation
software as an aid in teaching the principles of power electronics to
undergraduate students",ICETET-09,Nagpur, India, pp.68 1-686, 2005.

[5] Ibrahim Chamas, Mahmoud A EI Nokali , "Automated PSpice

simulation as an effective design tool in teaching power electronics",
IEEE Transactions on Education,Vol. 47,no.3,pp.415-421,2004.
[6]

Juing-huei, Jiann-Jong Chen and Dong-Shuiuh Wu, "Learning feedback

controller design of switching converters via MATLAB/SIMULlNK",
IEEE Transaction on Education, vo1.45, no.4, pp.307-315, 2002.

[7]

Jiwei Sun, Hailong You, Zhiyun Li, Xinzhang Jia ailing, "Research on
modeling control module of dc-dc converter for simulink", Second
international conference on power electronics and intelligent
transportation system (IEEE), pp. 139-142,2009.

[8]

R.D.Middlebrook and S. Cuck, "A General unified approach to

modeling switching converter power stages" IEEE Power Electronics
specialist conference record,pp.18-34,1976.

[9]

V. Vorperian, "Simplified analysis of PWM converters using model of

PWM switch. PartI: continuous conduction mode", IEEE transaction on
aerospace and electronic systems,pp.490-496,1990.

[10] "Pspice User's Guide",2nd edition, Cadence Design System,2000.

[II] DanieI.W.Hart, "Power Electronics",Tata Mcgraw Hill,2011.
[12] Chandra Shetty, Anil Kadle, A.B.Raju, "A simplified approach to the
first order approximations of a closed loop, non isolated dc-dc converter
with synchronous rectifier circuit behavior by using the Orcad Pspice",
Fourth international conference on advances in power electronics and
instrumentation engineering,unpublished data.
[13] H. Dean Venable, Venable Industries, "The k factor: a new
mathematical tool for stability analysis and synthesis", reference reading
#4.
[14] Chandra Shetty, Anil Kadle, A.B.Raju, "A detailed application of
TL494 Pspice model in designing switching regulators: an educational
approach", International conference on advances in recent technologies
in electrical and electronics,unpublished data.

IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

A Quick and Simplified Approach for

Understanding the Dynamics of the SEPIC
Converter for Low Voltage Applications:
Simulation Study
Chandra Shetty, Member, IEEE
Department of Electrical & Electronics Engineering
National Institute of Technology Karnataka, Surathkal, India
chandra shetty84@yahoo.com

AbstractDesigning the feedback compensator for the SEPIC

(single ended primary inductance converter) converter is quite
difficult due to the extreme amount of phase shift in the power
stage and occurrence of double resonance. Hence the current
mode control, which increases the complexity of the system, is the
most commonly adapted for stabilizing the converter. However,
the careful observation of the frequency response of power stage,
which depends on the filter components and equivalent series
resistance of the capacitor, of the power stage makes the process
of controlling the dynamics of the converter easy. Sometimes the
frequency response of the power stage of the converter is free
of double resonance with minimum phase shift and resembles
the second order converter. So, one can develop the compensator
network similar to the second order converter. In this paper, the
design of controller for the SEPIC converter based on single loop
feedback control is presented without the need of current mode
control and its associated complexity. The presented analysis
does not require the complicated methods such as the principal
component analysis and the model order reduction but it is as
simple as observing the bode plot of the power stage of the
converter. The entire simulation is carried out in Pspice.
Index TermsFourth order converters, k-factor approach,
small signal model, SEPIC converter, voltage mode control.

I. I NTRODUCTION
Fourth order converters are preferred by power electronics
engineers over second order converters due to their high
performance. As the SEPIC converter consists of four energy
storage elements, it is labeled as fourth order converter. The
SEPIC converter is shown in Fig. 1(a) [1]. It is assumed that
the converter operates in continuous conduction mode (CCM).
The Fig. 1(b) shows the circuit status when the switch is
on and Fig. 1(c) shows SEPIC converter when the switch
is off. When the switch is turned on, the inductor, L1, is
charged from the input voltage source. The second inductor
takes energy from the first capacitor and the output capacitor is
left to provide the load current. When the switch is turned off,
the first inductor charges the capacitor C1 and also provides
current to the load. The second inductor is also connected to
the load during this time.
It has always been believed that the stabilization of fourth
order converter is a tedious process due to the large amount of

phase shift in the power stage and the voltage mode control
cannot be adapted. Since the current mode control reduces
the order of the power stage by eliminating the effect of
inductance, it is the usual method employed to control the
fourth order converters. However, the current mode control
brings on other complexities. So, the voltage mode control
is the most preferred method due to its simplicity. Since
the power stage of the fourth order converter entails four
energy storage elements, there will be a large amount of
phase shift which makes the voltage mode control unfavorable
for controlling the fourth order converter and hence either
the model reduction method [2] or the principal component
analysis [3] can be employed for adapting the voltage mode
control in controlling the fourth order converters. Both the
method involves complex theory and a lot of mathematics.
This paper deals with the fact how one can employ the voltage
mode control by carefully observing the frequency response
of power stage for low voltage applications.
Some applications, such as portable devices, require low
voltages. Since the size of power stage components is the
function of load voltage, its dimensions will be reduced
considerably. Therefore, phase shift in the power stage will
be truncated. Consequently, the voltage mode control can be
adapted for shaping the dynamics of the converter.
II. M ETHODOLOGY
For understanding the dynamics of a converter, it is common to adapt frequency domain approach. So, the frequency
response of the converter is necessary. To get the frequency
response, it is essential to have the linear model of the power
stage, since it is inherently non linear, of the converter. After
obtaining the small signal model of the converter through
any of the existing standard methods, frequency response is
plotted. In this paper, bode plot of the converter is obtained
by AC Sweep analysis of the Pspice simulation tool. Once the
plot is available, the feedback components are calculated using
k-factor approach based on gain and phase shift. Eventually,
entire converter simulation for transient response will be

IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

TABLE I
SEPIC C ONVERTER S PECIFICATIONS
Parameter

Value

Input Voltage

2.7 V

C1

3.3 V

ESR of C1

Output Voltage
Switching Frequency

5 H

L1
ESR of L1

0.0038
5 H

L2
ESR of L2

(a)

300 kHz

0.109

Parameter

Value
10 F
0.382

C2

141 F

ESR of C2

0.003

Load Resistance

100

Bandwidth

10 kHz

Phase Margin

60 degree

works approximately as an ideal diode [1] with emission

coefficient n = 0.001. The default value of emission coefficient
in the vendor model is n = 1.
III. AC M ODEL OF THE SEPIC C ONVERTER

(b)

The small signal model of the PWM dc-dc converters can be

developed with the aid of different modeling techniques, such
as state space averaging, circuit averaging, current injected approach, averaged switch modeling, etc. State-space averaging
is quite useful for developing the transfer functions of dcdc converters and involves the manipulation of equations. In
circuit averaging technique the converter equivalent circuit is
obtained by averaging the converter waveforms. The converter
model can also be obtained by replacing the switches by its
averaged model. In this paper the AC model of the converter
is obtained by replacing the switch network with its average
model [7]. The average model can be found in Pspice library
of averaged models. The library of these models can be
downloaded from the website. The model script is repeated
here.
.subckt CCM1 1 2 3 4 5
Et 1 2 value={(1-v(5))*v(3,4)/v(5)}
Gd 4 3 value={(1-v(5))*i(Et)/v(5)}
.ends

(c)
Fig. 1. (a) SEPIC Circuit; (b) Circuit with the switch closed and the diode
off; (c) Circuit with the switch open and the diode on.

carried in Pspice. The proposed approach is valid only if the

phase shift due to filter components of the power stage is less
than 180 degree. However, as the converter for low voltage
application is considered, the phase shift would be, most of
the times, is less than 180 degree.
For the simulation, the swiches of the converter are implimented using Sbreak Switch model [4][6]. The PWM
signals are obtained by TL494 Pspice Model. The Pspice
model of this chip is available in controller.olb. For the
capacitor and the inductor, we can use PSPICE model from
PSPICE library breakout.olb. Dbreak, Pspice model of the
diode, is employed for transferring the energy to output which

These can be employed in spice model editor to obtain

the capture of the averaged model. This is valid for a dc-dc
converter operating in continuous conduction mode. The small
signal model of power stage can be with respect to change
in duty ratio or with respect to change in line voltage [8].
Here the average model of the power stage is considered with
respect to variation in the duty cycle.
The Table I show the specifications of the converter and
the Fig. 2 shows the small signal model of the power stage
which is employed for determining the frequency response
using computer simulation, Pspice. The bode plot of the power
stage is shown in the Fig. 3. The phase shift in the power stage
is -176 degree and the gain is 7.216 dB at the phase cross over
frequency of 10 kHz.
IV. C OMPENSATOR N ETWORK
For compensating the converter, type III compensator is
used as shown in the Fig. 4 with compensator component

IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

Fig. 2. Small signal model of the SEPIC converter.

values. Type III error amplifier is commonly referred as

PID (proportional plus integral plus derivative) controller in
technical literature. The type III compensation is adapted when
the phase boost required is more than 90 degree and less than
180 degree. The phase margin indicates the relative stability
of the system. The more phase margin is selected, the more
stability is assured. However, one cannot go for high phase
margin which would result in increased settling time. As a
compromise between stability and good transient response,
a phase margin of 60 degree is chosen. The compensator
components are calculated with the aid of k-factor approach
[9] at the bandwidth of 10kHz. The compensating components
are calculated using the equations as shown below. These
equations repeated here from the k-factor approach.

Boost = M P 90

(1)
0

K = (tan[(Boost/4) + 45 ])
1
C2 =
2f GR1
C1 = C2 (k 1)

k
R2 =
2f C1
R1
R3 =
(k 1)
1

C3 =
2f kR3

G = Amplifier gain at cross-over frequency

M = Desired Phase Margin (degrees)
P = Modulator Phase Shift (degrees)

(2)
(3)
(4)
(5)
(6)
(7)

V. R ESULT AND D ISCUSSION

The output voltage is shown in the Fig. 5. The output
voltage reaches steady state voltage of 3.3V after the transient
period dies out. The settling time is around 10.517ms. Here
settling time is quite long since the converter is not optimized
for bandwidth. The bandwidth depends on the amount of
phase shift in the power stage which in turn depends on the
value of passive components. The converter bandwidth can be
improved with a little more work.
VI. C ONCLUSION
The controller design for the fourth order SEPIC converter
using the voltage mode control is discussed. It is observed that
the sensible evaluation of the bode plot of the power stage of
the converter would ease the process of stabilization. Since the
control to output frequency response of the converter approximate to the second order converter, type III compensation is
applied to control the dynamics of the converter. For the given
specifications of the converter, the frequency response of the
converter is free of double resonance. Accordingly, it requires
neither the principal components analysis nor the model order
reduction method for stabilizing the converter. In actual fact,
sometimes its the passive components that determine the type
of controller which can be applied to govern the dynamics of
the converter.
The process, quick and simple, described in the methodology section can be applied to a SEPIC converter only when
the total phase shift in the power stage of the converter is
less than 180 degree. In contrast, the current mode is the
only alternative if the phase shift is more than 180 degree.
Another disadvantage of this method is one cannot go for high
band width to have improvement over transient response since
designer has to restrict to a bandwidth frequency where phase

IEEE Sponsored 2nd International Conference on Innovations in Information,Embedded and Communication systems (ICIIECS)2015

Fig. 3. Frequency response of the control to output transfer function.

R EFERENCES

Fig. 4. Type III error amplifier..

Fig. 5. Transient response of the converter.

shift is less than 180 degree. For the improvement in transient

response, it is necessary to reduce the order of the converter by
measuring the current of the inductor, current mode control,
and selecting a higher bandwidth, which is not possible in the
above discussed method.

[1] D. W. Hart, Power electronics. Tata McGraw-Hill Education, 2011.

[2] B. K. Kushwaha and A. Narain, Controller design for cuk converter
using model order reduction, in Power, Control and Embedded Systems
(ICPCES), 2012 2nd International Conference on. IEEE, 2012, pp. 15.
[3] A. De Nardo, N. Femia, M. Nicolo, G. Petrone, and G. Spagnuolo, Power
stage design of fourth-order dcdc converters by means of principal
components analysis, Power Electronics, IEEE Transactions on, vol. 23,
no. 6, pp. 28672877, 2008.
[4] M. H. Rashid, Spice for Electronics Using PSpice. Prentice Hall PTR,
1990.
[5] C. Shetty, A. Kadle, and A. Raju, A simplified approach to the first
order approximations of a closed loop, non isolated dc-dc converter with
synchronous rectifier circuit behavior by using the orcad pspice, 2013.
[6] Pspice Users Guide. Cadence Design System., 2000.
[7] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics.
Springer Science & Business Media, 2001.
[8] B. Sahu and G. A. Rincon-Mora, A low voltage, dynamic, noninverting, synchronous buck-boost converter for portable applications, Power
Electronics, IEEE Transactions on, vol. 19, no. 2, pp. 443452, 2004.
[9] H. D. Venable, The k factor: A new mathematical tool for stability
analysis and synthesis, in Proc. Powercon, vol. 10. Citeseer, 1983, pp.
H11.