An Investigation Of

Injection-Locked Frequency
Dividers

A report submitted in partial fulfillment

of the requirement for the degree of
Bachelor Of Engineering

David ONeill
March 2005

University College Cork

Department of Microelectronic
Engineering

Declaration
I hereby declare that, except where otherwise indicated, this document is entirely
my own work and has not been submitted in whole or in part to any other university.
Signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date

.............................

ii

Abstract
Injection of a periodic signal into an oscillator leads to interesting locking or
pulling phenomena. These effects investigated in the past by Adler [1] and others,
have found increasing importance in todays phase-locked loops. Recently phaselocked loops have moved toward higher and higher speeds. As this frequency of
operation has increased power consumption in the frequency divider has increased
due to the methods of division used.
Injection-locked frequency dividers (ILFD) offer a low power consumption alternative to the traditional methods of frequency division. However as these methods
have become more widely used, numerous papers have proposed contradictory models for quantifying the input locking range of the ILFD.
In this report we will seek to investigate ILFDs by modeling an ILFD and verifying the results experimentally.

iii

Acknowledgements
Firstly Id sincerely like to thank Professor Kennedy for his encouragement
and advice thought the year on the work involved in the project. Id also like
to thank David Bourke for being willing to work the long hours with me to get this
project completed. Special thanks must go to the postgraduates especially Keith
ODonoghue who was always available to help as much as he could with any queries
we had.
Thanks to Zhipeng Ye for his input toward writing the ECCTD 2005 paper.
Thanks to Gerard Hooton for all the technical support throughout the year and a
final word of thanks to Niamh OSullivan for always being extremely helpful toward
us.

iv

Contents

Abstract

ii

Acknowledgements

iii

Contents

iv

List of Figures

vii

List of Tables

1 Introduction & Objectives

1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3

Background To Project . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4

Structure Of Report . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Constructing An ILFD
2.1

2.2

LC-VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2

Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3

Simulation & Implementation . . . . . . . . . . . . . . . . . .

ILFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1

ILFD Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 12

Contents
2.2.2

v
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Testing And Modeling an ILFD

3.1

3.2

Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1

Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2

Agilent VEE Setup . . . . . . . . . . . . . . . . . . . . . . . . 18

Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1

Existing Models . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2

Parametric Model of an ILFD . . . . . . . . . . . . . . . . . . 20

3.2.3

Extraction of Model Parameters . . . . . . . . . . . . . . . . . 22

3.2.4

Implementation in MATLAB . . . . . . . . . . . . . . . . . . 24

4 Results
4.1

4.2

17

26

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.2

Devils Staircases . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.3

Parameters which affect locking range . . . . . . . . . . . . . . 31

Model Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.2

Visual Comparison of Outputs . . . . . . . . . . . . . . . . . . 33

4.2.3

Comparing Modeled Results to Experiment . . . . . . . . . . 34

5 Conclusions & Future Work

38

5.1

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.2

Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Bibliography

40

Contents
Appendices

vi
42

MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Photographs of Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Accurate Modeling and Experimental Validation of an Injection-Locked

Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

The Devils Staircase As A Method of Comparing Injection-Locked

Frequency Divider Topologies . . . . . . . . . . . . . . . . . . . . . . 50

vii

List of Figures

2.1

Real VCO. IIN is a current impulse, C is a capacitance, L is an

inductor and R represents the losses inherent in the circuit . . . . . .

VCO with negative resistance (R) added to overcome positive resistance R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Oscillator Model: (a) Representation of Oscillator with NR representing the active components of the circuit. (b) Desired IV Characteristic
of NR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chosen LC-VCO Topolgy. Cross-Coupled Inverters M1 to M4 , generate the negative resistance needed to overcome the losses in the LC
tank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Alternative LC-VCO Topolgy. Consists of only NMOS Transistors.

Note that inductance L is created by using two inductors of inductance L2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6

PSpice Driving Point Characteristic . . . . . . . . . . . . . . . . . . .

2.7

Comparison between the PSpice Driving Point Characteristics. Solid

Line: Original Characteristic. Dashed Line: Increased W
Ratio CharL
acteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8

Experimental Extraction of Driving Point Characteristic: (a) Circuit

Used. (b) Difference Op-Amp used to capture small voltage drop
across resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.9

Example Driving Point Characteristic from Tektronix TDS5054 Oscilliscope. Channel 1: X-Axis 2V/Div. Channel 2: Y-Axis 2mA/Div . 12

2.2

2.3

2.4

2.5

2.10 Injection Locked Frequency Divider Topology . . . . . . . . . . . . . 13

2.11 Direct Injection Based Injection-Locked Oscillator Topology . . . . . 14

List of Figures

viii

2.12 Injection Locked Divider Topology with load balancing for Input VCO 16
3.1

Experimental Setup for Automated Measurement of Locking Range . 18

3.2

Complete Agilent VEE Interface . . . . . . . . . . . . . . . . . . . . . 18

3.3

Agilent VEE Interface for selecting voltage and frequency sweep.

Voltage to be swept from 0.25V to 6V with a step-size of 0.25V.
Frequency is swept from 1 kHz to 10 MHz with a step-size of 1 kHz . 19

3.4

Example Staircase Structure created from Agilent results . . . . . . . 20

3.5

Injection Locked Frequency Divider Model. NR represents the active

components in the circuit . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6

Driving Point Characteristics for Various Bias Voltages . . . . . . . . 23

3.7

Plot of the a Co-efficients with a Quadratic Fit. dVdaGS indicates slope

around bias point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.8

Finding the Locking Range: (a) Injected Signal Outside Locking

Range. (b) Injected Signal Inside Locking Range . . . . . . . . . . . . 25

4.1

Locking behaviour for the classical injection locked oscillator topology.

Locking is characterised by a flat region on the plot. Note that the
widths of the locking regions increase with VIN J . . . . . . . . . . . . 27

4.2

Devils Staircase with VIN J = 3V. Note the steps at fd =

4.3

J
Portion of Staircase highlighted in Fig. 4.2. Note the steps at fIN
=
fd
2 fIN J
1 fIN J
2
, fd = 2 , fd = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5

4.4

Locking behaviour for the direct injection locked oscillator topology . 29

4.5

Devils Staircase with VIN J = 3V. Note the steps at fd =

4.6

Portion of Staircase highlighted in Fig. 4.5. Note the step at

4.7

Comparison between Simuation and Experiment . . . . . . . . . . . . 33

4.8

Comparison between locked and unlocked oscillation on both the

scope and in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.9

Driving Point Characteristics: Solid: Experiemental; Dotted: Cubic

Fit To Experiment; Dashed: PSpice . . . . . . . . . . . . . . . . . . . 37

fIN J fIN J fIN J

, 4 , 6
2

27

fIN J fIN J fIN J

, 4 , 6
2

30

fIN J
fd

30

8
3

List of Figures

ix

5.1

Adjustment of Input Frequency by varying VCO capacitance. Notice

the division of the frequency by two that can be seen on the frequency
counters near the top of the picture. i.e. 1.7435 MHz X 2 = 3.487 MHz 43

5.2

Breadboard containing both VCO and ILFD . . . . . . . . . . . . . . 44

List of Tables

4.1

Comparison of input locking ranges with VIN J = 1 Vpp . . . . . . . . 28

4.2

Comparison of input locking ranges with VIN J = 3 Vpp . . . . . . . . 29

4.3

Comparison of input locking ranges with various input amplitudes . . 31

4.4

Comparison of input locking ranges with various inductor sizes . . . . 32

4.5

Comparison of input locking ranges with various bias voltages . . . . 32

4.6

Comparison of Experimental Data to Lees Predictions. VIN J = 2.5

Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.7

Comparison of Experimental Data to Lees Predictions. VIN J = 6.5

Vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.8

Locking Range Versus Injection Amplitude f0 = 1.568 MHz . . . . . 36

4.9

Locking Range Versus Inductor Size . . . . . . . . . . . . . . . . . . . 36

4.10 Locking Range Versus Bias Voltage . . . . . . . . . . . . . . . . . . . 36

5.1

MOSFET SPICE Parameters taken from [10] . . . . . . . . . . . . . 42

Chapter 1

Introduction & Objectives

1.1

Introduction

In general, oscillatory systems are prone to injection locking or pushing/pulling.

This has been observed in all types of oscillatory systems and as early as the 17th
century, the Dutch scientist Christiaan Huygens observed that the pendulums of two
clocks on the wall moved in unison if the clocks were hung close to each other [2].
Huygens suggested that through coupling of mechanical vibrations through the wall
the clocks were hung on, drove the clocks into synchronization.
In electronic circuits injection locking can be utilized in a number of applications.
The application that we will focus on in this report is frequency division [3]. This can
be explained through a more detailed explanation of injection-locking. The principle
is that, when a free-running oscillator is injected with an external signal that is
within a certain range (locking range) around the first harmonic of the oscillators
natural frequency, the oscillators frequency changes to become equal to that of the
frequency of the injected signal. Also, the oscillator will lock to multiples of its
natural frequency and hence it is capable of performing frequency division.

1.2

Objectives

The basic aims of this project can be summarized as follows:

Research was to be conducted on previously published material concerning the
topic of injection-locking. As neither myself nor David Bourke were familiar
with oscillator theory this area was also to be researched.
A discrete circuit implementation of an injection-locked frequency divider
(ILFD) was to be built. The injection signal for the ILFD was to be pro-

1.3 Background To Project

vided by a voltage controller oscillator (VCO), using the same topology as the
divider.
An automated method of testing the locking range of the divider was to be
devised and implemented.
The operation of the ILFD was to be modeled. The existing models were to
be compared to our experimental results and if they were not valid for the
observed results a new model would have to be devised to accurately predict
the observed results.

1.3

Background To Project

RF phase-locked loops are widely used in applications such as frequency synthesizers [4]. The frequency divider is one of the key components in a phase-locked loop
(PLL) and its power consumption is one of the primary concerns when designing a
PLL. Frequency dividers are commonly realized using common-mode logic (CML) [5]
or through the use of a Miller divider [6]. While both of these methods have been
realized at very high frequencies [7], the power consumption is very high. Injectionlocked frequency dividers offer a low power consumption alternative to both Miller
and CML division at high frequencies.
One of the drawbacks to the use of injection-locking as a method of frequency
division is that there is a limited input bandwidth (locking range) over which frequency division occurs. However, this is not very relevant with their use in LC-VCO
based PLLs as the LC-VCO itself has a limited tuning range.
As outlined in Section 1.2 the main objective of this project was to investigate injection-locking and attempt to match our experimental results to an existing
model.
The main contradiction in the existing models for the input locking range is that
it has been stated as being both proportional [8] and inversely proportional [9] to
the size of the inductor present in the divider.
In [9], the locking range is presented as the following, where Iin is the injected
current, Itail , the current in the tail of the VCO, RS the series resistance of the
inductor and L the inductor size:

1.4 Structure Of Report

Iin Rs
Itail 0 L

(1.1)

However the theory in [8] presents the following expression for the locking range of
an injection-locked divider.

 

   H0 a2 Vin 

 

(1.2)
 0  =  2Q 
By equating H0 to Q2 Rs , Eq. (1.2) can be reduced to
2 = 2 La2 Vin ,
where a2 is the second-order coefficient of the nonlinearity. This leads to the conclusion that larger locking ranges can be achieved by increasing the size of L and
has been mentioned previously this is clearly contradictory to what is presented in
Eq. (1.1).
This paper will attempt to resolve this conflict.

1.4

Structure Of Report

This report will begin, in Chapter 2, by discussing the process involved in designing and implementing the oscillator which formed the basis of the ILFD. Following
this the process involved in modifying this oscillator to operate as a frequency divider
will be outlined.
With the oscillator constructed Chapter 3 will discuss the process of testing and
modeling the oscillator. Chapter 4 will include the results of the project which
Chapter 5 will attempt to draw conclusions from these results and outline future
work that could be done in the area.

Chapter 2

Constructing An ILFD
This chapter outlines the steps involved in the implementation of an ILFD. It
was decided to implement an ILFD as opposed to performing SPICE simulations as
analysing injection-locking in SPICE is an extremely time consuming process. The
creation of an ILFD first requires the design on a VCO which is then modified to
act as an ILFD. These processes will now be described.

2.1
2.1.1

LC-VCO
Introduction

In [10], Buckley outlines a design methodology for CMOS oscillators. Buckley

describes in detail multiple CMOS oscillator topologies. Having examined the various topologies available and having discussed it with Professor Kennedy, it was
decided to choose a cross-coupled CMOS LC Oscillator biased with a tail current
source. This is not explicitly outlined in [10] but a similar topology without a tail
current source is detailed so it was easy to transfer the theory from one to another.
In this area of the project my work was mainly centered around theory and
simulation of the circuit in PSpice, while David Bourke was concerned with the
implementation of the VCO on the breadboard. Davids report outlines in far more
detail the process of implementation and the associated problems. Therefore the
reader is referred to it for queries regarding the implementation as this report will
mainly deal with the design aspects of the VCO.

2.1.2

Theory

A simple electronic oscillator produces a periodic voltage output. An ideal oscillator could simply consist of a capacitor and inductor but in reality there will

2.1 LC-VCO

be losses associated with the components so a more realistic representation of an

oscillatory circuit is shown in Figure 2.1.
VOU T

C
IIN

Figure 2.1: Real VCO. IIN is a current impulse, C is a capacitance, L is

an inductor and R represents the losses inherent in the circuit.
When the tank circuit (Figure 2.1) is stimulated by a current impulse, the tank
responds with a decaying oscillatory behaviour. The oscillation decays due to the
fact that in every cycle, energy is lost in the resistor R. Now if it were possible to
overcome this positive resistance with an equal, but opposite resistance R, then
the tank would oscillate continually as shown in Figure 2.2.
VOU T

C
IIN

Figure 2.2: VCO with negative resistance (R) added to overcome positive resistance R.
The negative resistance is achieved through the use of an active circuit. This
is more accurately described as a non-linear resistor NR as shown in Figure 2.3(a).
The non-linear resistor has a characteristic which has a negative resistance for a
portion of its IV characteristic. This can be achieved through the use of a CMOS
cross-coupled pair which approximates the ideal negative resistance characteristic.
This characteristic will be similar to that shown in Figure 2.3(b). As can be seen
in the characteristic, for a portion of the voltage swing applied across NR the slope
is negative, hence if NR only acts in this region, the circuit shown in Figure 2.3(a)
will act like the circuit described in Figure 2.2.

2.1 LC-VCO

6
f (VC )

IIN

IL

L
VIN

VC

NR

VDD

VDD
g0

(a)

(b)

Figure 2.3: Oscillator Model: (a) Representation of Oscillator with NR

representing the active components of the circuit. (b) Desired IV Characteristic of NR .
Choice of VCO Topology
As was mentioned in the introduction it was decided to choose a cross-coupled
CMOS LC-VCO with a tail current source for the oscillator topology. This topology, shown in Figure 2.4 utilizes both NMOS and PMOS cross-coupled pairs to
provide the negative resistance necessary to cancel the losses in the tank circuit.
This topology allows a large voltage swing at the output of the oscillator when compared to many other oscillator toplogies. The current source in the tail does reduce
the output voltage swing slightly, but offers extra control to the designer and as
outlined later is advantageous when transforming the VCO to act as an ILFD. The
large voltage swing at the output is advantageous as it helps improve phase noise
performance [11]. Also the differential mode of operation (taking output from V+
and V ) lowers undesirable effects such as supply and substrate noise and also can
eliminated the need for single ended to differential output circuitry.
The main disadvantage of the circuit is the presence of the PMOS transistors
(M1 and M2 ). Since these transistors are PMOS they have to be larger than the
NMOS transistors in the oscillator to overcome the low mobility of the majority
charge carriers in the devices. Usually this means that the PMOS devices have
to be 23 times larger than the NMOS devices. This has negative effects such as
increasing the overall size of the oscillator and perhaps more importantly increasing
the parasitic capacitances of the oscillator, thus negatively impacting on parameters
such as the tuning range of the VCO.

2.1 LC-VCO

VDD

M1

M2

C
IBIAS

M3

M5

V+

M4

M6

Figure 2.4: Chosen LC-VCO Topolgy. Cross-Coupled Inverters M1 to M4 ,

generate the negative resistance needed to overcome the losses in the LC
tank.
Despite these disadvantages the circuit shown in Figure 2.4 was chosen ahead of
that shown in Figure 2.5. This was mainly due to the work done on characterising
the cross-coupled device within the department previously [12]. Also the fact that
that only one inductor exists in the circuit makes the implementation far easier as
the components do not have to be matched.
The current source in the tail of Figure 2.4 offers considerable advantages over the
topology without the current source that was outlined in [10]. The current source
allows control over the amplitude of oscillation and the power dissipation that is
independent of the supply voltage VDD .

2.1 LC-VCO

VDD

L
2

L
2

C
IBIAS
V

V+

M3

M5

M4

M6

Figure 2.5: Alternative LC-VCO Topolgy. Consists of only NMOS Transistors. Note that inductance L is created by using two inductors of
inductance L2 .

2.1.3

Simulation & Implementation

With the choice of topology having been made the next step was to choose the
component values so as to be able to implement the design. At this stage of the
project PSpice was utilized to see how the VCO reacted to changes in component
values and transistor model parameters.
As was mentioned briefly in Section 2.1.2 it is necessary to create a negative
resistance using the transistors M1 to M4 to create a non-linear resistance. In order
to quantify the negative resistance created by the transistors present in our design
we used PSpice to create a driving point (DP) characteristic. This is shown in
Figure 2.6.
The DP characteristic is a plot of the current in the non-linear resistor versus the

2.1 LC-VCO

Figure 2.6: PSpice Driving Point Characteristic.

voltage across it, i.e. the output conductance of the nonlinear resistor. The slope at
V=0 is denoted by g0 and can be used to calculate whether or not the circuit will
oscillate. The mathematical background is outlined in [10] but the most important
results are repeated here. Essentially the analysis concludes that the circuit will
oscillate if the following conditions are satisfied:

R<

1
L
and R < g0 .
g0
C

(2.1)

The analysis also predicts the frequency of oscillation as:

1
f=
2

1 + g0 R
.
LC

(2.2)

Reading the slope of the curve in Figure 2.6 around V=0, we can calculate
g0 . Initially we believed that this would be large enough to satisfy the oscillation
criterion as outlined in Eq. (2.1). Next we choose values of L and C such that the
circuit would be capable of oscillating at a frequency of 1.75 MHz. The choice of
this frequency was not arbitrary. At this frequency it is possible to build the circuit
on breadboard, without unnecessary concern regarding the layout of the circuit for
RF reasons. To calculate the components values required Eq (2.2) is simplified to

f = 1/2 LC as precise calculation of L and C is not needed since the tolerances

of the components will make it impossible to find those exact values.

2.1 LC-VCO

10

So at this stage using CD4007N chips the cross-coupled CMOS LC was implemented. As described briefly here and in more detail in David Bourkes report,
problems were encountered due to the lossy nature of the components used in the
oscillator. The losses involved were larger than what we first estimated. This meant
that g0 was not large enough to over come the losses, so to overcome the lossy nature of the components and breadboard, it was necessary to increase the W
ratio in
L
the transistors used in the cross-coupled pair. This is performed on the breadboard
by connecting multiple PMOS or NMOS transistors in parallel. This has the same
ratio in PSpice.
effect as increasing the W
L
To model the circuit to a reasonable degree of accuracy in PSpice it was necessary
to find some of the model parameters for the CD4007N devices. These parameters
were obtained by using the parameters found in [12] and [10]. These parameters are
repeated in Appendix A. Having input these values into PSpice, and increased the
W
ratio, an increased slope around V=0 was observed both experimentally and in
L
simulation.
ratio.
Figure 2.7 shows the increase in the slope with the increased transistor W
L
As can be seen and measured from the curve the slope g0 is now steeper and thus
the negative resistance is large enough to overcome the lossy components.

Figure 2.7: Comparison between the PSpice Driving Point Characteristics. Solid Line: Original Characteristic. Dashed Line: Increased W
L
Ratio Characteristic.

2.1 LC-VCO

11

Experimental Measurement of Driving Point Characteristic

The technique for the experimental extraction was taken from [12]. It requires
the use of a function generator and an op-amp to display the resultant characteristic.
Figure 2.8(a) shows the experimental setup. The NR is simply the points on either
side of the LC tank. The VCO must be powered while the characteristic is being
taken, but it is necessary to power it from a supply with a floating ground. To
achieve this the VDD is supplied from a 9V battery.
R

V1

V2

V
V

VIN

NR

 V

OU T

R
R

(a)

(b)

Figure 2.8: Experimental Extraction of Driving Point Characteristic: (a)

Circuit Used. (b) Difference Op-Amp used to capture small voltage drop
across resistor.
The voltage VIN is swept from V across the input of the resistor and plotted
against the measuring current IR . Plotting VIN against IR yields the driving point
characteristic.
A function generator set to a low frequency triangular wave simulates a voltage
sweep and is used as the Vin. The current is measured using the sense resistor
R. The voltages V1 and V2 on either side of this sense resistor are measured and
inputted into the op-amp circuit as shown in Figure 2.8(b). The difference op-amp
gives an output:
VOU T = V1 V2
which is related to the current through the resistor by:
IR =

V1 V2
R

2.2 ILFD

12

Plotting the output of the op-amp, VOU T , against the voltage across the terminals
of the nonlinear resistor, V2 , yields the driving point characteristic of the particular
nonlinear resistor. A sense resistor of 100 is adequate for most characterisations.

Figure 2.9: Example Driving Point Characteristic from Tektronix

TDS5054 Oscilliscope. Channel 1: X-Axis 2V/Div. Channel 2: Y-Axis
2mA/Div.

2.2

ILFD

At this stage a VCO had been designed and implemented as outlined in 2.1.3.
The next step is to manipulate this VCO design so it is capable of being used as
an ILFD. This is described in this section. Again I was responsible for much of
the design and simualation work, while David Bourke solved many of the problems
ecountered in implementing the circuit.

2.2.1

ILFD Topologies

There are a number of different ILFD topologies available. Two of them are
outlined in this section. Initially we chose the topology shown in Figure 2.10. This
topology was chosen due to its similarity to the LC-VCO created previously. With

2.2 ILFD

13

the work characterising the LC-VCO topolgy having been done previously, the creation of an ILFD simply required the alteration of the circuit to allow an injection
signal be applied at some point in the circuit.
VDD

M1

M2

C
IBIAS

RS

M3

M4

R
M5

M6

VIN J

CIN J

Figure 2.10: Injection Locked Frequency Divider Topology.

This topology (Figure 2.10) is known as the classical injection topology. As can
be seen the VCO from Section 2.1.2 has been altered so as to allow the injection of
an input signal on the tail current source. The capacitor acts as a high-pass filter
so that the input sinusoids perturb the bias point thus injecting a signal. This
topology was the first chosen by us but toward the end of the project it was decided
to investigate some alternative topologies.
While the classical injection topology appears to be the most popular ILFD
topology [13] [14] used in realizing ILFDs, Tiebout outlines some of the disadvantages
to the topology in [9] and outlines an alternative direct-injection based topology.
The circuit shown in Figure 2.11 is based upon this topology. As can be seen the
injected signal is now applied directly to the LC tank.
The main reason for initially choosing the classical injection-locked topology
ahead of the direct injection based topology was its popularity. The work that had
been previously performed on it suggested that it would be possible to match the

2.2 ILFD

14
VDD

M1

M2

VIN J
M7

C
IBIAS

M3

M5

V+

M4

M6

Figure 2.11: Direct Injection Based Injection-Locked Oscillator Topology.

experimental results to one of the models. However as is clear from a visual analysis
of both topologies, there is very little different between them, hence altering the
circuit to move from one topology to another was not difficult.

2.2.2

Implementation

As mentioned previously in Section 2.2.1 we first implemented the divider using

the classical injection topology. This did not require extensive changes to the VCO.
When David Bourke had made the necessary changes to the VCO we set about
initially getting a feel for the circuit. This involved manually selecting injection
frequencies (fIN J ) and voltages (VIN J ) and applying the resultant sinusoid to the
circuit. We would then visually observe the effects of the injected signal on the
natural frequency of the ILFD.

2.2 ILFD

15

To have a specification to work toward, Professor Kennedy suggested that we

attempt to show that the ILFD was capable of dividing across the GSM receive band.
This ranges from 1.715 GHz to 1.785 GHz. To demonstrate this we attempted to
build a frequency scaled model on the breadboard. To achieve this we would require
an oscillator operating at 3.5 MHz and a divider with a natural frequency of 1.75
MHz. We would then vary the frequency of the oscillator and attempt to have the
divider divide-by-two over all input frequencies between 3.4 MHz and 3.6 MHz, this
would correspond to output frequencies covering the entire receive band.
It became apparent that the divider was incapable of locking over a sufficiently
large locking range so changes had to be made. It was observed that the use of a
larger inductor allowed for a larger locking range. This was contradictory to some of
the models previously outlined. At this stage it was decided to create an automated
testing procedure to attempt to characterise the circuit. This is described in far
more detail in Section 3.1
Having completed the testing as described in Section 3.1, the component values
to achieve the specification outlined previously were known. So now our VCO could
be used to drive the ILFD and produce a signal which had been divided by two. To
successfully implement the topology shown in Figure 2.10 it was necessary to alter
it so as to load the VCO (Figure 2.4) equally on both sides of the LC tank. This
was achieved as shown in Figure 2.12. Here extra circuitry has been added so as to
load the VCO symettrically.
With this circuit implemented the VCO was now capable of driving the divider.
Changing the frequency on the VCO saw the output of the divider also change as
intended. The frequency of the VCO was altered simply by changing the value of
the capacitance using a variable capacitor. This is shown in Appendix B. As the
capacitance of the variable capacitor was changed the VCO frequency was swept
from 3.4 MHz to 3.6 MHz the output of the divider moved through the desired
range of frequencies.

2.2 ILFD

16

VDD

M1

M2

C
IBIAS

VDIV

M3

VDIV+

M4

R
M5

M6

C1
M5
C1

V+

Figure 2.12: Injection Locked Divider Topology with load balancing for
Input VCO.

17

Chapter 3

Testing And Modeling an ILFD

In this Chapter the process of testing the ILFD and attempting to model its operation are discussed. Firstly the steps involved in automating the testing procedure
are discussed. Following this the process of modeling the ILFD are discussed.

3.1

Testing

In this section the process for automatically testing the ILFD is outlined. In [15]
a process for automatically obtaining the Devils Staircase structure of an ILFD is
described. That structure is useful to us as it shows the input locking range for the
oscillator and thus can be used to compare our experimental results to the existing
models for injection-locking.

3.1.1

Basics

The experimental setup used is shown in Fig. 3.1. The driving voltage VIN J and
the driving frequency fIN J are produced by a precision frequency generator (Agilent
33220A) connected to a IEEE-488 bus. We estimate the frequency of the driven
oscillator (fd ) through the use of a precision counter (Agilent 53131A) which is also
under IEEE-488 control.
Once the circuit under test has been connected to the signal generator and
counter, we set the frequency of the undriven circuit to the desired natural frequency f0 . We then specify the frequency range, step size and amplitude range of
the forcing signal. The software (Agilent VEE Pro 7.0) then initializes the instruments and begins to take measurements.
Should one wish to examine a section of the staircase at a higher resolution, the
step-size can be decreased (to increase input resolution) and the resolution of the

3.1 Testing

18

FUNCTION
GENERATOR

NONLINEAR
OSCILLATOR

P.C. WITH IEEE 488

CONTROLLER
IEEE 488

FREQUENCY
COUNTER

IEEE 488

Figure 3.1: Experimental Setup for Automated Measurement of Locking

Range.
counter measurements can also be increased.

3.1.2

Agilent VEE Setup

David Bourke did the majority of work on creating the Agilent interface to automate the testing procedure and thus it is discussed in far more detail in his report.
However Figure 3.2 shows a screenshot of the Agilent VEE interface reproduced
from David Bourkes report.

Figure 3.2: Complete Agilent VEE Interface.

3.2 Modeling

19

To obtain the data displayed in Section 4.1 the user must input the chosen voltage
sweep values and the chosen frequency sweep values. Figure 3.3 shows in detail the
area where the user inputs the values.

Figure 3.3: Agilent VEE Interface for selecting voltage and frequency
sweep. Voltage to be swept from 0.25V to 6V with a step-size of 0.25V.
Frequency is swept from 1 kHz to 10 MHz with a step-size of 1 kHz.
When Agilent creates the text files containing the output data it is necessary
to remove the error values. This can be done easily in MATLAB by parsing the
array and removing the error. The error value was then replace by an interpolated
value. The number of errors was extremely small (50 in 250,000 measurements) so
the impact of them is minimal.
When the array has been fixed, the values are then simply plotted. Using the
following command plots such as the one that can be seen in Figure 3.4 are created.
The significance of this plot will be discussed later in the report.

3.2
3.2.1

Modeling
Existing Models

Initially attempts we made to fit our experimental results to the models which
had been previously outlined in [8] and [9]. Ultimately these attempts failed. This

3.2 Modeling

20

Figure 3.4: Example Staircase Structure created from Agilent results.

can be seen in Tables 4.6 and 4.7 where our experimental results have been compared
to the results obtained from using the model outlined in [8].
Since our other observations (variation of locking range with inductor size) differed from what was predicted by [9], it was clear that we would have to devise a
new model to accurately model the input locking range of an ILFD.
We also attempted to understand why the model in [8] did not fit our results.
In [8], Lee outlines his model based on the idea that the injected signal is summed
directly with the oscillation signal. As is clear from our topology our injection signal
is not directly added to the oscillation signal. This appears to explain why a new
model was necessary.

3.2.2

Parametric Model of an ILFD

At this stage we attempted to create a model for the ILFD we had constructed.
The model was required to accurately predict the size of the locking range based
on the circuit parameters, (e.g. Value of L). One of the post-graduate students

3.2 Modeling

21

in the department, Zhipeng Ye, was also researching the area of injection-locking,
so we worked with him toward modeling our ILFD. Zhipeng and I concentrated on
modeling the ILFD while David Bourke utilized the testing routine he had created
to extract the values we required from the circuit.
The model of the ILFD is shown in Figure 3.5. From this model, we can develop
the following equations:
f (VC )
IL

L
VC

NR

Figure 3.5: Injection Locked Frequency Divider Model. NR represents

the active components in the circuit.

dVC
= IL f (VC )
dt
dIL
L
= IL R VC .
dt

(3.1)

In Eq. (3.1), f (VC ) is the driving point characteristic of the non-linear resistor.
This characteristic can be extracted both experimentally and in PSpice. This is
described in Section 3.2.3. From Section 2.1.3 we expect that the characteristic
curves will have a cubic form. We assume the curves are of the form:

f (VC ) = aVC bVC3

where
b=

a
2
VDD

(3.2)

From observing the behaviour of the ILFD we know that when the ILFD has a
signal injected into it the parameter a is altered. To model this change, we expand
a around VGS as follows:

3.2 Modeling

22

a=a
(VGS


d
a 
+ vGS ) = a
(VGS ) +
vGS
dVGS VGS

(3.3)

Now substituting Eq. (3.3) into Eq. (3.2) and combining with Eq. (3.1) we get the
following differential equations:

dVC
A + daVin 3
= IL (A + daVin )VC +
VC
2
dt
VDD

(3.4)

dIL
= IL R VC
dt

(3.5)

For simplicity a
(VGS ) is denoted as A while

d
a 
dVGS 

VGS

is referred to as da. Vin

represents the injected sinusoid and should be of the form V sin(t) Solving (3.4)
and (3.5) with MATLAB allows us to model the operation of the oscillator. The
results from this modeling are shown in Section 4.2.

3.2.3

Extraction of Model Parameters

Eq. (3.4) and Eq. (3.5) require us to extract some parameters from the circuit in
order to have a working model. In Section 2.1.3 a driving point characteristic was
obtained for a single bias voltage on the current source. However when an injected
signal is applied this bias point will vary, thus it was necessary to obtain a number
of different characteristics for a number of different bias voltages. The results of this
are shown in Figure 3.6.
In MATLAB polynomials were fitted to these curves in order to extract a number
of different values for the coefficient a for different bias voltages. By plotting the
values of a extracted and assuming a quadratic fit in the region of interest we can
extract da as shown in Figure 3.7
At this stage it was desirable to also get the PSpice simulation to agree with
what was observed experimentally. To achieve this a MOSFET model was extracted
experimentally from the CD4007N devices. This model is shown below.
.model PMOS level=3 L=10u W=70.8u VTO=-0.78V LAMBDA=0 Kp=55.5u
.model NMOS level=3 L=10u W=35.4u VTO=1.1V LAMBDA=0 Kn=111u

3.2 Modeling

23

Figure 3.6: Driving Point Characteristics for Various Bias Voltages.

Figure 3.7: Plot of the a Co-efficients with a Quadratic Fit.

slope around bias point.

da
dVGS

indicates

3.2 Modeling

24

When PSpice simulations were preformed using this model, the driving point
characteristics extracted were almost identical to those observed in the experiment.
The values for the model parameters were also extracted from PSpice and these were
used to predict the locking range also.

3.2.4

Implementation in MATLAB

At this stage the model was implemented in MATLAB. The code used for the
simulation is shown here. Essentially MATLAB is used to solve the differential
equations Eq. (3.4) and Eq. (3.5). So for the case of an injected sinusoid of amplitude 0.75V and frequency 2.66 MHz the results of injection into our divider can be
obtained using the following code:
function dy=dlfun(t,y)
dy=zeros(2,1);
dy(1)=(y(2)-(-0.0016-5.07e-4*0.75*sin(2.66e6*2*pi*t))*y(1)+
(-0.0016-5.07e-4*0.75*sin(2.66e6*2*pi*t))*y(1)^3/50)/(131e-12);
dy(2)=(-y(2)*10-y(1))/(76.8e-6);
In the above equations the value of A was -0.0016, L was 76.8 H, C was 131 pF
while da was extracted as 5.07e-4. To utilize the m file shown above it is initiated
as follows:
[t,y]=ode45(@odea_exp, [0 5*1e-5], [2 0]);
[0 5*1e-5] indicates the time step that the m file should be run over. odea_exp
is the name given to the m file. The code then outputs a time vector t and a vector
containing the output voltages y. As shown in Section 4.2 when these are plotted it
can be found whether or not the ILFD is in lock for a particular input sinusoid.
To find the locking range the user has to perform an iterative process. The
simplest way to do this to pick an injection signal near the natural frequency of
the oscillator and run the simulation over a reasonably long time. The output is
plotted using a simple MATLAB plot command plot(t,y(:,1)). This results in
an output like is shown in Figure 3.8(a). For Figure 3.8(a), the oscillator is out of
lock. This is indicated by the slight perturbations on the output. In this case the
injection signal chosen is outside the input locking range. Now the user must now

3.2 Modeling

25

choose a frequency closer to the natural frequency. This is shown in Figure 3.8(b).
In this case the new frequency is in lock. The user should now, perhaps using a
midpoint method, iteratively pick new points to find the edge of the locking range.

(a)

(b)

Figure 3.8: Finding the Locking Range: (a) Injected Signal Outside Locking Range. (b) Injected Signal Inside Locking Range.

26

Chapter 4

Results

4.1
4.1.1

Experimental Results
Introduction

The experimental results obtained from the ILFD are detailed in this section.
All the results were taken from an ILFD with a natural frequency of oscillation of
1.745 MHz unless otherwise noted. This was designed as discussed in Chapter 2.

4.1.2

Devils Staircases

The results for the classical injection-locked oscillator are shown in Tables 4.1
and 4.2. With the amplitude of the driving oscillator set to 0 V, we set the natural
frequency, f0 , of the undriven oscillator to 1.745 MHz. We then cycle through
sinusoids with frequencies from 1 kHz to 10 MHz and amplitude 0.25 Vpp to 4 Vpp .
The results of the experiment described above are shown in the surface plot in
Fig. 4.1. On the surface plot it is possible to see the flat regions of locking where
fIN J
is constant, corresponding to a step of the staircase. These regions get wider
fd
for larger input amplitudes. To see the devils staircase structure of the oscillator,
a cross section of the plot is shown in Fig. 4.2. As observed in [15] it is possible to
zoom in on specific regions of this curve and see a self-similar staircase structure.
This can be seen in Fig 4.3.
In Fig. 4.2 the structure reveals that the ILFD is capable of locking over quite
large ranges when dividing by two, four and six. The ILFD also locks and divides by
one, three and five, but the locking ranges are not as large for these division ratios.
A cross-section of Fig. 4.4 is shown in Fig. 4.5 to illustrate the staircase structure
for the direct injection topology. This is similar to the structure shown in Fig. 4.2 but

4.1 Experimental Results

27

Figure 4.1: Locking behaviour for the classical injection locked oscillator
topology. Locking is characterised by a flat region on the plot. Note that
the widths of the locking regions increase with VIN J .

Figure 4.2: Devils Staircase with VIN J = 3V. Note the steps at fd =
fIN J fIN J fIN J
, 4 , 6 .
2

4.1 Experimental Results

28

Figure 4.3: Portion of Staircase highlighted in Fig. 4.2. Note the steps
J
J
J
at fIN
= 25 , fIN
= 21 , fIN
= 32 .
fd
fd
fd
the locking ranges vary slightly. This is not immediately apparent, but Tables 4.1
and 4.2 show the differences in the locking ranges of the two topologies.
Fig. 4.6 shows the self-similar repeating staircase for the direct injection locked
oscillator.
Ratio

Classical (MHz)

Direct (MHz)

0.0055

0.0009

0.1080

0.0415

0.0135

0.0060

0.1600

0.0395

0.0090

0.0135

0.0950

0.0300

Table 4.1: Comparison of input locking ranges with VIN J = 1 Vpp .

Both topologies show similar locking behaviour. For the 3 Vpp input signal, the
classical topology has the largest locking range in divide-by-four mode. The direct
injection topology has its largest locking range in divide-by-six mode.

4.1 Experimental Results

29

Ratio

Classical (MHz)

Direct (MHz)

0.0240

0.0185

0.3470

0.2310

0.0375

0.0440

0.4950

0.2120

0.0270

0.0830

0.3410

0.3430

Table 4.2: Comparison of input locking ranges with VIN J = 3 Vpp .

Figure 4.4: Locking behaviour for the direct injection locked oscillator
topology.

4.1 Experimental Results

30

Figure 4.5: Devils Staircase with VIN J = 3V. Note the steps at fd =
fIN J fIN J fIN J
, 4 , 6 .
2

Figure 4.6: Portion of Staircase highlighted in Fig. 4.5. Note the step at
fIN J
= 83 .
fd

4.1 Experimental Results

4.1.3

31

Parameters which affect locking range

As previously mentioned in Section 1.3 a number of different models for ILFDs

have been previously outlined. These models claim that the input injection locking
range is dependent on a number of the parameters in the circuit. With the aim of
verifying what parameters the locking range is dependent on we set about finding
the locking range of the ILFD while varying one of the parameters.

Input Amplitude
Firstly the variation in the input locking range as the amplitude of the injected
sinusoid changes was obtained. The results of this are shown in Table 4.3. As can
be clearly seen there is quite a linear increase in the bandwidth for larger input
amplitudes. This agrees with the existing models (Eq. (1.2) and Eq. (1.1)) and also
fits in with the model outlined in Section 3.2.2
Amplitude (Vpp )

Bandwidth (MHz)

1.00

0.10

1.50

0.15

2.00

0.21

Table 4.3: Comparison of input locking ranges with various input amplitudes.

Inductor Size
In the previously outlined theories of [8] and [9], there has been a contradiction
regarding the dependence of locking range on the size of the inductor present in the
ILFD. To obtain the results of this section the capacitance and the inductor present
in the circuit were changed while the frequency of operation of the divider was kept
constant. This resulted in the values of input locking range as shown in Table 4.4.
As can be clearly seen in the table, the size of the locking range was seen to
increase with for large inductor sizes. This agrees with the theory outlined in [8].
The disagreement of these measurements with the model outlined in [9] can be
explained by the fact that in [9] the author tests the variation of locking range with
inductor size on three ILFDs with different frequencies of operation. We believe that
a fairer comparison is made when the frequency of operation is kept constant while
the inductor size is varied.

4.1 Experimental Results

32

Inductor Size (H)

Bandwidth (MHz)

17

0.03

63

0.13

77

0.15

Table 4.4: Comparison of input locking ranges with various inductor sizes.
Current Source Bias Voltage
The final parameter that was varied while measuring the locking range was the
bias voltage on the current source in the tail of the divider. This change can be
visualised as moving the point around which the slope da is taken. So increasing
the bias voltage lowers the slope of da by moving it to either steeper or shallower
points on the curve shown in Figure 3.7.
As can be seen in Table 4.5 increasing the bias voltage, which leads to a smaller
da results in a smaller locking range. On the other hand decreasing the bias voltage,
which leads to a larger da results in a large locking range.
Bias Voltage (V)

Bandwidth (MHz)

4.18

0.21

5.42

0.15

8.08

0.06

Table 4.5: Comparison of input locking ranges with various bias voltages.
Its worth noting that myself and Zhipeng attempted to increase the locking range
by cascoding the current source in the tail and injecting on one of the transistors
while biasing the other with a constant voltage. This had the desired results in
simulation but it was not possible to implement on the breadboard due to time
constraints.

4.2 Model Simulations

4.2
4.2.1

33

Model Simulations
Introduction

In this section the model introduced in Section 3.2 along with that provided by [8]
are used to predict the input locking range of the divider for different parameters.
For the parametric model outlined in Section 3.2 the parameters used are the those
that were outlined in Section 3.2.4.

4.2.2

Visual Comparison of Outputs

As was outlined in Section 3.2.4 visually observing the simulation output allows
one to tell whether the circuit is in or out of lock. To show that this can be observed
experimentally also Figures 4.7 and 4.8 have been included. The comparisons show
that the simulation and the experiment give visually comparable outputs for the
oscillation voltage both in lock and out of lock.

(a) Oscilliscope Trace showing Division of the

VCO

(b) MATLAB Simulation showing Frequency

Division

Figure 4.7: Comparison between Simuation and Experiment.

4.2 Model Simulations

34

(a) Results of Simulation for Locked Oscillator

(b) Oscilliscope Trace Showing Locked Oscillator

(c) Results of Simulation for Unlocked Oscillator

(d) Oscillscope Trace Showing Unlocked Oscillator

Figure 4.8: Comparison between locked and unlocked oscillation on both

the scope and in MATLAB.

4.2.3

Comparing Modeled Results to Experiment

Lees Model
As mentioned in Section 3.2 before attempting to devise a new model for injectionlocking, we first attempted to fit our results to the existing models. As we had already shown the locking range was proportional to the inductor size we concentrated
on the model shown in Eq. (1.2). The results for these comparisons are shown in
Table 4.6 and 4.7.
As can be seen from the two tables, for the low input injection amplitudes the
model was a good match but for larger input injection amplitudes the model did
not match the experimental results. Following the further analysis and modeling

4.2 Model Simulations

35

Inductor Size (H)

Measured Bandwidth (MHz)

Prediction from [8]

82

0.045

0.04

68

0.032

0.03

22

0.009

0.01

15

0.007

0.01

Table 4.6: Comparison of Experimental Data to Lees Predictions. VIN J

= 2.5 Vpp .

Inductor Size (H)

Measured Bandwidth (MHz)

Prediction from [8]

82

0.228

0.09

68

0.195

0.08

22

0.053

0.02

15

0.042

0.02

Table 4.7: Comparison of Experimental Data to Lees Predictions. VIN J

= 6.5 Vpp .

performed it appears likely that the correlation between the results is purely coincidental as the Lee model appears to only predict locking in situations where the
injected signal is directly summed with the oscillation signal.

Parametric Model
In this section our model was utilised both with the parameters found experimentally and those obtained from PSpice. When PSpice is set up with the models
outlined in Section 3.2.3, the driving point characteristics and thus the parameters
obtained are almost identical to those extracted experimentally. A plot comparing
the driving point characteristics is shown in Figure 4.9.
Tables 4.8, 4.9 and 4.10 show the results of the comparison between the experimentally obtained locking ranges and the locking ranges obtained from the model.
In the tables, Model [P] refers to the results from the simulations based on parameters extracted from PSpice while Model [E] refers to results based on parameters
extracted from the experimental setup.
As can be clearly seen from the Tables, the model proposed in Section 3.2 provides
an excellent model for the locking range of the classical injection locked divider

4.2 Model Simulations

36
VIN J

Method

Range (M Hz)

1.00

Experiment

0.10

Model [E]

0.10

Model [P]

0.10

Experiment

0.15

Model [E]

0.16

Model [P]

0.16

Experiment

0.21

Model [E]

0.20

Model [P]

0.20

1.50

2.00

Table 4.8: Locking Range Versus Injection Amplitude f0 = 1.568 MHz.

L (H)

Method

Range (M Hz)

17

Experiment

0.03

Model [E]

0.03

Model [P]

0.03

Experiment

0.13

Model [E]

0.12

Model [P]

0.12

Experiment

0.15

Model [E]

0.16

Model [P]

0.16

63

77

Table 4.9: Locking Range Versus Inductor Size.

VGS

Method

Range (M Hz)

4.18

Experiment

0.21

Model [E]

0.21

Model [P]

0.21

Experiment

0.15

Model [E]

0.16

Model [P]

0.16

Experiment

0.06

Model [E]

0.07

Model [P]

0.07

5.42

8.08

Table 4.10: Locking Range Versus Bias Voltage.

4.2 Model Simulations

37

Figure 4.9: Driving Point Characteristics: Solid: Experiemental; Dotted:

Cubic Fit To Experiment; Dashed: PSpice.
implemented on the breadboard. The model using the experimental parameters
gives marginally better performance over that based on the PSpice parameters but
this is understandable due to the simplicity of the PSpice models used.

38

Chapter 5

Conclusions & Future Work

5.1

Conclusions

All the objectives as were stated in Section 1.2 were successfully carried out over
the duration of the project. An implementation of an ILFD being driven by a VCO
was completed. This implementation demonstrated the concept of injection-locking
and acted as a frequency scaled model of the GSM receive specification.
An automated method of testing an ILFD was devised. This technique was used
to extract the values for the locking range depending on different circuit parameters.
These results were used to show the inadequacy of the existing models for dealing
with the ILFD topology described in this report. The results obtained for the
variation in locking range with inductor size disagrees fundamentally with the theory
outlined in [9] but agrees with that found in [8].
A method of modeling to a high degree of accuracy, the locking range of the
ILFD was devised. This model predicted the locking range successfully for changes
in all the circuit parameters.
Based on the work completed, two papers have been submitted to the European
Conference on Circuit Theory and Design. The first is entitled Accurate Modeling and Experimental Validation of an Injection-Locked Frequency Divider while
the second is entitled The Devils Staircase As A Method of Comparing InjectionLocked Frequency Divider Topologies. Both of these papers have been included as
appendices to this report and can be found in Appendix C and Appendix D.

5.2

Future Work

One focus of future work that could be performed in the area would be to expand
upon the MATLAB model for injection-locking such that it would be possible for it

5.2 Future Work

39

to automatically calculate the locking range based on the input parameters without
the need for constant intervention from the user.
A high speed IC layout could be investigated, with the focus of that investigation
being an analysis of the validity of the model at higher frequencies.
Based on the results of Section 4.1.3 extensive analysis could be performed on the
impact of a change in the current source bias voltage on the operation of the circuit.
Further to this analysis could be done on a circuit implementation of Zhipeng Yes
suggestion of a cascode current source to increase input locking range.
Finally since the intention of an injection-locked frequency divider is to reduce the
power consumption of the divider in a PLL an analysis of this power consumption
versus the power consumption of a traditional method of division at a particular
frequency could be undertaken.

40

Bibliography
[1] R. Adler, A study of locking phenomena in oscillators, Proc. IEEE, vol. 61,
pp. 13801385, Oct. 1973
[2] A. E. Siegman, Lasers, Mill Valley, CA: University Science Books, 1986.
[3] V. Manassewitsch, Frequency Synthesizers, 3rd ed. New York: Wiley, 1987.
[4] J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesiser Design,
London, U.K.: Kluwer, 1998.
[5] J. Craninckx and M. Steyaert, A 1.75 GHz/3 V dual-modulus divide-by-128/129
prescaler in 0.7 m CMOS, in Proc. ESSCIRC, Sept. 1995, pp. 254257.
[6] J. Lee and B. Razavi, A 40 GHz frequency divider in 0.18 m CMOS technology, in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 259262.
[7] H.-D. Wohlmuth and D. Kehrer, A high sensitivity static 2:1 frequency divider
up to 27 GHz in 120 nm CMOS in Proc. Eur. Solid-State Circuits Conf., Firenze,
Italy, Sept. 2002, pp. 823826.
[8] H.R. Rategh and T.H. Lee, Superharmonic injectionlocked frequency dividers, IEEE J. Solid-State Circuits, vol. 34, pp. 813821, June 1999.
[9] M. Tiebout, A CMOS Direct InjectionLocked Oscillator Topology as HighFrequency Low-Power Frequency Divider, IEEE J. of Solid-State Circuits,
vol. 39, July 2004, pp. 11701174.
[10] J. Buckley, A Design Methodology for CMOS Oscillators, Masters Thesis,
Dept. of Microelectronic Engineering, UCC, Sept. 2004
[11] A. Hajimiri and T.H. Lee, Design Issues in CMOS Differential LC Oscillators,
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[12] K. ODonoghue Final Year Project Report, Dept. of Microelectronic Engineering, UCC, March 2004.

Bibliography

41

[13] S.-M. Wu and W.-L. Chen, A 5.8-Ghz CMOS VCO with Injection-Locked
Frequency Divider for IEEE 802.11a Application, ECCTD, Cracow, Poland,
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[14] T.H. Lee, H. Samavati and H.R. Rategh, 5-GHz CMOS Wireless LANs,,
IEEE Trans. on Microwave Theory and Techniques, vol. 50, Jan. 2002
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42

Appendices

MOSFET Parameters
NMOS

PMOS

level=1

level=1

vto=0.7

vto=-0.8

gamma=0.45

gamma=0.4

phi=0.9

phi=0.8

nsub=9e+14

nsub=5e+14

ld=0.08e-6

ld=0.09e-6

uo=350

uo=100

lambda=0.01

lambda=0.02

tox=9e-9

tox=9e-9

pb=0.9

pb=0.9

cj=0.56e-3

cj=0.94e-3

cjsw=0.35e-11

cjsw=0.32e-11

mj=0.45

mj=0.5

mjsw=0.2

mjsw=0.3

cgdo=0.4e-9

cgdo=0.3e-9

js=1e-8

js=0.5e-8

Table 5.1: MOSFET SPICE Parameters taken from [10].

B Photographs of Circuit

43

Photographs of Circuit

Figure 5.1: Adjustment of Input Frequency by varying VCO capacitance.

Notice the division of the frequency by two that can be seen on the
frequency counters near the top of the picture. i.e. 1.7435 MHz X 2 =
3.487 MHz.

B Photographs of Circuit

44

Figure 5.2: Breadboard containing both VCO and ILFD.

The VCO is the circuitry in the bottom half of the breadboard. Its output
frequency is adjusted by changing the variable capacitor shown in the centre. The
output is then fed through the large orange capacitors into the ILFD.

45

Accurate Modeling and

Experimental Validation of an
Injection-Locked Frequency
Divider

46
.

47
.

48
.

49
.

50

The Devils Staircase

As A Method of Comparing
Injection-Locked Frequency
Divider Topologies