SUMMER TRAINING REPORT

ON
VLSI DESIGN & EMBEDDED SYSTEMS
(VDES 2016)
SUBMITTED BY
Ankit Kulshrestha

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY
ALLAHABAD 211004

Motilal Nehru National Institute of Technology Allahabad

Department of Electronics and Communication Engineering

CERTIFICATE

This is to certify that Ms. Deeksha Saxena of Hindustan Institute of Technology and
Management , Agra has participated in summer training programme on VLSI Design &
Embedded System (VDES-2016)at Motilal Nehru National Institute of Technology
Allahabad, organized by Department of Electronics and Communication Engineering from 15 th
June to 13th July 2016. The conduct of participant during the course was good.

Date:13-07-15
Place: Allahabad

Course Coordinator
(VDES 2016)

MNNIT, Allahabad

ACKNOWLEDGEMENT
It is pleasure to acknowledge the assistance and contribution of the individuals who co-operated
with me to complete the project work successfully.
First and foremost, I wish to express my deep gratitude and thanks to Prof. V.K. Srivastavafor
their enthusiastic guidance and helpful in successful completion of our training. They provided
us their precious time for valuable suggestions encouragement throughout the training. It is only
due to their patience, guidance and encouragement at all time that this project has shaped up the
way it is.
I am also grateful to respected Prof. S.K. Gupta and V. Narendra for permitting me to utilize all
the necessary facilities of the institution. I am also thankful to all other faculty and staff
members of electronics and communication department for their kind cooperation and help.
I thank profusely all the volunteers of MNNIT, Allahabad for their kind help and cooperation
throughout the training period.
Lastly I would like to express our deep appreciation towards my classmates and my indebtness
to for providing me the moral support and encouragement.

DATE: 13-07-2016
PLACE: ALLAHABAD

ANKIT KULSHRESTHA

ABSTRACT
In the first section of the report a model of Traffic control light implementation on 8051
microcontroller is described. As in this era we want pace and control both. But one is possible
on the cost of the other. So to equally giving weightage to both, we need a well design traffic
system.
Though this project is almost same as located on the crossings of our country but one
amendment is made to increase the security. Only one side is allowed to travel at one time to
avoid road accidents and decrease the load of road. For implementation 12 LEDs are used as 4
sets of traffic light systems.

In the second section of this report, write operation of SRAM schematic is implemented using
EDA tool Mentor Graphics.
The structure of a 6 transistor SRAM cell, storing one bit of information. The core of the cell is
formed by two CMOS inverters.Only one bit memory is made to reduce complexity of the
circuit.
Here, WRITE operation is made by giving inputs WL (word line), BL (bit line)
,performing HOLD and STORE operation and checking the output Q at the same time.

TABLE OF CONTENTS
No.

Contents

Certificate

Acknowledgement

Table of contents

Abstract

Introduction to tool and

kits used in project 1

Introduction to tool and

kits used in project 2

Project 1

Output /result

Conclusion

10

Project 2

11

Output /result

12

Conclusion

13

APPENDIX

Pg. No.

INTRODUCTION TO TOOLS AND KITS USED IN

PROJECT 1 : 8051 MICROCONTROLLER
The 8051 microcontroller is an 8-bit microcontroller introduced by Intel corporation. this
microcontroller has 128 bytes of Random Access Memory(RAM), 4K bytes of on-chip Ream
Only Memory(ROM), two timers, one serial port and four port(each 8-bits wide) all on a single
chip. The Central Processing Unit (CPU) can work only on 8-bit of data at a time. The 8051 has
four I/O ports, each 8- bits wide.

INTRODUCTION TO 8051 KIT

The Intel MCS-51 (commonly termed 8051) is an internally Harvard
architecture, complex instruction set computing (CISC) instruction set,
single chip microcontroller (C) series developed by Intel in 1980 for use
in embedded systems.[1] Intel's original versions were popular in the 1980s
and early 1990s and enhanced binary compatible derivatives remain
popular today.
Intel's original MCS-51 family was developed using N-type metal-oxidesemiconductor (NMOS) technology like its predecessor Intel MCS-48, but
later versions, identified by a letter C in their name (e.g., 80C51) used
complementary metaloxidesemiconductor (CMOS) technology and
consume less power than their NMOS predecessors. This made them more
suitable for battery-powered devices.
The family was continued in 1996 with the enhanced 8-bit MCS-151 and the
8/16/32-bit MCS-251 family of binary compatible microcontrollers.[2] While
Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family,
enhanced binary compatiblederivatives made by numerous vendors remain
popular today. Some derivatives integrate a digital signal processor (DSP).
Beyond these physical devices, several companies also offer MCS-51
derivatives as IP cores for use in field-programmable gate array (FPGA)
orapplication-specific integrated circuit (ASIC) designs. ROM of 4KB and
RAM of 128 bytes

INTRODUCTION TO TOOL AND KITS USED IN

PROJECT 2: MENTOR GRAPHICS
MENTOR GRAPHICS:
Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic
design automation (EDA) for electrical engineering and electronics.
Mentor graphics is very useful tool for designing layout , Mentor Graphics is a global
company with product development taking place in the USA, Europe, Japan, Pakistan,
India and Egypt. In keeping with global trends in software development, the company
has a substantial labor force in lower cost locations such as Pakistan, India, Poland,
Hungary and Egypt. James "Jim" Ready, one of the more colorful people in embedded
systems, left Mentor in 1999 to form the embedded Linux company MontaVista. Neil
Henderson, a pioneer in the royalty-free, source provided market space, joined Mentor
Graphics in 2002 with the acquisition of Accelerated Technology Inc

PROJECT-1
AIM FOUR WAY TRAFFIC LIGHT SYSTEM WITH 7
SEGMENT DISPLAY USING 8051

INTRODUCTION
Traffic lights, which may also be known as stoplights, traffic lamps, traffic signals,
signal lights, robots or semaphore, are signaling devices positioned at road
intersections, pedestrian crossings and other locations to control competing flows of
traffic.

ABOUT THE COLORS OF TRAFFIC LIGHT CONTROL

Traffic lights alternate the right of way of road users by displaying lights of a
standard color (red, yellow/amber, and green), using a universal color code (and a
precise sequence to enable comprehension by those who are color blind).
In the typical sequence of colored lights:

Illumination of the green light allows traffic to proceed in the direction

denoted,

Illumination of the yellow/amber light denoting, if safe to do so, prepare to

stop short of the intersection, and

Illumination of the red signal prohibits any traffic from proceeding. Usually,
the red light contains some orange in its hue, and the green light contains some
blue, for the benefit of people with red-green color blindness, and "green" lights in
many areas are in fact blue lenses on a yellow light (which together appear green)

INTERFACING TRAFFIC LIGHT WITH 8051

The Traffic light controller section consists of 12 Nos. point LEDS are arranged 8051 Trainer kit. Each lane has
Go (Green), Listen (Yellow) and Stop (Red) LED is being placed.

LIGHT

WAY1

WAY2

WAY3

WAY4

RED

P2.0

P2.5

P3.0

P3.5

YELLOW

P2.1

P2.6

P3.1

P3.6

GREEN

P2.2

P2.7

P3.2

P3.7

TABLE 1 (PORT USED TO REPRESENT DIFFERENT TRAFFIC LIGHTS)

This system uses 8051 microcontroller, 7-segments and LEDs for indication. The LEDs which
was used as lights were connected to the Microcontroller by means of common Anode
configuration. In this configuration the Microcontroller was used to sink the current from the
LED to its ports. That means logic 0 signal in the Microcontroller switches the LED ON and
logic 1 signal switches the LED off.

ANKIT INSERT PICTURE

OF BLINKING LED ONLY
TO SHOW PORT USAGE

FIGURE-1 FOUR WAY INTERSECTION OF ROADS

1.
2.
3.
4.
5.
6.
7.
8.

P2.0
G1

P2.1
Y1

P2.2
R1

P2.5
G2

P2.6
Y2

P2.7
R2

P3.0
G3

P3.1
Y3

P3.2
R3

P3.5
G4

P3.6
Y4

P3.7
R4

0
0
1
1
1
1
1
1

1
1
1
1
1
1
1
0

1
1
0
0
0
0
0
1

1
1
0
0
1
1
1
1

1
0
1
1
1
1
1
1

0
1
1
1
0
0
0
0

1
1
1
1
0
0
1
1

1
1
1
0
1
1
1
1

0
0
0
1
1
1
0
0

1
1
1
1
1
1
0
0

1
1
1
1
1
0
1
1

0
0
0
0
0
1
1
1

TABLE-2 INPUTS GIVEN TO DIFFERENT PORTS

(3)

OUTPUT RESULT
12 LEDs shows 4 sets of traffic lights and for each traffic light configuration count starts on seven segment
display.
CASE
1.
2.
3.
4.
5.
6.
7.
8.

P2.0
G1
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF

P2.1
Y1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON

P2.2
R1
OFF
OFF
ON
ON
ON
ON
ON
OFF

P2.5
G2
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF

P2.6
Y2
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF

P2.7
R2
ON
OFF
OFF
OFF
ON
ON
ON
ON

P3.0
G3
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF

P3.1
Y3
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF

P3.2
R3
ON
ON
ON
OFF
OFF
OFF
ON
ON

P3.5
G4
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON

P3.6
Y4
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF

P3.7
R4
ON
ON
ON
ON
ON
OFF
OFF
OFF

TABLE-3 OBSERVED PATTERN OF LEDS

On seven segment display count of fifty and ten is observed on seven segment
display alternatively after each case.

FIGURE-2 IMPLEMENTATION OF PROJECT

CONCLUSION
With the correct traffic light system we can facilitate the traffic facility in
any area, city, country and hence in the world.
This project is a small model of traffic light system situated on different
road crossings to avoid the accidents with counter counting the time while
each side has to wait.

PROJECT -2
AIM DRAW SCHEMATIC OF 6T RAM AND OBSERVE ITS
CHARACTERISTIC WAVE USING MENTOR GRAPHICS

INTRODUCTION
The memory circuit is said to be static if the stored data can be retained indefinitely, as long as
the power supply is on, without any need for periodic refresh operation. The data storage cell,
i.e., the one-bit memory cell in the static RAM arrays, invariably consists of a simple latch
circuit with two stable operating points. Depending on the preserved state of the two inverter
latch circuit, the data being held in the memory cell will be interpreted either as logic '0' or as
logic '1'. To access the data contained in the memory cell via a bit line, we need atleast one
switch, which is controlled by the corresponding word line.
A low power SRAM cell may be designed by using cross-coupled CMOS inverters. The most
important advantage of this circuit topology is that the static power dissipation is very small;
essentially, it is limited by small leakage current. Other advantages of this design are high noise
immunity due to larger noise margins, and the ability to operate at lower power supply voltage.
The major disadvantage of this topology is larger cell size. The circuit structure of the full
CMOS static RAM cell is shown in Figure 2.1 The memory cell consists of simple CMOS
inverters connected back to back, and two access transistors. The access transistors are turned
on whenever a word line is activated for read or write operation, connecting the cell to the
complementary bit line columns.

Fig. 2.1

Static random access memory (SRAM) can retain its stored information as long as
power is supplied. This is in contrast to dynamic RAM (DRAM) where periodic
refreshes are necessary or non-volatile memory where no power needs to be
supplied for data retention, as for example flash memory. The term ``random
access'' means that in an array of SRAM cells each cell can be read or written in any
order, no matter which cell was last accessed.
Fig. 2.2

The structure of a 6 transistor SRAM cell, storing one bit of information. The core of the cell is
formed by two CMOS inverters, where the output potential of each inverter Vout is fed as input
into the other Vin. This feedback loop stabilizes the inverters to their respective state.
The access transistors and the word and bit lines, WL and BL, are used to read and write from
or to the cell. In standby mode the word line is low, turning the access transistors off. In this
state the inverters are in complementary state. When the p-channel MOSFET of the left inverter
is turned on, the potential V1out is high and the p-channel MOSFET of inverter two is turned
off, Vr,out is low.
To write information the data is imposed on the bit line and the inverse data on the inverse bit
line, ~BL. Then the access transistors are turned on by setting the word line to high. As the
driver of the bit lines is much stronger it can assert the inverter transistors. As soon as the
information is stored in the inverters, the access transistors can be turned off and the
information in the inverter is preserved.
For reading the word line is turned on to activate the access transistors while the information is
sensed at the bit lines.

 MENTOR GRAPHICS : SCHEMATIC

MENTOR GRAPHICS : GENERATED SYMBOL

OUTPUT
When WL is high, output Q changes with the value of BL, called the storing
operation. But when WL is low, Q keeps the last stored value i.e. now
memory is in the state of HOLD.

DESIRED WAVEFORM

CONCLUSION
The structure of a 6 transistor SRAM cell, storing one bit of information.
The core of the cell is formed by two CMOS inverters.6T RAM schematic
and it output waves are successfully implemented and tested.

APPENDIX
CODE-1
void count1();
void count2();
void main() {
while(1)
{
p2_0_bit=0;
p2_1_bit=1;
p2_2_bit=1;

p2_5_bit=1;
p2_6_bit=1;
p2_7_bit=0;

p3_0_bit=1;
p3_1_bit=1;
p3_2_bit=0;

p3_5_bit=1;
p3_6_bit=1;
p3_7_bit=0;

count1() ;

p2_0_bit=0;

p2_1_bit=1;
p2_2_bit=1;

p2_5_bit=1;
p2_6_bit=0;
p2_7_bit=1;

p3_0_bit=1;
p3_1_bit=1;
p3_2_bit=0;

p3_5_bit=1;
p3_6_bit=1;
p3_7_bit=0;

count2();
p2_0_bit=1;
p2_1_bit=1;
p2_2_bit=0;

p2_5_bit=0;
p2_6_bit=1;
p2_7_bit=1;

p3_0_bit=1;
p3_1_bit=1;
p3_2_bit=0;

p3_5_bit=1;
p3_6_bit=1;
p3_7_bit=0;

count1();
p2_0_bit=1;
p2_1_bit=1;
p2_2_bit=0;

p2_5_bit=0;
p2_6_bit=1;
p2_7_bit=1;

p3_0_bit=1;
p3_1_bit=0;
p3_2_bit=1;

p3_5_bit=1;
p3_6_bit=1;
p3_7_bit=0;

count2();
p2_0_bit=1;
p2_1_bit=1;
p2_2_bit=0;

p2_5_bit=1;
p2_6_bit=1;
p2_7_bit=0;

p3_0_bit=0;
p3_1_bit=1;
p3_2_bit=1;

p3_5_bit=1;
p3_6_bit=1;
p3_7_bit=0;

count1();

p2_0_bit=1;
p2_1_bit=1;
p2_2_bit=0;

p2_5_bit=1;
p2_6_bit=1;
p2_7_bit=0;

p3_0_bit=0;
p3_1_bit=1;
p3_2_bit=1;

p3_5_bit=1;

p3_6_bit=0;
p3_7_bit=1;

count2();

p2_0_bit=1;
p2_1_bit=1;
p2_2_bit=0;

p2_5_bit=1;
p2_6_bit=1;
p2_7_bit=0;

p3_0_bit=1;
p3_1_bit=1;
p3_2_bit=0;

p3_5_bit=0;
p3_6_bit=1;
p3_7_bit=1;

count1();

p2_0_bit=1;
p2_1_bit=0;
p2_2_bit=1;

p2_5_bit=1;
p2_6_bit=1;
p2_7_bit=0;

p3_0_bit=1;
p3_1_bit=1;
p3_2_bit=0;

p3_5_bit=0;
p3_6_bit=1;
p3_7_bit=1;
count2();
}

void count1()
{
inti,j,c;
char arr[20]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
{
for(i=0;i<=4;i++)
{
for(j=0;j<=9;j++)
{for(c=0;c<=20;c++)
{
p1=1;
p0=arr[j];
delay_ms(12);

p1=2;

p0=arr[i];
delay_ms(8);
}
}
}
}
}
void count2()
{
intj,c;
char arr[]={0xc0,0xf9,0xa4,0xb0,0x99,0x92,0x82,0xf8,0x80,0x90};
{
for(j=0;j<=9;j++)
{for(c=0;c<=20;c++)
{
p1=1;
p0=arr[j];
delay_ms(12);

}
}
}
}