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DDR2 SDRAM
Device Operations
&
Timing Diagram
Contents
1. Functional Description
1.1 Simplified State Diagram
1.2 Basic Function & Operation of DDR2 SDRAM
1.2.1 Power up and Initialization
1.2.2 Programming the Mode and Extended Mode Registers
1.2.2.1 DDR2 SDRAM Mode Register (MR)
1.2.2.2 DDR2 SDRAM Extended Mode Register
1.2.2.3 Off-Chip Driver(OCD) Impedance Adjustment
1.2.2.4 ODT(On Die Termination)
1.3 Bank Activate Command
1.4 Read and Write Command
1.4.1 Posted CAS
1.4.2 Burst Mode Operation
1.4.3 Burst Read Command
1.4.4 Burst Write Operation
1.4.5 Write Data Mask
1.5 Precharge Operation
1.6 Auto Precharge Operation
1.7 Refresh Commands
1.7.1 Auto Refresh Command
1.7.2 Self Refresh Command
1.8 Power Down
1.9 Asynchronous CKE LOW Event
1.10 No Operation Command
1.11 Deselect Command
2. Truth Tables
2.1 Command Truth Table
2.2 Clock Enable(CKE) Truth Table for Synchronous Transistors
2.3 Data Mask Truth Table
3. Maximum DC Ratings
3.1 Absolute Maximum DC Ratings
3.2 Operating Temperature Condition
4. AC & DC Operating Conditions
4.1 DC Operation Conditions
4.1.1 Recommended DC Operating Conditions(SSTL_1.8)
4.1.2 ODT DC Electrical Characteristics
4.2 DC & AC Logic Input Levels
4.2.1 Input DC Logic Level
4.2.2 Input AC Logic Level
4.2.3 AC Input Test Conditions
4.2.4 Differential Input AC Logic Level
4.2.5 Differential AC output parameters
4.2.6 Overshoot / Undershoot Specification
4.3 Output Buffer Levels
4.3.1 Output AC Test Conditions
4.3.2 Output DC Current Drive
4.3.3 OCD default chracteristics
4.4 Default Output V-I Characteristics
4.4.1 Full Strength Default Pulldown Driver Characteristics
2
1. Functional Description
1.1 Simplified State Diagram
Initialization
Sequence
CKEL
OCD
calibration
Self
Refreshing
SRF
CKEH
PR
Idle
Setting
MR
EMR
(E)MR
REF
All banks
precharged
Refreshing
CKEL
ACT
CKEL
CKEH
Precharge
Power
Down
Activating
CKEL
CKEL
CKEL
Automatic Sequence
Active
Power
Down
Command Sequence
CKEH
CKEL
Bank
Active
Read
Write
Write
Read
WRA
Writing
RDA
Read
Write
Reading
RDA
WRA
WRA
Writing
with
Autoprecharge
RDA
PR, PRA
PR, PRA
PR, PRA
Precharging
Reading
with
Autoprecharge
Note: Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions
and the commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions,
- among other things - are not captured in full detail
Figure 1. DDR2 SDRAM simplified state diagram
3
CK
/CK
tIS
CKE
tIS
ODT
Command
PRE
ALL
NOP
400ns
tRP
PRE
ALL
MR
EMR
tMRD
tMRD
DLL
ENABLE
DLL
RESET
REF
tRP
MR
REF
tRFC
tRFC
EMR
tMRD
ANY
CMD
EMR
Follow OCD
Flowchart
tOIT
OCD
CAL. MODE
EXIT
0*1
0*1
WR
A7
No
Yes
BA0
A9
DLL Reset
BA1
PD
A10
A8
Active power
down exit time
A12
A12 A11
MR mode
MR
EMR(1)
EMR(2)
EMR(3)
A8
A7
DLL
TM
A6
A5
A4
CAS Latency
A3
BT
A2
A1
A0
Burst Length
Address Field
Mode Register
Burst Length
mode
A3
Normal
Sequential
A2
A1
A0
BL
Test
Interleave
Burst Type
A10
A9
WR(cycles)
Reserved
7(Optional)
8(Optional)
CAS Latency
*2
DDR2-400
DDR2-533
DDR2-667
DDR2-800
DDR2-1066
BA2
A6
A5
A4
Latency
Reserved
2(optional)
Reserved
*1 : BA2 and A13~A15 are reserved for future use and must be programmed to 0 when setting the mode register.
*2: For DDR2-400/533. WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR
in clock cycles is calculated by dividing WR (in ns) by tCK (in ns) and rounding up to the next integer (WR[cycles] = WR[ns]/tCK[ns]). For
DDR2-667/800/1066. WR min is determined by tCK(avg) max and WR max is determined by tCK(avg) min. (WR[cycles] =
WR[ns]/tCK(avg)[ns]) The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
*3 : Speed bin determined. Not required on all speed bins.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning
to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation
and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset),
200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
A12
0*1 0
0*1
BA1
A11
A10
A9
A8
A6
A5
Rtt
OCD program
MR mode
BA0
A7
A6
A2
A4
A3
A2
A1
A0
Additive latency
Rtt
D.I.C
DLL
Address Field
Extended Mode Register
Rtt (NOMINAL)
MR
ODT Disabled
EMR(1)
75
EMR(2)
150
EMR(3): Reserved
50 *2
A0
DLL Enable
Enable
Disable
Additive Latency
A9
A8
A7
Drive(1)
Drive(0)
Adjust mode*3
*4
* 3 : When Adjust mode is issued, AL from previously set value must be applied.
* 4 : After setting to default, OCD mode needs to be exited by setting A9-A7 to
000. Refer to the following 1.2.2.3 section for detailed information
A12
A3
6(Optional)
Reserved
A1
Output Driver
Impedence Control
Driver
Size
Full Strength
100%
Reduced Strength
60%
DQS
Enable
Disable
A11
A4
Qoff (Optional)*5
A10
A5
RDQS Enable*6
Disable
A11
(RDQS Enable)
Enable
0 (Disable)
0 (Enable)
DM
0 (Disable)
1 (Disable)
DM
A10
(DQS Disable)
RDQS/DM
RDQS
DQS
DQS
Hi-z
DQS
DQS
Hi-z
DQS
Hi-z
1 (Enable)
0 (Enable)
RDQS
RDQS
DQS
DQS
1 (Enable)
1 (Disable)
RDQS
Hi-z
DQS
Hi-z
*1 : BA2 and A13~A15 are reserved for future use and must be set to 0 when programming the EMR(1)
A12
A11
0*1
A7
BA1
A10
BA0
A9
A8
A7
A6
A5
A4
0*1
SRF
A3
A2
DCC*3
A1
A0
PASR*3
Address Field
Extended Mode
Register(2)
Disable
Enable(Optional)*2
MR mode
A3
DCC Enable(Optional)*4
MR
EMR(1)
Disable
EMR(2)
Enable
EMR(3):Reserved
A2
A1
A0
Full Array
Full Array
Not Defined
Not Defined
*1 : The rest bits in EMR(2) are reserved for future use and all bits except A7, BA0 and BA1 must be programmed to 0 when setting the
mode register during initialization.
*2 : Currently the periodic Self-Refresh interval is hard coded whithin the DRAM to a specific value. EMR(2) bit A7 is a migration plan to
support higher Self-Refresh entry. However, since this Self-Refresh control function is an option and to be phased-in by manufacturer
individually, checking on the DRAM parts for function availablity is necessary. For more details, please refer to Operating Temperature
Condition section at Chapter 5. AC & DC operation conditions.
*3 Optional in DDR2 SDRAM. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified
address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued. If the PASR feature is not supported, EMR(2)[A0-A2] must be set to 000 when programming EMR(2).
*4 Optional in DDR2 SDRAM. JEDEC standard DDR2 SDRAM may or may not have DCC (Duty Cycle Corrector) implemented, and in
some of the DRAMs implementing DCC, user may be given the controllability of DCC thru EMR(2)[A3] bit. JEDEC standard DDR2
SDRAM users can look at manufacturer's data sheet to check if the DRAM part supports DCC controllability. If Optional DCC Controllability is supported, user may enable or disable the DCC by programming EMR(2)[A3] accordingly. If the controllability feature is not supported, EMR(2)[A3] must be set to 0 when programming EMR(2).
A12
A11
A10
A9
A8
A7
A6
A5
A4
0*1
A3
A2
A1
A0
Address Field
Extended Mode
Register(2)
*1 :All bits in EMR(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the mode register during
initialization.
10
EMR: Drive(1)
DQ & DQS HIGH; DQS LOW
EMR: Drive(0)
DQ & DQS LOW; DQS HIGH
ALL OK
ALL OK
Test
Test
Need Calibration
Need Calibration
EMR: OCD calibration mode exit
EMR :
Enter Adjust Mode
EMR :
Enter Adjust Mode
End
Figure 7. OCD Impedence adjustment
11
A8
A7
Operation
OCD calibration mode exit
Adjust mode
Operation
DT0
DT1
DT2
DT3
Increase by 1 step
NOP
Decrease by 1 step
NOP
NOP
Increase by 1 step
NOP
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
CMD
EMR
NOP
NOP
NOP
NOP
NOP
EMR
NOP
CK
CK
WL
WR
DQS
DQS_in
tDS tDH
DQ_in
ViH(ac)
ViH(dc)
ViL(ac)
ViL(dc)
DT0
DT1
DT2
DT3
DM
Figure 8. OCD adjust mode
Drive Mode
Drive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance.
In this mode, all outputs are driven out tOIT after enter drive mode command and all output drivers are
turned-off tOIT after OCD calibration mode exit command as the following timing diagram
CMD
EMR
NOP
NOP
NOP
EMR
CK
CK
DQS
DQS
Hi-Z
Hi-Z
DQS HIGH & DQS LOW for Drive(1), DQS LOW & DQS HIGH for Drive(0)
DQs HIGH for Drive(1)
DQ
tOIT
tOIT
Figure 9. OCD drive mode
13
VDDQ
sw2
Rval2
VDDQ
sw3
Rval3
DRAM
Input
Buffer
Input
Pin
Rval1
sw1
VSSQ
Rval2
sw2
VSSQ
Rval3
sw3
VSSQ
14
T0
T1
T2
T3
T4
T5
T6
CK
CK
tIS
CKE
ODT
tIS
tIS
VIH(ac)
VIL(ac)
tAOFD
tAOND
Internal
Term Res.
RTT
tAOF,min
tAON,max
tAON,min
tAOF,max
T0
T1
T2
T3
T4
T5
T6
CK
CK
CKE
tIS
ODT
VIH(ac)
tIS
VIH(ac)
tAOFPD,max
tAOFPD,min
Internal
Term Res.
RTT
tAONPD,min
tAONPD,max
15
T-5
T-4
T-3
T-2
CK
CK
T-1
T0
T2
T1
T3
T4
tANPD
tIS
CKE
VIL(ac)
tAOFD
Internal
Term Res.
RTT
tIS
ODT
VIL(ac)
Power Down
mode timings to
be applied.
tAOFPDmax
Internal
Term Res.
RTT
tIS
ODT
VIH(ac)
tAOND
Internal
Term Res.
RTT
tIS
ODT
VIH(ac)
tAONPDmax
Internal
Term Res.
RTT
Power Down
mode timings to
be applied.
T1
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
tIS
CKE
tAXPD
VIH(ac)
ODT
VIL(ac)
tAOFD
Internal
Term Res.
RTT
tIS
Power Down
mode timings to
be applied.
ODT
VIL(ac)
tAOFPDmax
Internal
Term Res.
RTT
tIS
VIH(ac)
ODT
tAOND
Internal
Term Res.
RTT
tIS
Power Down
mode timings to
be applied.
ODT
VIH(ac)
tAONPDmax
Internal
Term Res.
RTT
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
..........
CK / CK
Internal RAS-CAS delay (>= tRCDmin)
ADDRESS
Bank A
Row Addr.
Bank B
Bank B
Col. Addr.
Row Addr.
CAS-CAS delay time (tCCD)
additive latency delay (AL)
Bank A
Col. Addr.
tRCD =1
A
. . . . . . . . .Bank
.
Addr.
Bank B
Addr.
Bank A
Row Addr.
Bank B
Precharge
Bank A
Activate
Read Begins
COMMAND
: H or L
Bank A
Activate
Bank A
Post CAS
Read
Bank B
Activate
Bank B
Post CAS
Read
A
. . . . . . . . Bank
..
Precharge
Figure 15. Bank active command cycle: tRCD =3, AL=2, tRP=3, tRRD=2, tCCD=2
18
19
-1
10
11
12
11
12
CK/CK
Active
A-Bank
CMD
Write
A-Bank
Read
A-Bank
DQS/DQS
> = tRCD
DQ
WL = RL -1 = 4
CL = 3
AL = 2
RL = AL + CL = 5
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
> = tRAC
10
CK/CK
AL = 0
CMD
DQS/DQS
DQ
Active
A-Bank
Write
A-Bank
Read
A-Bank
WL = RL -1 = 2
CL = 3
> = tRCD
RL = AL + CL = 3
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
> = tRAC
20
000
0, 1, 2, 3
0, 1, 2, 3
001
1, 2, 3, 0
1, 0, 3, 2
010
2, 3, 0, 1
2, 3, 0, 1
011
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
21
tCL
CK
CK
CK
DQS
DQS/DQS
DQS
tRPST
tRPRE
DQ
tDQSQmax
tDQSQmax
tQH
tQH
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS/DQS
AL = 2
CL =3
RL = 5
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
READ A
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS/DQS
CL =3
RL = 3
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
T1
Tn-1
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
NOP
NOP
NOP
NOP
CK/CK
CMD
Post CAS
READ A
NOP
Post CAS
NOP
WRITE A
tRTW (Read to Write turn around time)
NOP
DQS/DQS
RL =5
WL = RL - 1 = 4
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DIN A0
DIN A1
DIN A2
DIN A3
The minimum time from the burst read command to the burst write command is defined by a read-to-writeturn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
23
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Post CAS
READ A
NOP
Post CAS
READ B
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
CL =3
AL = 2
RL = 5
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT B0
DOUT B1
DOUT B2
24
CK/CK
CMD
Read A
NOP
Read B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Note
1.
2.
3.
4.
5.
6.
7.
Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or
Precharge command is prohibited.
Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt
timings are prohibited.
Read burst interruption is allowed to any bank inside DRAM.
Read burst with Auto Precharge enabled is not allowed to interrupt.
Read burst interruption is allowed by another Read with Auto Precharge command.
All command timings are referenced to burst length set in the mode register. They are not referenced to actual
burst. For example, Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the mode
register and not the actual burst (which is shorter because of interrupt).
Figure 23. Read burst interrupt timing example: (CL=3, AL=0, RL=3, BL=8)
25
DQS
DQS/
DQS
tDQSL
tDS
DQS
tWPRE
tWPST
VIH(ac)
DQ
VIH(dc)
DM
DMin
tDH
tDH
tDS
tDS
VIL(dc)
VIL(ac)
VIH(ac)
VIH(dc)
DMin
DMin
DMin
VIL(dc)
VIL(ac)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CK/CK
CAS
CMD Posted
WRITE A
NOP
NOP
NOP
NOP
tDQSS
NOP
tDSS tDQSS
NOP
NOP
Precharge
tDSS Completion of
the Burst Write
DQS/DQS
> = WR
WL = RL - 1 = 4
DQs
DIN A0
DIN A1
tDQSS tDSH
DIN A2
DIN A3
tDQSStDSH
DQS/DQS
WL = RL - 1 = 4
DQs
> = WR
DIN A0
DIN A1
DIN A2
DIN A3
T0
T1
T2
T3
T4
T5
Tm
Tm+1
Tn
CK/CK
WRITE A
CMD
NOP
NOP
NOP
NOP
NOP
Precharge
NOP
Completion of
the Burst Write
< = tDQSS
Bank A
Activate
DQS/
DQS
WL = RL - 1 = 2
> = WR
DQs
DIN A0
DIN A1
DIN A2
> = tRP
DIN A3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK/CK
Write to Read = CL - 1 + BL/2 + tWTR
CMD
NOP
NOP
NOP
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
DQS
DQS/
DQS
DQS
CL = 3
AL = 2
WL = RL - 1 = 4
RL =5
> = tWTR
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DOUT
The minimum number of clock from the burst write command to the burst read command is [CL - 1 + BL/2 +
tWTR]. This tWTR is not a write recovery time (WR) but the time required to transfer the 4bit write data from
the input buffer into sense amplifiers in the array. tWTR is defined in AC spec table of this data sheet.
Figure 27. Burst write followed by burst read: RL = 5 (AL=2, CL=3), WL = 4, tWTR = 2, BL = 4
27
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Post CAS
Write A
NOP
Post CAS
Write B
DQS/
DQS
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
WL = RL - 1 = 4
DQs
DIN A0
DIN A1
DIN A2
DIN A3
DIN B0
DIN B1
DIN B2
DIN B3
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4
operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated
28
CK/CK
CMD
NOP
Write A
NOP
NOP
Write B
NOP
NOP
NOP
NOP
NOP
DQS/DQS
DQs
A0
A1
A2
A3
B0
B1
B2
B3
B4
B5
B6
B7
Notes:
1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read
command or Precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with Auto Precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another Write with Auto Precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, minimum Write to Precharge timing is WL+BL/2+WR where WR starts with
the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Figure 29. Write Burst Interrupt Timing Example: (CL=3, AL=0, RL=3, WL=2, BL=8)
29
DM
VIH(ac) VIH(dc)
VIH(ac) V (dc)
IH
VIL(dc)
VIH(ac) VIL(dc)
VIL(ac)
tDS tDH
tDS tDH
Write
WL
tWR
tDQSS
DQS/DQS
DQ
DM
Case 2 : max tDQSS
tDQSS
DQS/DQS
DQ
DM
30
A10
BA2
BA1
BA0
Precharged Bank(s)
LOW
LOW
LOW
LOW
Bank 0 only
Remarks
LOW
LOW
LOW
HIGH
Bank 1 only
LOW
LOW
HIGH
LOW
Bank 2 only
LOW
LOW
HIGH
HIGH
Bank 3 only
LOW
HIGH
LOW
LOW
Bank 4 only
LOW
HIGH
LOW
HIGH
Bank 5 only
LOW
HIGH
HIGH
LOW
Bank 6 only
LOW
HIGH
HIGH
HIGH
Bank 7only
HIGH
DONT CARE
DONT CARE
DONT CARE
All Banks
31
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Bank A
Active
NOP
CK/CK
CMD
Post CAS
READ A
NOP
NOP
Precharge
NOP
NOP
AL + BL/2 clks
DQS/DQS
> = tRP
CL = 3
AL = 1
RL =4
DQs
DOUT A0
> = tRAS
DOUT A1
DOUT A2
DOUT A3
CL =3
> = tRTP
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
CK/CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
Precharge A
AL + BL/2 clks
DQS/DQS
CL = 3
AL = 1
RL =4
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
> = tRTP
first 4-bit prefetch
32
T0
T1
T2
T3
T4
T5
T6
T7
T8
Bank A
Activate
NOP
CK/CK
CMD
Posted CAS
READ A
NOP
NOP
NOP
Precharge A
NOP
NOP
AL + BL/2 clks
DQS/DQS
> = tRP
CL =3
AL = 2
RL =5
DQs
DOUT A0
> = tRAS
DOUT A1
DOUT A2
DOUT A3
CL =3
> = tRTP
T0
T1
T2
T3
T4
T5
T6
T7
T8
Bank A
Activate
NOP
CK/CK
CMD
Post CAS
READ A
NOP
NOP
NOP
Precharge A
NOP
NOP
AL + BL/2 Clks
DQS/DQS
> = tRP
AL = 2
CL =4
RL = 6
DQs
DOUT A0
> = tRAS
DOUT A1
DOUT A2
DOUT A3
CL =4
> = tRTP
33
T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
Bank A
Activate
CK/CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
NOP
Precharge A
DQS/DQS
> = tRP
CL =4
AL = 0
RL = 4
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
> = tRAS
> = tRTP
first 4-bit prefetch
34
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
> = tWR
DQS/DQS
WL = 3
DQs
DIN A0
DIN A1
DIN A2
DIN A3
T0
T1
T2
T3
T4
T5
T6
T7
T9
CK/CK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
> = WR
DQS/DQS
WL = 4
DQs
DIN A0
DIN A1
DIN A2
DIN A3
35
If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The
DDR2 SDRAM starts an Auto Precharge operation on the rising edge which is (AL + BL/2) cycles later than
the read with AP command if tRAS(min) and tRTP(min) are satisfied.
If tRAS(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRAS(min) is satisfied.
If tRTP(min) is not satisfied at the edge, the start point of auto-precharge operation will be delayed until
tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where tRTP ends(not at the next
rising clock edge after this event). So for BL = 4 the minimum time from Read_AP to the next Activate command becomes AL + {(tRTP + tRP)/ tCK}* (see example 2) for BL = 8 the time from Read_AP to the next Activate is AL + 2 + {(tRTP + tRP)/tCK}*, where * means: rounded up to the next integer. These equations
change to AL + {tRTP + tRP)/tCK(avg)}*and AL + 2 +{tRTP + tRP)/tCK(avg)}*, respectively, for DDR2667/800. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank activate (command) may be issued to the same bank if the following two conditions are satisfied
simultaneously.
(1) The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
36
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
T8
CK/CK
Post CAS
CMD
NOP
READ A
NOP
NOP
NOP
Bank A
Activate
Autoprecharge
AL + BL/2 clks
> = tRP
DQS/DQS
CL = 3
AL = 1
RL =4
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
> = tRTP
second 4-bit prefetch
tRTP
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
Bank A
Activate
NOP
CK/CK
CMD
Post CAS
READ A
NOP
NOP
NOP
NOP
Autoprecharge
DQS/DQS
CL = 3
AL = 1
RL =4
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
4-bit prefetch
tRTP
tRP
37
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
A10 = 1
CMD
Post CAS
READ A
NOP
NOP
NOP
> = tRAS(min)
NOP
NOP
NOP
NOP
Bank A
Activate
DQS/DQS
> = tRP
AL = 2
CL =3
RL = 5
DQs
DOUT A0
DOUT A1
DOUT A2
DOUT A3
CL =3
> = tRC
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
A10 = 1
CMD
Post CAS
READ A
NOP
NOP
NOP
> = tRAS(min)
NOP
NOP
Bank A
Activate
NOP
NOP
DQS/DQS
> = tRP
AL = 2
CL =3
RL = 5
DQs
DOUT A0
> = tRC
DOUT A1
DOUT A2
DOUT A3
CL =3
38
T0
T1
T2
T3
T4
T5
T6
T7
Tm
CK/CK
A10 = 1
Post CAS
CMD WRA
BankA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A
Active
DQS/DQS
DQs
> = tRP
> = WR
WL =RL - 1 = 2
DIN A0
DIN A1
DIN A2
DIN A3
> = tRC
T3
T4
T5
T6
T7
T8
T9
T12
CK/CK
A10 = 1
Post CAS
CMD WRA
Bank A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Bank A
Active
DQS/DQS
> = WR
WL =RL - 1 = 4
DQs
DIN A0
DIN A1
DIN A2
> = tRP
DIN A3
> = tRC
Figure 43. Burst Write with Auto-Precharge (WR + tRP):
WL = 4, WR =2, BL = 4, tRP=3
39
Read w/AP
Write
Write w/AP
Precharge
Precharge All
To Command
Unit
Notes
AL + BL/2 + max(RTP,2) - 2
clks
1,2
Precharge All
AL + BL/2 + max(RTP,2) - 2
clks
1,2
AL + BL/2 + max(RTP,2) - 2
clks
1,2
Precharge All
AL + BL/2 + max(RTP,2) - 2
clks
1,2
WL + BL/2 + WR
clks
Precharge All
WL + BL/2 + WR
clks
WL + BL/2 + WR
clks
Precharge All
WL + BL/2 + WR
clks
clks
Precharge All
clks
Precharge
clks
Precharge All
clks
Note 1: RTP[cycles] = RU{tRTP(ns)/tCK(ns)}, where RU stands for round up. tCK(avg) should be used in
place of tCK for DDR2-667/800.
Note 2: For a given bank, the precharge period should be counted from the latest precharge command, either
one bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP or tRPall
(=tRP for 4 bank device, = tRP +1*tCK for 8 bank device) depending on the latest precharge command
issued to that bank
Table 5. Precharge & auto precharge clarification
.
T1
T2
T3
Tm
Tn
Tn + 1
CK/CK
HIGH
CKE
CMD
Precharge
NOP
> = tRFC
> = tRFC
> = tRP
REF
NOP
REF
NOP
ANY
41
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
tCK
tCH tCL
CK
CK
> = tXSNR
tRP*
> = tXSRD
CKE
VIH(ac)
VIL(ac)
tIS
tIS
tAOFD
ODT
VIL(ac)
tIH
tIS
tIS
tIH
tIS tIH
VIL(ac)
CMD
VIL(ac)
VIH(dc)
Self
Refresh
NOP
NOP
NOP
Valid
VIL(dc)
- Device must be in the All banks idle state prior to entering Self Refresh mode.
- ODT must be turned off tAOFD before entering Self Refresh mode, and can be turned on again
when tXSRD timing is satisfied.
- tXSRD is applied for a Read or a Read with autoprecharge command
- tXSNR is applied for any command except a Read or a Read with autoprecharge command.
Figure 45. Self refresh operation
42
tIH
tIS
tIH
tIS
tIS tIH
CKE
Command
VALID
NOP
NOP
NOP
tCKE(min)
VALID
VALID
or NOP
tXP, tXARD
tXARDS
tCKE(min)
Exit Power-Down mode
Dont Care
Figure 46. Basic power down entry and exit timing diagram
43
T1
T2
Tx
Tx+ 1
Tx+ 2
Tx+ 3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK
CK
CMD
RD
BL=4
CKE
AL + CL
DQ
tI S
DQS
DQS
T0
CMD
T1
T2
Tx
Tx+1
Tx+2
Tx+3
RD
Tx+4
Tx+5
Tx+6
Tx+7
Tx+ 8
Tx+ 9
BL=8
CKE
tIS
AL + CL
DQ
DQS
DQS
T1
T2
Tx
Tx +1
Tx +2
Tx+3
Tx +4
Tx +5
Tx +6
T x+7
T x+8
T x+9
CK
CK
CM D
RDA
P RE
BL=4
AL + BL/2
with tRT P = 7.5ns
& tRA S min satisfied
CKE
AL + CL
DQ
t IS
DQS
D QS
T0
T1
T2
Tx
T x+ 1
T x+ 2
T x+ 3
T x+ 4
T x+5
T x+6
Tx +7
Tx +8
Tx +9
RDA
BL=8
AL + BL/2
with tRT P = 7.5ns
& tRAS m in s atisfied
PRE
CKE
AL + CL
DQ
tIS
DQS
DQS
44
T1
Tm
Tm+1
Tm+2
Tm+3
Tx
Tx+1
Tx+2
Ty
Ty+1
Ty+2
Ty+3
Tx
Tx+1
Tx+2
Tx+3
Tx+4
T x+3
Tx +4
Tx +5
Tx +6
T x+1
Tx +2
Tx +3
Tx +4
CK
CK
CMD
WR
BL=4
CKE
WL
tIS
DQ
D
tWTR
DQS
DQS
T0
CMD
T1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
WR
BL=8
CKE
WL
t IS
DQ
D
tWTR
DQS
DQS
T1
Tm
T m+ 1
T m+ 2
T m+ 3
Tx
T x+ 1
T x+2
CK
CK
CM D
WR A
P RE
BL =4
CK E
WL
tI S
DQ
D
W R *1
DQ S
DQ S
T0
T1
Tm
T m+ 1
T m+ 2
T m+ 3
T m+ 4
T m+ 5
Tx
CK
CK
S ta rt Int e rn al P re c h arg e
CM D
WR A
P RE
B L =8
CK E
WL
t IS
DQ
D
WR * 1
DQ S
D QS
* 1: WR is programmed through MR
45
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
CK
CMD
REF
CMD
ACT
CMD
PR or
PRA
CKE can go to LOW one clock after a Precharge or Precharge all command
CKE
tIS
CMD
MR or
EMR
CKE
tIS
tMRD
46
Stable clocks
tCK
CK#
CK
CKE
tDelay
tIS
47
T0
T1
T2
NOP
NOP
T4
Tx
Tx+1
Ty
Ty+1
Ty+2
Ty+3
Ty+4
Tz
CK
CK
CMD
CKE
NOP
NOP
Frequency Change
Occurs here
NOP
Valid
200 Clocks
tIS
tIS
ODT
DLL
RESET
tRP
tIH
tXP
tAOFD
Minmum 2 clocks
required before
changing frequency
48
49
2. Truth Tables
2.1 Command truth table.
CKE
Function
CS
RAS
CAS
WE
BA0
BA1
BA2
A15-A11
A10
A9 - A0
Notes
Previous
Cycle
Current
Cycle
BA
Refresh (REF)
1,7
OP Code
1,2
BA
1,2
Bank Activate
BA
Write
BA
Column
Column
1,2,3,
BA
Column
Column
1,2,3,
Read
BA
Column
Column
1,2,3
BA
Column
Column
1,2,3
No Operation
Device Deselect
1,4
X
X
1,4
Row Address
1,2
1. All DDR2 SDRAM commands are defined by states of CS, RAS, CAS , WE and CKE at the rising edge of the clock.
2. Bank addesses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MR BA selects an (Extended) Mode
Register.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" in section 1.4 for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh
requirements outlined in section 1.2.2.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See
section 1.2.2.4.
6. X means H or L (but a defined logic level).
7. Self refresh exit is asynchronous.
8. VREF must be maintained during Self Refresh operation
50
Command (N) 3
Action (N) 3
Notes
Maintain Power-Down
11, 13, 15
DESELECT or NOP
4, 8, 11,13
11, 15
DESELECT or NOP
4, 5,9,16
DESELECT or NOP
4,8,10,11,13
DESELECT or NOP
4, 8, 10,11,13
REFRESH
6, 9, 11,13
Previous Cycle 1
(N-1)
Current Cycle 1
(N)
Power Down
Self Refresh
Bank(s) Active
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may
be issued only after tXSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register operations or Precharge operations
are in progress. See section 1.8 "Power Down" and 1.7.2 "Self Refresh Command" for a detailed list of restrictions.
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire
time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period
of tIS + 2*tCKE + tIH.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. See section 1.2.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 1.2.2.
14. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode .
15. X means dont care (including floating around VREF) in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power
Down if the ODT fucntion is enabled (Bit A2 or A6 set to 1 in EMR(1) ).
16. VREF must be maintained during Self Refresh operation.
DM
DQs
Note
Write enable
Valid
Write inhibit
1. Used to mask write data, provided coincident with the corresponding data
51
3. Maximum DC Ratings
Rating
Units
Notes
- 1.0 V ~ 2.3 V
1,3
VDDQ
- 0.5 V ~ 2.3 V
1,3
VDDL
- 0.5 V ~ 2.3 V
1,3
- 0.5 V ~ 2.3 V
-55 to +100
1, 2
VDD
VIN, VOUT
TSTG
Parameter
Storage Temperature
1.Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions. Please
refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6xVDDQ. When VDD and
VDDQ and VDDL are less than 500mV, Vref may be equal to or less than 300mV.
Parameter
Operating Temperature
Rating
Units
Notes
0 to 85
1,2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature
rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During
operation, the DRAM case temperature must be maintained between 0 ~ 85C under all other specification parameters. However,
in some applications, it is desirable to operate the DRAM up to 95C case temperature. Therefore 2 spec options may exist.
1) Supporting 0 - 85C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature
options.
2) Supporting 0 - 85C and being able to extend to 95C with doubling auto-refresh commands in frequency to a 32 ms
period(tRFI=3.9us).
Note; Currently the periodic Self-Refresh interval is hard coded within the DRAM to a specificic value.
There is a migration plan to support higher temperature Self-Refresh entry via the control of EMR(2) bit A7. However, since
Self-Refresh control function is a migrated process. For our DDR2 module user, it is imperative to check SPD Byte 49 Bit 0
to ensure the DRAM parts support higer than 85C case temperature Self-Refresh entry.
1) if SPD Byte 49 Bit 0 is a 0 means DRAM does not support Self-Refresh at higher than 85C, then system have to ensure
the DRAM is at or below 85C case temperature before initiating Self-Refresh operation.
2) if SPD Byte 49 Bit 0 is a 1 means DRAM supports Self-Refresh at higher than 85C case temperature, then system can
use register bit A7 at EMR(2) control DRAM to operate at proper Self-Refresh rate for higher temperature. Please also
refer to EMR(2) register definition section and DDR2 DIMM SPD definition for details.
52
Parameter
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
1.7
1.8
1.9
VDDL
1.7
1.8
1.9
VDDQ
1.7
1.8
1.9
1,5
VREF
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
2,3
Termination Voltage
VREF-0.04
VREF
VREF+0.04
VTT
1. There is no specific device VDD supply voltage requirement SSTL-1.8 compliance. However under all conditions VDDQ must be
less than or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
4. VTT of transmitting device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
SYMBOL
MIN
NOM
MAX
Rtt1(eff)
Rtt2(eff)
Rtt2(eff)
VM
60
120
40
-6
75
150
50
90
180
60
+6
UNITS NOTES
1
1
1,2
1
Note
1. Test condition for Rtt measurements
2. Optional for DDR2-400/533/667, mandatory for DDR2-800/1066.
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I( VIL (ac))
respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
Rtt(eff) =
Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
VM =
2 x Vm
VDDQ
-1
x 100%
53
Parameter
Min.
Max.
Units
VIH(dc)
VREF + 0.125
VDDQ + 0.3
VIL(dc)
- 0.3
VREF - 0.125
Notes
DDR2-400, DDR2-533
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
VREF + 0.200
VREF - 0.200
VIH (ac)
VREF + 0.250
VIL (ac)
VREF - 0.250
Notes:
1. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot adn undershoot.
Condition
Value
Units
Notes
VREF
0.5 * VDDQ
VSWING(MAX)
1.0
SLEW
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the range
from VREF min to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on
the negative transitions.
Table 15. AC input test conditions
VDDQ
VIH(ac) min
VIH(dc) min
VSWING(MAX)
VREF
VIL(dc) max
VIL(ac) max
TF
Falling Slew =
VSS
TR
Rising Slew =
VIH(ac)min - VREF
TR
Parameter
VID (ac)
VIX (ac)
Min.
Max.
Units
Notes
0.5
VDDQ
1,3
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
3. Refer to Overshoot/undershoot specifications for Vpeak value: maximum peak amplitude allowed for overshoot adn undershoot.
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,
LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)
- V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
Parameter
ac differential cross point voltage
Min.
Max.
Units
Notes
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
55
Parameter
DDR2-400
DDR2-533
DDR2-667
DDR2-800
DDR2-1066
Maximum peak amplitude allowed for overshoot area (See Figure 1):
0.5V
0.5V
0.5V
0.5V
0.5V
Maximum peak amplitude allowed for undershoot area (See Figure 1):
0.5V
0.5V
0.5V
0.5V
0.5V
1.33 V-ns
1.0 V-ns
0.8V-ns
0.66V-ns
0.66V-ns
1.33 V-ns
1.0 V-ns
0.8V-ns
0.66V-ns
0.66V-ns
V o lts
(V )
V DD
VS S
U n d e rs h o o t A re a
M a x im u m A m p litu d e
T im e (n s )
Figure 59. AC overshoot and undershoot definition for address and control pins
Specification
Parameter
DDR2- 400
DDR2-533
DDR2-667
DDR2-800
Maximum peak amplitude allowed for overshoot area (See Figure 2):
0.5V
0.5V
0.5V
0.5V
DDR2-1066
0.5V
Maximum peak amplitude allowed for undershoot area (See Figure 2):
0.5V
0.5V
0.5V
0.5V
0.5V
0.38 V-ns
0.28 V-ns
0.23 V-ns
0.23 V-ns
0.23 V-ns
0.38 V-ns
0.28 V-ns
0.23 V-ns
0.23 V-ns
0.23 V-ns
Table 18. AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins:
DQ, (U/L/R)DQS, (U/L/R)DQS, DM, CK, CK
M a xim u m A m p litu d e
O v e rs h o o t A re a
V o lts
(V )
V DDQ
V SSQ
U n d e rs h o o t A re a
M a x im u m A m p litu d e
T im e (n s)
Figure 60. AC overshoot and undershoot definition for clock, data, strobe, and mask pinsns
56
Voltage across
clamp(V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.1
0.1
0.9
1.0
1.0
1.0
2.5
2.5
1.1
4.7
4.7
1.2
6.8
6.8
1.3
9.1
9.1
1.4
11.0
11.0
1.5
13.5
13.5
1.6
16.0
16.0
1.7
18.2
18.2
1.8
21.0
21.0
Table 19. V-I Characteristics table for input only pins with clamps
57
Parameter
Output Timing Measurement Reference Level
SSTL_18 Class II
Units
Notes
0.5 * VDDQ
1.
2.
3.
4.
Parameter
IOH(dc)
IOL(dc)
SSTl_18
Units
Notes
- 13.4
mA
1, 3, 4
13.4
mA
2, 3, 4
VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 for values of VOUT between VDDQ and VDDQ - 280
mV.
VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 for values of VOUT between 0 V and 280 mV.
The dc value of VREF applied to the receiving device is set to VTT
The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current
capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 load line to define a
convenient driver current for measurement.
58
Parameter
Output impedance
Min
Nom
Max
Unit
Notes
12.6
18
23.4
1,2
1.5
1,2,3
V/ns
1,4,5,6,7,8
Sout
1.5
Note:
1. Absolute Specifications (0C TCASE +tbdC; VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V)
2 Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less
than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink dc current:
VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC.
This is guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 at nominal conditions across all process corners/variations and represents
only the DRAM uncertainty. A 0 value(no calibration) can only be achieved if the OCD impedance is 18 +/- 0.75 under nominal
conditions.
7. DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS
specification.
9. DDR2 SDRAM output slew rate test load is defined in General Note 3 of the AC Timing specification Table in Hynix DDR2 SDRAM
component datasheet.
59
Minimum
(23.4 Ohms)
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Maximum
(12.6 Ohms)
0.2
8.5
11.3
11.8
15.9
0.3
0.4
0.5
12.1
14.7
16.4
16.5
21.2
25.0
16.8
22.1
27.6
23.8
31.8
39.7
0.6
0.7
0.8
0.9
17.8
18.6
19.0
19.3
28.3
30.9
33.0
34.5
32.4
36.9
40.9
44.6
47.7
55.0
62.3
69.4
1.0
1.1
19.7
19.9
1.2
20.0
20.1
20.2
20.3
35.5
36.1
36.6
36.9
37.1
37.4
47.7
50.4
52.6
75.3
80.5
84.6
54.2
55.9
87.7
90.8
57.1
58.4
59.6
60.9
92.9
94.9
97.0
99.1
101.1
Voltage (V)
1.3
1.4
1.5
20.4
20.6
1.6
1.7
1.8
1.9
37.6
37.7
37.9
120
100
Maximum
80
Nominal
Default
High
60
Nominal
Default
Low
40
20
Minimum
0
0.2
0.4
0.3
0.6
0.5
0.8
0.7
1.0
0.9
1.2
1.1
1.4
1.3
1.6
1.5
1.8
1.7
1.9
60
Voltage (V)
Minimum
(23.4 Ohms)
0.2
-8.5
0.3
0.4
0.5
-12.1
-14.7
-16.4
0.6
0.7
0.8
0.9
-17.8
-18.6
-19.0
-19.3
1.0
1.1
-19.7
-19.9
1.2
-20.0
-20.1
-20.2
-20.3
-20.4
-20.6
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Nominal Default
Low (18 ohms)
Nominal Default
High (18 ohms)
Maximum
(12.6 Ohms)
-11.1
-16.0
-20.3
-24.0
-11.8
-15.9
-17.0
-22.2
-27.5
-23.8
-31.8
-39.7
-27.2
-29.8
-32.4
-36.9
-40.8
-44.5
-47.7
-55.0
-62.3
-69.4
-47.7
-50.4
-52.5
-75.3
-80.5
-84.6
-54.2
-55.9
-87.7
-90.8
-57.1
-58.4
-59.6
-60.8
-92.9
-94.9
-97.0
-99.1
-101.1
-31.9
-33.4
-34.6
-35.5
-36.2
-36.8
-37.2
-37.7
-38.0
-38.4
-38.6
Table 24. Default pullup characteristics for full strength output driver
-20
Minimum
-40
Nominal
Default
Low
-60
Nominal
Default
High
-80
-100
Maximum
-120
0.2
0.4
0.3
0.6
0.5
0.8
0.7
1.0
0.9
1.2
1.1
1.4
1.3
1.6
1.5
1.8
1.7
1.9
Voltage (V)
0.2
0.3
0.4
Nominal
Minimum
Nominal
Low
(21 ohms)
(18.75 ohms)
9.5
14.3
18.7
10.7
16.0
21.0
Nominal
(18 ohms)
11.5
16.6
21.6
Nominal
High
Nominal
Maximum
(17.25 ohms)
(15 ohms)
11.8
17.4
23.0
13.3
20.0
27.0
Voltage (V)
0.2
0.3
0.4
Nominal
Minimum
Nominal
Low
(21 ohms)
(18.75 ohms)
-9.5
-14.3
-18.7
-10.7
-16.0
-21.0
Nominal
(18 ohms)
-11.4
-16.5
-21.2
Nominal
High
Nominal
Maximum
(17.25 ohms)
(15 ohms)
-11.8
-17.4
-23.0
-13.3
-20.0
-27.0
62