Best of DesignIdeas

A SPECIAL SUPPLEMENT TO EDN
J U LY 2 0 0 4
32
VDD
ANTENNA
VDD
VDD
RadioWire RF Transceiver
Smaller Easier Better
31
30
29
28
27
26
25
24
23
22
CS
21
SCLK
20
IO
19
DATAIXO
18
DATACLK
17
MICRF505
10
11
12
13
14
15
5mm x 5mm
MLF
16
VDD
LD
RSSI
Actual Size
*Optional components
The Good Stuff
850 950MHz Operating Range

FSK Modulation
200kbps Maximum Data-Rate
Output Power Programmable to +10dBm
Integrated T/R Switch
Integrated Clock Recovery Circuit
Digital Crystal Trimming Capability
The new MICRF505 RadioWire transceiver supports data-rates

up to 200kbps at frequencies ranging from 850MHz to 950MHz.
The MICRF505 offers the highest level of integration, in the
smallest package with performance better than competing
devices.
www.micrel.com/micrf505.html
RadioWire is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology
Smaller: The MICRF505 is squeezed into the 5x5mm MLF32 (micro lead-frame) package. More importantly the MICRF505
requires just 13 external components to implement a fullfeature RF transceiver thats including the supply bypass
capacitors (not shown).
Easier: Fewer external components mean less design concerns
and greater reliability. Internal on-the-fly crystal trimming
enables the use of low-cost crystals. This eliminates the need
for expensive production tuning and further enhances reliability,
while our free design software ensures fast and easy component
selection.
Better: A better RF transceiver provides a more robust RF link

with greater range. FCC regulations allow higher power
transmission when frequency hopping. The MICRF505 has a
fully programmable PLL, making it ideally suited for frequency
hopping systems. Equally important, the MICRF505 features
excellent sensitivity and by integrating the Transmit/Receive
switch on the front-end theres no switch loss to factor in.
Literature: (800) 401-9572 Factory: 1 (408) 944-0800
Stocking Distributors: Arrow (800) 777-2776 Future (800) 388-8731
Newark (800) 463-9275 Nu Horizons (888) 747-6846
Enter 709 at www.edn.com/info
Op Amps Designed
for the Unexpected.
Ever worry about op amp performance when
temperatures reach -60C or when it soars to
+130C? We have. Our op amps are tested to deliver
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We dont overstate performance. With our data
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Performance Driven.
www.linear.com
LT, LTC and
are registered trademarks of Linear Technology Corp.
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Letter from
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The Best of
Amplifiers . . . . . . . . . p8
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Web/CPS Production Coordinator
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ADVERTISER INDEX
Analog Devices, Inc./ASC Div. ......................P9
Bourns..............................................................P13
Datel, Inc.................................................P6, P31
Digi-Key Corp ..................................................P3
Electronics Workbench ................................P43
International Rectifier........................P23, P25
Linear Technology Corp. ........P4, P15, P29,
P40, Cover 3
Maxim Integrated Products, Inc.................P27
Melexis ............................................................P34
Micrel Semiconductor ....Cover 2, Cover 4,
P11, P18, P39
MicroSemi Corp ............................................P37
National Instruments ........................P17, P45
Toshiba America ..................................P7, P21
Publish your Design Idea in EDN.

See the Whats Up section at
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The Best of
Communications . . . . p12
Grounded resistor tunes oscillator

Frequency source feeds entire lab
Category Sponsor: Bourns

One-shot provides frequency
discrimination
High-current driver serves homepower-line modems
Category Sponsors:
Datel, Inc.
Linear Technology Corp.
Switched-capacitor IC and reference form
elegant 48 to +10V converter
Buck-boost regulator suits battery operation
Dual comparator thermally protects
lithium-ion battery
Reset supervisor waits for stable supply
The Best of
Sensors . . . . . . . . . . . p35
The Best of
Controllers . . . . . . . . . p16
Circuit ensures safety in power-on
operation
Microcontroller provides SRAM
battery backup
Category Sponsor: MicroSemi Corp.

Safety device uses GMR sensor
Use a DAC to vary LVDT excitation
The Best of
Software . . . . . . . . . . p41
The Best of
Detectors . . . . . . . . . . p19
Thermal switches provide circuit
disconnect
Circuit offers improved active
rectification
The Best of
Filters . . . . . . . . . . . . . p22
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The Best of
Power . . . . . . . . . . . . p28
Category Sponsor: Analog Devices, Inc.

Bootstrapping allows single-rail op amp
to provide 0V output
Absolute-value circuit delivers
high bandwidth
Single IC provides gains
of 10 and -10
Cindy Fitzpatrick
EDN Custom Publishing Director
Phone (617) 558-4503
Fax (617) 558-4470
cfitzpatrick@reedbusiness.com
The Best of
Oscillators . . . . . . . . . . p26
Prevent instrumentation-amp
RF-rectification errors
Build an adjustable high-frequency
notch filter
Category Sponsor: Electronics Workbench

Software snippet provides improved
subset-sum algorithm
Make noise with a PIC
Code provides adjustable differential drive
for robots
The Best of
Test . . . . . . . . . . . . . p44
Category Sponsor: National Instruments
Interface a serial 12-bit ADC to a PC

High-side current sensor monitors
negative rail
J U LY 2004 | EDN B E S T
OF
D E S I G N I D E A S P5
AC
Voltmeters
Letter from
2-WIRE
the editor
Panel-Mount Models
for 85-264Vac Line
Monitor Applications
Welcome to...
DMS-20PC-LM Series
Blue LED
displays
now
available
Plug-In Models
for Standard
120Vac Outlets
DMS-20PC-LM-F Series
Easy to install/operate - only two connections

Monitor to 600Vac @ 50/60Hz or 140Vac @ 400Hz
Accuracy to 1V; 0.37" Red, Green or Blue LEDs
Epoxy construction; Screw-terminal connectors
UL, CSA and IEC1010-1 certied
iven the competitive nature of the electronics
DC
Voltmeters
industry, the Design Idea section of EDN used to puzzle
2-WIRE
me. Engineers gladly send us solutions to tricky design
problems with only the prospect of praise from their peers as

reward (and a few bucks from us).
Low Cost ($9.95*)

LCD-Display
Battery Monitors
But I get it now. I've worked side by side with engineers for
awhile, and I've come to appreciate that no one would put
DMS-20LCD-DCM Series
him/herself through the rigorous training and workloads that

*OEM Qty.
engineers handle without loving the work for itself. It's only
Easy-to-Read
Red, Blue & Green
LED Displays
natural that they want to show it off, and that's why Design Ideas
is consistently the best-read section of EDN.
DMS-20PC-DCM Series
Here, then, are our picks for some of the very best of our recent
"Self-powered" - 2 connections, no supplies

Measure inputs from +2.00Vdc to 264Vdc
Resolutions to 0.01V; Accuracies to 10mV
0.37" LED (Red, Green, Blue) or LCD displays
Epoxy construction; Screw-terminal connectors
Design Ideas. And when you visit our Web site at www.edn.com,
scroll to the What's Up section for a pdf of this supplement and
the Best of Design Ideas link, where we provide details on how
you can share your own idea with your engineering brethren.
Free CD!
But for the moment, just sit back and enjoy.
2004 DPM Catalog
Detailed Selection Guides

Easy web-browser interface
22 Application Notes & FAQ's
Fast access to 100+ data sheets
Joan Lynch,
Managing Editor, EDN
DATEL, Inc., 11 Cabot Boulevard

Manseld, MA 02048
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P6
EDN B E S T
OF
D E S I G N I D E A S | J U LY 2004
www.edn.com
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The best of
amplifiers
Bootstrapping allows single-rail op amp

to provide 0V output
Jim Williams, Linear Technology Corp, Milpitas, CA
Figure 1
5V
any single-supply-powered
applications require amplifier-output swings within 1 mVor even
submillivoltsof ground. Amplifieroutput-saturation limitations normally
preclude such operation. Figure 1s power-supply bootstrapping scheme achieves
the desired characteristics with

5V
V+
minimal parts count. IC1, a chop1k
+
10 F
IC
per-stabilized amplifier, features
LTC1150
+
_
CLOCK
a clock output. This output
Q
BAT85
OUT
V
2N3904
39k
switches Q1, providing drive to
10 F
+
the diode-capacitor charge pump.
100k
The charge pumps output feeds
IC1s V terminal, pulling it below 0V, thus permitting an output swing to and be- This configuration uses bootstrapping to allow a
Figure 2
low ground. In Figure single-rail op amp to operate at 0V output.
2, the amplifiers V pin (Trace
B) initially rises at supply turn-on but heads negative when amplifier clocking
commences at approximately midscreen.
This start-up photo shows that the amplifiers
The circuit provides a simple way to obV pin (Trace B, midscreen) goes negative
tain output swing to 0V, allowing a true
when the bootstrapping takes hold.
live-at-zero output.
A5V/DIV
B0.2V/DIV
Absolute-value circuit delivers high bandwidth

Ron Mancini, Texas Instruments, Bushnell, FL
ost absolute-value circuits
have limited bandwidth and high
component count, and they require several matched resistors. The circuit in Figure 1 uses three fewer components than most absolute-value
circuits require, and only two of the resistors must have 1% tolerance to obtain
1% accuracy. This circuits output voltage is an accurate representation of the
absolute value of the input signal, and it
is accurate for input signals containing
frequencies as high as 10 MHz. Another advantage of this circuit is that it has
a positive-voltage output, thus saving an
analog inverter in most applications.
When the input voltage is positive, the
negative output voltage of IC1 cuts off
the diode, thereby preventing signal
propagation through IC1. Virtually no
signal propagates through R2, because
the resistor connects to ac ground
through the output of IC2. The only signal path is through R3 to buffer IC2, and
the output of the buffer is a positive
P8
EDN B E S T
OF
voltage. When the

Figure 1
input voltage is
R1
R2
negative, the positive output
10k
10k
VIN
1%
1%
voltage of IC1 forward-biases
the diode, thus providing an
5V
ac short circuit for R3 to
_
R3
IC1
ground. IC2 is within IC1s
5%
TLC072
feedback loop, so the output
+
D1
voltage is positive because of
5V
SD103CCT-NO
IC1s configuration as an inverting op amp.
This design uses a dual op
+
VOUT
IC2
amp to minimize parts count.
TLC072
_
Two op amps in a feedback
loop tend to be unstable. Select
an op amp that has sufficient
phase margin to prevent oscil- This inexpensive absolute-value circuit has
lation when the input voltage is high bandwidth.
negative. The circuits dynamic
range is from the op amps input offset high-frequency TLC072 op amp with a
voltage to the maximum output voltage. fast Schottky-barrier diode. You can use
This dynamic range is from 1 mV to higher frequency op amps to obtain bet4.1V for the TLC072 with 5V power ter bandwidth results, but you must take
supplies. The excellent bandwidth per- care in the op-amp selection to avoid osformance results from combining the cillation or reduced dynamic range.
www.edn.com
New op amp delivers the lowest errors for

highest speed, highest resolution systems.
From the world leader in amplifier technology
AD8099
Performance ...
Ultralow noise: 0.95 nV/Hz, 2.6 pA/Hz
Ultralow distortion
2nd harmonic: 1 k load, 116 dB @ 1 MHz,
92 dB @ 10 MHz,
3rd harmonic: 1 k load, 117 dB @ 1 MHz,
105 dB @ 10 MHz
High speed: 700 MHz (G = +2),
550 MHz (G = +10), 1350 V/s (G = +10)
Offset voltage: 0.5 mV
Low power: 15 mA
... where it matters
ADC preamps
Receivers
Instrumentation
IF and baseband amplifiers
Filters
The ideal amplifier for 16-bit and 18-bit systems

No other op amp can deliver the low noise and low-gain stability of the
new AD8099the specs that make it ideal for 16-bit and higher systems.
But this high performance, high speed amp also offers very low voltage
offset, bias current, and uses only 15 mA of supply current. Its a
breakthrough combination of specs and features unmatched anywhere
else in the industry, and its only available from Analog Devices. For more
information, or to order free samples, please visit our website.
To view the data sheet,

or order a sample, visit
www.analog.com/lowlowamp.
www.analog.com/lowlowamp
THE LEADER IN HIGH PERFORMANCE ANALOG
The best of
amplifiers
Single IC provides gains of 10 and 10

Moshe Gerstenhaber and Charles Kitchin, Analog Devices, Wilmington, MA
lowed by an uncommitted buffer amplifier, A2. You can configure it to provide
different gains by strapping or grounding the appropriate pins.
For a gain of 10, the input signal connects between the VREF pin (Pin 3) and
ground, instead of to the op amps inputs. With the input tied to the VREF pin,
the voltage at the noninverting input of
A1 equals VIN(100 k/110 k), or
VIN(10/11). The inverting input of A2
(Pin 6) is grounded; therefore, feedback
from the output of A2 forces the noninverting input of A2 to be 0V. The output
of A1 must then also be at 0V. The voltage on the inverting input of A1 must be
equal to the voltage on the noninverting
input of A1, so both equal VIN(10/11).
Thus, the output voltage of A2, VOUT,
equals
The companion circuit of Figure 2

provides a gain of 10. This time, the input connects between the inverting input
of A2 (Pin 6) and ground.Operation is similar to that of Figure 1, but A2 now inverts
the input signal by 180. With the VREF pin
grounded, the noninverting input of A1 is
at 0V, so feedback forces the inverting input of A1 to 0V as well. Because A1 operates at a gain of 0.1, the output of A2 necessary to force the inverting input of A1 to
0V is 10VIN.The two connections exhibit
different input impedances. When you
drive the VREF input (Pin 3) for a gain of 10,
the input impedance to ground is 110 k;
it is approximately 50 G when you drive
the noninverting input of A2 (Pin 6) for a
gain of 10.All resistors are internal to the
gain block, so both accuracy and drift are
excellent. These circuits have gain accuracy better than 0.1%, with a gain tempera10 100k
ture coefficient lower than 5 ppm/C. The
VOUT = VIN 1 +
3-dB bandwidth is approximately 110

11
10k
kHz with a 10-mV input and 95 kHz with
10
= VIN 11 = 10 VIN ,
a 100-mV input. Although 15V supplies
11
are appropriate,you may operate these cirproviding a precise gain of 10 with no cuits with dual supplies from 2.25V to
external components.
18V.
eal-world data-acquisition
systems require amplifying weak
signals to match the full-scale input
range of an A/D converter. Unfortunately, when you configure them as gain
blocks, most common amplifiers have
both gain errors and offset drift. The
typical two-resistor gain-setting arrangement found in many op-amp circuits has serious accuracy and drift limitations. With standard 1% resistors, the
circuit gain can be off by as much as 2%.
Also, the gain can vary with temperature,
because each resistor drifts differently.
You can use monolithic resistor networks for precise gain setting, but these
components are expensive and consume
valuable pc-board space. The circuits of
figures 1 and 2 offer improved performance and lower cost; they are also
smaller. The single-SOIC approach is
the smallest available for this function,
and the circuits require no external components. Figure 1 shows an AD628 precision gain block connected to provide
a voltage gain of 10. The gain block itself comprises two internal amplifiers: a
gain-of-0.1 difference amplifier, A1, fol-
15V
15V
0.1 F
Figure 1
0.1 F
Figure 2
7 VS
8 100k
1 100k
7 VS
10k
AD628
IN
+IN
8 100k
10k
A1
+IN
IN
A2
VOUT
1 100k
10k
0.1 F
VIN
This circuit has a precise gain of 10 and uses no

external components.
P10
EDN B E S T
OF
+IN
A1
10k
+IN
IN
VREF 3
RG 6
VG 2
15V
AD628
IN
A2
VOUT
10k
VREF 3
0.1 F
10k
RG 6
VG 2
15V
VIN
This companion circuit to the one in Figure 1 delivers an

accurate gain of 10.
www.edn.com
Lowest Jitter, Multi-Channel Programmable

Clock Dividers Eliminate Zero Delay PLLs
<10psPK-PK Total Jitter, <30ps Bank-to-Bank offset
n
uatio
Eval rd
Boa le!
lab
Avai
The Good Stuff
Optimized for high-speed, low-jitter applications, the

SY8987x family features a pass-through bank and a divided
output bank with matched phase relationship, thus
eliminating trace-length delay matching or PLL-based zerodelay buffers. Output options include LVPECL and LVDS with
the fastest rise/fall times in the industry. The result is a
programmable output divider family with internal termination
in an extremely small 3mm x 3mm MLF package.
Guaranteed AC Performance
FMAX >2.5GHz
<15ps within-device skew
<10psPK-PK total jitter
Unique input interfaces to any differential signal
Low-voltage operation: 2.5V & 3.3V
Output options: LVPECL, LVDS
Industrial temperature range: 40C to +85C
Choose the Ideal Clock Divider and Improve Signal Integrity

Part No.
Fmax
(GHz)
SY89871U
>2.5
SY89872U
>2.0
SY89873L
>2.0
SY89874U
SY89875U
SY89876L
>2.5
>2.0
>2.0
Divider
Options
Bank A: Pass-thru
Bank B: 2, 4, 8, 16
Bank A: Pass-thru
Bank B: 2, 4, 8, 16
Bank A: Pass-thru
Bank B: 2, 4, 8, 16
1, 2, 4, 8, 16
1, 2, 4, 8, 16
1, 2, 4, 8, 16
Output
Output
Tr/Tf (ps)
Total Jitter1
(psPK-PK)
Supply
Voltage
LVPECL
<250
<10
2.5V, 3.3V
LVDS
<200
<10
2.5V
LVDS
<190
<10
3.3V
LVPECL
LVDS
LVDS
<250
<200
<190
<10
<10
<10
2.5V, 3.3V
2.5V
3.3V
1 TJ defined: with an ideal clock source of frequency fmax, no more than one output edge in 1012 edges will deviate by more than the specified peak-to-peak jitter value.
Applications Support: (408) 955-1690 hbwhelp@micrel.com

Factory: 1 (408) 944-0800
www.micrel.com
The best of
communications
One-shot provides frequency discrimination

Victor Aksenenka, CSRI Elektropribor, St Petersburg, Russia
ou use a frequency discriminator
to compare one signal frequency
with another one. A functional feature, retriggering, of a monostable, oneshot 74xx123 multivibrator can yield frequency discrimination. Figure 1 shows
a frequency discriminator that deter-
the interval tW. The same pulse

Figure 3
edge sets the 74xx174 flip-flop
to the same state as the output of the
VOUT
one-shot. If the interval between pulses
is longer than tW, the next pulse arrives
Q1
after the one-shot returns to its initial
state. The one-shots output is low, and
The output of the exclusive-OR

circuit in Figure 2 is high only
when the input frequency is
between defined limits.
Q2
Figure 1
3
R1
10k
Q 13
2 D
fIN
IC1
Q
74LS123
R/C
3 C
14
fRL
5V
1,4 R,S
5V
Q3
IC2
74LS74
R1
10k
15
R3
10k
C1
5100 pF
5V
This simple circuit can reveal whether an input frequency is above or below a reference frequency.
mines the relation of input-pulse frequency to a reference frequency. The external components, R1 and C1, set the
reference frequency. These values determine the 74xx123s reference frequency
as follows: fR1/tW, and tWkR1C1. The
multiplication factor k depends on C1s
value and the power-supply voltage. The
rising edge of the input pulse starts the
one-shot, whose output switches high for
fIN
2
1
3
Figure 2
R1
10k
the rising edge of the input pulse sets the

flip-flop low. The low flip-flop output
indicates that the input-pulse frequency,
fIN, is lower than fR.
If the interval between input pulses is
shorter than tW, the next pulse arrives before the one-shot completes its cycle and
returns to its initial state. The one-shots
output is high, and the rising edge of the
input pulse sets the flip-flop high. A high
D
R/C
ICIA C
74LS123
13
4
15
R3
10k
14
C1
3
1,4
5V
Q1
R5
10k
5100 pF
1
5V
5V
10
9 D
11
R2
10k
R/C
ICIB C
74LS123
5V
Q 12
7
6
12
11
R4
30k
C2
fIN
flip-flop output indicates that the inputpulse frequency, fIN, is higher than fR.
Doubling the circuit in Figure 1 implements frequency discrimination with a
window characteristic (Figure 2). Two
pairs of R and C values determine the
lower and upper reference frequencies.
An exclusive-OR circuit takes the outputs
of the upper and lower flip-flops. The exclusive ORs output is high when fIN is between fRL and fRH. When fIN is outside the
frequency band fRL to fRH the exclusive
ORs output is low. Figure 3 shows the
frequency-discrimination characteristic.
With R and C values as in Figure 2, and
the use of a 74LS123 one-shot, fRL16
kHz, and fRH46 kHz. Other types of
one-shots could produce different results.
D IC2A Q
74LS74
C
R,S
fRH
10,13
5V
D IC2B Q
74LS74
C
R,S
IC3
74LS86
Q3
Q2
R6
10k
5100 pF
5V
Doubling the circuit in Figure 1 and using an exclusive-OR circuit results in a window discriminator.
P12
EDN B E S T
OF
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Trim your sails according to the winds.
Smooth sailing with Bourns 3223

With sealed construction, Model 3223 was designed to withstand today's typical board processes
such as IR, Forced Hot Air or Convection solder reflow. Key features of the Model 3223 are:
vertical adjustment, pick and place centering design with flush adjustment, surface mount,
3 mm size, and 11 turns. Recommended solder processing specifications are available upon
request or may be found on our website at www.bourns.com.
Europe: e-mail: euro.marcom@bourns.com Phone: +41-41-768 55 55 Fax: +41-41-768 55 10 www.bourns.com
The best of
communications
High-current driver serves

home-power-line modems
0.1 F
RG
205
0.1 F
49.9
8
IN2
Ryan Metivier, Analog Devices, Wilmington, MA

o m e - ba s e d p ower- l i n e networking signals are similar to xDSL
signals in that they both typically
employ a form of OFDM. Both applications require high output current, wide
bandwidth, and good linearity. This Design Idea describes a simple line-driver
circuit, designed with an xDSL driver, to
drive high-speed data over a home power line. Figure 1 shows the AD8391 current-feedback amplifier connected in a
negative-feedback circuit to drive wideband, discrete multitone-based signals
through home power lines. The advantage of current feedback is that it allows
you the flexibility of increasing the gain
beyond unity without being limited by
the gain-bandwidth product. The AD8391 has 60-MHz bandwidth, 600V/
sec slew rate and 250-mA outputdrive-current capability, making it ideal
for driving home power lines.
The circuit in Figure 1 operates with
a 5V supply, has a voltage gain of
2(RF/RG), and drives a 33 load. The
33 load emulates the worst-case impedance of a home power-line network,
which can vary greatly from home to
home. The driver is transformer-coupled to the power line. The amplitude of
the output signal is 2.8V p-p into the
RF
412
6
VS
7
VMID
5
OUT2
_
+
POWER
differential power line
33
LINE
FROM DAC/MODEM
AD8391
(hot and neutral) with a
+
peak-to-average ratio of
_
4V/V. The feedback resistor, RF, and the gain
V
OUT1
PWDN
INI
Figure 1
3
4
resistor, RG, maxi1
2
mize circuit bandwidth
0.1 F
10 F
and stability. For this cirR
R
205
412
cuit, an acceptable band
0.1 F
0.1 F
49.9
width is approximately 30
MHz. The following
5V
PD
equation shows the relationship between closed- An xDSL driver uses current-feedback technology to make an
loop bandwidth (fCL), RG, efficient home-power-line driver.
and RF for current-feedback amplifiers.
should adjust these values based on each
application. The four 0.1-F capacitors
1
fCL =
.
provide ac coupling on the input and
R
R
output lines. The test signal is a com2C PR F 1 + IN + IN
RF
RG
posite waveform constructed from the

sum of 75 sinusoids of pseudorandom
CP, the internal capacitance, sets the phase. Each tone in the test waveform
corner frequency of the open-loop trans- may have one of four phases to emulate
impedance function, and RIN is the input QPSK. The sinusoids are orthogonally
impedance of the inverting terminal of spaced from 4 to 21 MHz, leaving the
each amplifier. (Figure 1 does not show amateur-radio bands empty. Figure 2
CP and RIN.) It is important to note that shows that the worst-case empty-tone
RF dominates the expression, thus con- distortion is 35 dBc. This figure is adtrolling the closed-loop bandwidth. The equate for most practical power-line ap49.9 resistors on the inputs of the cir- plications. Figure 3 shows the output in
cuit terminate the signal source. You the time domain.
S
Figure 2
AMPLITUDE
(10 dB/DIV)
START 3 MHZ
1.9 MHZ
STOP 22 MHZ
1V
100 nSEC
FREQUENCY
The output spectrum of the power-line driver in Figure 1 shows

that the worst-case empty-tone distortion is 35dBc.
P14
EDN B E S T
OF
Figure 3
This plot represents the time-domain characteristic

of the power-line driver.
www.edn.com
High Linearity, Low LO Drive
Input IP3: +25dBm at 900MHz
The LT 5522 active mixer offers the best-in-class combination of high linearity, low Local Oscillator drive requirement, excellent port-to-port isolation, good conversion gain and low power consumption. Its integrated RF transformer and on-board
50 matching enables single-ended RF and LO operation with minimum external components. These features, combined with
rock-solid performance over temperature, simplify your design task while providing consistent system results.
Features
LO Leakage vs LO Frequency
600MHz to 2.7GHz Frequency Range
Info & Online Store

www.linear.com
Literature: 1-800-4-LINEAR
Support: 408-432-1900
+25 dBm Input IP3 @ 900MHz

+21.5 dBm Input IP3 @ 1.9GHz
On-chip RF Transformer
50 Single-ended Matched RF and
LO Ports
12.5dB Noise Figure @ 900MHz
-5dBm LO Drive Level
, LTC and LT are registered trademarks of Linear

Technology Corporation. All other trademarks are the
property of their respective owners.
<-49dBm LO to RF or IF Leakage
The best of
controllers
Circuit ensures safety in power-on operation
Jean-Bernard Guiot, DCS AG, Allschwil, Switzerland

URING POWER- AND START- UP sequences (booting), the outputs of
industrial-control systems may
yield uncontrolled pulses before the software defines the correct status. If these
outputs control the power-on state of a
system, these uncontrolled pulses could
have dramatic consequences. The circuit
in Figure 1 is one approach to the spurious-pulse problem. The circuit costs
about 10 times less than other timers. The
open-collector output of the controlling
device connects to the reset input of the
CD4060 counter, IC1.You can easily adapt
this circuit to other controller-output
configurations. As long as R1 pulls the reset input high (controller-output off), the
counters clock stays disabled and all outputs are low. C, R2, and R3 are the timing
components for IC1.With R2R310 k
and C0.1 F, the measured clock frequency is approximately 360 Hz.
Figure 1
The output of the cirVCC

R2
R3
cuit is Q12. The reset input
must stay low longer than
16 9
10
11
VCC C0 C1
C2
R5
T(2 n1 )/f(2048)/
OUTPUT
1
3605 sec for the output
R1
IC2
Q12
to turn on (n is the output
12
6
number, 12). Any spuriIC
RESET
Q7
CD4060
ous pulse from the conR4
CONTROL
trollers output that is
OUTPUT
shorter than 5 sec has no
0V
LED
8
effect on the output of
0V
the circuit. Output Q13
of the counter turns on
This simple timing circuit ensures that a controllers spurious
after 11 sec, Q14 after 23
pulses do not affect a systems start-up operation.
sec, and so on. The LED,
connected to Q7 through R4, flashes on only if the controllers output is on.
during the timing period. With Choose the value of R1 depending on
VCC12V and an LED current of 10 the controllers output and the noise
mA, R4(VCC2)/101 k. For safe- level; in this design, R110 k. Note
ty reasons, you can add the optocou- that VCC should have a maximum valpler, IC2. If output Q12 of the counter ue of 15V for the CD4060 and 6V for
fails (shorted to VCC), the output turns the 74HC4060.
1
Microcontroller provides SRAM battery backup

Dave Bordui, Cypress Semiconductor, Orlando, FL
o maintain content in a power pins of the C. The C can then have no firmware, many Cs can run firmware
loss, many designs that include firmware that drives a third I/O to a logic- and continue execution throughout this
SRAM require a dedicated device high (source) mode or otherwise source power-supply transition. Continuing the
that can automatically switch from a current to an output pin.This output then Cs firmware execution allows other
standard power supply to battery opera- provides the uninterrupted power to the firmware-based functions, such as detion. Microcontrollers (Cs) seldom find external low-power SRAM device.
assertion of SRAM chip enable, batteryuse in power-switching applications. BeWhen the VCC rail is present, the C and rail-health indication, and analogcause Cs typically operate from the pri- draws current from the VCC pin and op- to-digital conversion. Take care to ensure
mary power supply, they stop execution erates normally. If the VCC rail drops be- that the entire design draws less current
if that supply drops, making it impossi- low the battery-input voltage, the C au- than the forward-bias-current rating of
ble to perform the switching. By using a tomatically draws current from the the protection diode. Also, the external
characteristic of many Cs, you can per- battery instead. Although this requires SRAM circuit must draw no more curform this switching function
rent than the Cs output can
MICROCONTROLLERwithout interruption to the
source. This stipulation remains
I/O-PORT INPUTS
VCC
SRAM (Figure 1). Many Cs
true whether the VCC rail or the
CHIP ENABLE
battery provides power. Also realhave internal protection diodes
POWER-SUPPLY INPUT
LOW-POWER SRAM
ize that, because the protection
on their I/O pins. Therefore, if
BATTERY INPUT
GND
diodes are sourcing the power, a
the VCC pin is left floating, the
MICROCONTROLLER
CPU in many instances powers
slight voltage drop exists on the
up and runs if you apply power
Cs uninterrupted-power-supOPTIONAL STATUS SIGNALS
only to an I/O pin.With this fact
ply output. This drop is equivaBATTERY OK
in mind, you can create an aulent to the one that the Cs manPOWER SUPPLY OK
VCC
GND
tomatic voltage switch by
ufacturer specifies. Consider this
connecting the main power- F i g u r e 1
drop when you select the battery,
supply rail and a secondary batVCC rail, and external-SRAM
voltage requirements.
tery backup to two separate I/O A microcontroller can power up and run even if its VCC pin is floating.
P16
EDN B E S T
OF
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2004 National Instruments Corporation. All rights reserved. Product and company names listed are trademarks or trade names of their respective companies.
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Factory: 1 (408) 944-0800
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MLF and MicroLead Frame are trademarks of Amkor Technology, Inc.
The best of
detectors
Thermal switches provide circuit disconnect

Mark Cherry, Maxim Integrated Products, Sunnyvale, CA
TO CIRCUIT
single temperature sensor

6
5
can provide an interrupt to a miC1
0.1 F
VCC OUTSET
crocontroller when the measured
3
OUT
IC1
temperature goes out of range. You
MAX6510
5V
SET
need multiple temperature sensors
1
POWER
R1
D
when you have to monitor more than
1
SUPPLY
HYST GND
13.7k
EC103A
4 2
one hot spot. A microcontroller impleR3
10k
ments the proper protective action
when one of the temperature monitors
IC3
C3
74HC32
detects an overtemperature condition.
0.033 F
6
5
C2
It is sometimes easier and more
VCC OUTSET
0.1 F
Figure 1
3
cost-effective to simply disconOUT
IC2
nect the offending circuit from the
MAX6510
SET
1
power supply without involving a miR2
GND
HYST
13.7k
crocontroller. A simple thermal-pro4 2
tection circuit (Figure 1) includes two
temperature switches, IC1 and IC2, with
active-high outputs. Temperature
thresholds for these switches depend on This thermal-protection circuit includes a crowbar device, D1, driven by thermal
resistors R1 and R2, and the switch out- switches IC1 and IC2.
puts connect to the inputs of a dual-input OR gate, IC3. OR gates with more (silicon-controlled rectifier) to crowbar the OR gate and cause the SCR to turn
than two inputs are available if you the power supply and blow the fuse. You on. Once triggered, the SCR cannot
need more than two temperature must take precautions to ensure that the turn off, and the fuse blows. A small RC
switches. When excessive temperature SCR does not trigger on a false gate filter, R3 and C3, suppresses any gate
drives either input high, the OR gates pulse. Power-supply transients can transients that would otherwise turn on
output switches high, causing an SCR cause a false high signal at the output of the SCR.
Circuit offers improved active rectification

Reza Moghimi, Analog Devices Inc, San Jose, CA
ectifiers convert ac signals duct, the amplifier is in an open-loop ure 1. The output is shown in green; the
to dc. You can combine a diode configuration, and VOUT2~0V. Figure 2 input is shown in red.
If VIN0V, the amplifier behaves as a
and a load resistor to create a half- shows the response of the circuit in Figwave rectifier, provided that the ampliVCC
tude of the ac source is much larger
than the forward drop of the diode
VOUT2
VOUT1
3
(typically 0.6V). Unfortunately, you
V
+
cant use this method to rectify signals
1
VIN
AD8591
that are smaller than a diode drop. For
4 _ SD
1N4154
V
these applications, active rectifiers using amplifiers are available. The diode
is inside the feedback loop of an am5k
VEE
plifier (Figure 1). For
Figure 1
VCC
VIN0V, the diode provides
negative feedback, and the output,
VOUT2, follows the input (VOUT2VIN).
For VIN0V, the diode does not conThis circuit is a typical half-wave-rectifier configuration.
www.edn.com
OF
The best of
detectors
comparator. Its negative input is at a

higher potential than its positive input,
so its output, VOUT1, saturates to VEE.
When the input again becomes positive,
the amplifier has to recover from saturation and respond as quickly as its slew
rate and saturation recovery time allow.
This response takes some time, and the
input may have changed by the time the
amplifier is ready to respond to the positive input. The signals at VOUT1 (red) and
VOUT2 (green) clarify this point (Figure
3). VOUT2 is the same waveform as in Figure 2. Note the change in scale factor.
VOUT1 is a diode drop higher for positive
inputs and saturates to VEE for negative
inputs. The time delay in the response
may result in a significant error in the
output.
For example, an amplifier that has a
slew rate of 2.5V/sec and saturates to
2.5V takes at least 1 sec to get ready
to respond to positive inputs. During
this time, the fast input has changed, so
rectification starts at the wrong part of
the input. One way to minimize this error is to use a high-slew-rate amplifier,
but this solution comes at the expense of
high power consumption. Another option is to use an inverting-amplifier configuration and two diodes, followed by
a unity-gain inverting amplifier to obtain the noninverting rectification. This
method appears in many textbooks. The
circuit in Figure 4 represents a onestage, noninverting rectifier that improves the accuracy of the rectification
and reduces the power consumption. In
this circuit, an AD8561 amplifier acts as
Figure 2
These signals appear at the input (red) and the output (green) of
the circuit in Figure 1.
Figure 3
These signals are the waveforms at VOUT2 (green) and VOUT1

(red) in the circuit in Figure 1.
a comparator. The AD8591 performs the

rectification.
When VIN0V, the output of the
AD8561 is high, and the AD8591 acts as
a follower. When VIN0V, the output of
the AD8561 is low, and the AD8591 shuts
down. This shutdown puts the output of
the AD8591 into a high-impedance state,
so it remains at approximately 0V, rather
than saturating to VEE as it did in the pre-
vious circuit. When VIN goes positive,

the amplifier comes out of shutdown and
again follows the input. This turn-on
time (the time it takes to come out of
shutdown) is much shorter than the saturation recovery time and slew-rate limiting that occurs in the previous circuit.
Figure 5 shows the signals at the input
(red) and output (green) of the improved rectifier circuit.
VCC
3+
V
AD8591
4_
SD V
VIN
VCC
V
3 _
5k
VEE
AD8561
2
VOUT1
1
4 V
7
5
6
VEE
Figure 4
P20
This circuit greatly improves on the performance of the circuit in Figure 1.
EDN B E S T
OF
Figure 5
These signals appear at the input (red) and output (green)

of the circuit in Figure 4.
www.edn.com
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Literature: (800) 401-9572 Factory: 1 (408) 944-0800

The best of
filters
Prevent instrumentation-amp RF-rectification errors

Charles Kitchin, Lew Counts, and Moshe Gerstenhaber, Analog Devices, Wilmington, MA
nstrumentation amplifiers serve across the instrumentation amplifiers between the two inputs tied together
in a variety of applications that need input pins. Because of this connection, and ground. C 2 does not affect the
to extract a weak differential signal any mismatch between the time con- bandwidth of the common-mode RF
from large common-mode noise or in- stants of C1A/R1A and C1B/R1B unbalance signal, because this capacitor connects
terference. However, designers often over- the bridge and reduce high-frequency between the two inputs, helping to
look the potential problem of RF rectifi- common-mode rejection. Therefore, re- keep them at the same RF-signal levcation inside the instrumentation sistors R1A and R1B and capacitors C1A el. Therefore, the parallel impedance
amplifier. The amplifiers common-mode and C1B should always be equal. C2 con- of the two RC networks (R1A/C1A and
rejection normally greatly reduces com- nects across the bridge output so that R 1B/C 1B) to ground sets common
mon-mode signals at an instrumentation C2 is effectively in parallel with the series mode bandwidth. The 3-dB comamplifiers input. Unfortunately, RF recti- combination of C1A and C1B. Thus con- mon-mode bandwidth is equal to
fication still occurs, because even the best nected, C2 effectively reduces any ac BWCM1/(2R1C1).
Using the circuit of Figure 1, with a C2
instrumentation amplifiers have virtual- common-mode-rejection errors from
ly no common-mode rejection at fre- mismatching. For example, making C2 value of 0.01 F, the 3-dB differentialsignal bandwidth is approxquencies higher than 20 kHz. The
imately 1900 Hz. When opamplifiers input stage may rectify a
V
0.01 F
0.33 F
erating at a gain of 5, the
strong RF signal and then appear as
RFI FILTER
circuit has measured dc-offa dc-offset error. Once the input
C
set shift over a frequency
stage rectifies the signal, no amount
R
1000 pF
4.02k
G=1+ 49.4k
range of 10 Hz to 20 MHz of
of lowpass-filtering at the instru1
R
+IN
+ 8
less than 6 V referred to
mentation amplifiers output can
C
2
7
the input. At unity gain,
remove the error. Finally, if the RF
AD8221
0.01 F
V
R
3
R
there is no measurable dcinterference is intermittent, meas4.02k
6 REFERENCE
_
5
IN
offset shift. Some instruurement errors may go undetected.
C
4
mentation amplifiers are
The best practical solution to this
1000 pF
0.01 F
more prone to RF rectificaproblem is to provide RF attenua0.33 F
tion than others and may
tion ahead of the instrumentation
need a more robust filter. A
amplifier by using a differential
V
Figure 1
micropower instrumentalowpass filter. The filter needs to
tion amplifier, such as the
remove as much RF energy as pos- This lowpass-filter circuit prevents RF-rectification errors
AD627, with its low-inputsible from the input lines, preserve in instrumentation amplifiers.
stage operating current, is a
the ac signals balance between
each line and ground (common), and 10 times larger than C1 provides a 20- good example. The simple expedient of
maintain a high enough input impedance times reduction in common-mode-re- increasing the value of the two input reover the measurement bandwidth to jection errors arising from C1A/C1B mis- sistors, R1A/R1B, that of capacitor C2, or
avoid loading the signal source. Figure 1 match. Note that the filter does not affect both can provide further RF attenuation
at the expense of reduced signal bandprovides a basic building block for a wide dc common-mode rejection.
The RFI filter has differential and width. Some steps for selecting RFI-filrange of differential RFI filters.
The component values are typical of common-mode bandwidths. The dif- ter component values follow:
1. Decide on the value of the two sethose for the latest generation of instru- ferential bandwidth defines the frementation amplifiers, such as the AD- quency response of the filter with a dif- ries resistors and ensure that the previ8221, which has a typical 3-dB band- ferential input signal applied between ous circuitry can adequately drive this
width of 1 MHz and a typical voltage the circuits two inputs, IN and IN. impedance. With typical values of 2 to
noise level of 7 nV/
Hz. In addition to The sum of the two equal-value input 10 k, these resistors should not conRFI suppression, the filter also provides resistors, R1A and R1B, and the differen- tribute more noise than that of the inadditional input-overload protection; tial capacitance, which is C2 in parallel strumentation amplifier itself. Using a
resistors R1A and R1B help isolate the in- with the series combination of C1A and pair of 2-k resistors adds Johnson
strumentation amplifiers input circuit- C1B, establish this RC time constant. The noise of 8 nV/
Hz. This figure increasry from the external signal source. Fig- 3-dB differential bandwidth of this filter es to 11 nV/
Hz with 4-k resistors
ure 2 shows a simplified version of the is equal to BWDIFF[1/(2R(2C2 C1))]. and 18 nV/
Hz with 10-k resistors.
RFI circuit. It reveals that the filter forms The common-mode bandwidth defines
a bridge circuit whose output appears what a common-mode RF signal sees
(Prevent contd on P46)
1A
1A
OUT
1B
1B
P22
EDN B E S T
OF
www.edn.com
PRIMARY SIDE CONTROLLER FOR HALFBRIDGE INTERMEDIATE DC BUS CONVERTERS

By Weidong Fan, Goran Stojcic and Carl Smith, International Rectifier
Figure 1
A simple open-loop primary side control for bridge-type isolated

intermediate bus converters is based on the integration of a fixed 50%
duty cycle oscillator with a 100V half-bridge driver to deliver a complete
primary side control and drive. In this scheme, switching frequency and
dead-time between the low-side and high-side pulses is adjustable in
order to fit various applications, power levels and switching devices.
The controller can also be easily synchronized to an external clock in a
wide frequency range, to improve performance of paralleled bus
converter solutions for higher power applications.
The IR2085S controller IC can be used to create a simple 48V DC bus
converter that delivers up to 25AOUT from between 6VOUT-12VOUT,
when used with a variety of primary and secondary side MOSFETs from
International Rectifier. The IR2085S is suitable for 48V regulated
systems or wide range input telecom systems, 36V-75VIN. The IR2085S
replaces two components that are normally used in traditional designs,
by combining the key features and functionality required for DC bus
converters (as shown in Figure 1).
Due to the fixed 50% duty cycle, the output voltage is proportional to the
input voltage with a factor K, where K equals the transformer turns ratio.
Figure 2: Front View

1.95
0.85
The half-bridge controller is designed to provide gate drive signals for halfbridge converters with 50% duty cycle and a minimum number of external
components. The high-side voltage can be up to 100V, suitable for 24V and
48V telecom, networking and computing applications. The primary side bias
voltage can range from 10V to 15V to further optimize circuit performance.
The pulse width difference between the high-side and low-side is less than
25ns to prevent magnetic flux imbalance, which is the main concern in the
bridge topology. The frequency and dead-time between the low-side and the
high-side pulses for half-bridge circuits can be adjusted with an external timing
capacitor to fit various applications, power levels, and switching devices.
Back View
The switching frequency of the controller is determined as follows in

Equation 1, where RT and CT are the external timing resistor and capacitor
values. The turn-off time of the primary power MOSFET can be estimated
as shown in Equation 2, where QGD is the MOSFET gate-to-drain charge
(Miller charge), and QGS2 is post-threshold gate charge, and Ig is the
driver current.
Equation 1
Equation 2
The IR2085S based DC bus converter demo board example as shown in

Figure 2 was designed to deliver 20A at ~8V output voltage achieving 96%
efficiency and high power density of 89 W/in3, or 270W/in2 at 48V input, at
a switching frequency of 220kHz. A well-designed 5V or 12V output regulated
BMP converter delivers 160W with 92-94% and in 1/4 brick size, highlighting
at least a 2% gain in efficiency and 50% reduction in board space when
choosing the IR2085S based DC Bus Converter approach.
for more great design tips and product news,

please call 800.981.8699 or visit us at
http://dc2dc.irf.com/dt2
THE POWER MANAGEMENT LEADER
The best of
filters
Build an adjustable high-frequency notch filter

John Ambrose, Mixed Signal Integration Corp, San Jose, CA
lthough you can obtain universal, resistor-programmable switchedcapacitor filters that are configurable
as notch filters, most cannot operate at
bandwidths higher than 100 kHz. Further, the typically 16- to 20-pin packages
do not include a continuous-time, antialiasing filter to prevent spurious signals
from appearing at the output. By using an
eight-pin, dual operational amplifier and
an eight-pin, switched-capacitor bandpass filter, you can construct a notch filter (Figure 1). IC2, a TLC082 is a dual BiCMOS op amp, replacing the older
JFET-input stage with lower noise CMOS
but retaining the bipolar output for high
drive capability. The gain-bandwidth
product of the TLC082 is 10 MHz, allowing you to use it for filtering at frequencies
as high as 1 MHz. The minimum
(VCCVEE) span with the TLC082 is 5V,
unlike the older TL082, which required
6V. This supply span matches well with
IC1, an MSHFS6, with its 5V nominal operating voltage. Using half of the TLC082,
you can construct a third-order, elliptic
lowpass filter.
You set the passband ripple at approximately 5 dB to increase the out-of-band
rejection.You set the continuous-time filter for 800 kHz, providing greater than 40
dB of rejection at 12.5 MHz. Figure 2
shows the frequency response of the third-
Figure 2
Figure 3
This plot is the frequency response of the

third-order lowpass-filter stage.
This Bode plot represents the passband of

the MSHFS6 filter.
order lowpass filter using the TLC082.

The MSHFS6 switched-capacitor selectable lowpass/bandpass filter with its 12.5to-1 clock-to-corner ratio allows for distortion measurements to 6.25 times the
notch center frequency before aliased signals cause measurement error. With the
TLC082 lowpass filter set at 800 kHz, you
can measure distortion products as high
as the third harmonic. If the notch center
frequency is always set lower than 260 kHz
(MSFS6 clock at 3.3 MHz), then you can
set the continuous-time lowpass filter corner to a lower frequency by adjusting the
resistor and capacitor values. By summing
the output of the bandpass filter with the
input, cancellation of the input signal occurs at 180 phase shift in the passband.
Figure 3 shows the Bode plot of the pass-
The circuit in Figure 1 delivers a 50-dB

notch.
band of the MSHFS6 sixth-octave filter

setting. The output of the other half of the
TLC082 provides the notch-filter output.
Figure 4 shows the depth of the notch filter at 50 dB.
5V
VDD
Figure 1
47k
100 nF
10k
IC2B
TLC082
_ 6
4
FSEL
OUT
10k
8
IN
1
2.4k
GND
IC1
TYPE MSHFS6S VSS
CLK
VDD
10k
47k
OF
4.7k
4.7k
100k
47 pF
470 nF
1k
SIGNAL
INPUT
20
10 pF
10 pF
4.7k
THIRD-ORDER, 800-kHz ELLIPTIC
LOWPASS FILTER
V2
6.25 MHz
5V
TUNABLE SIXTH-OCTAVE BANDPASS FILTER
EDN B E S T
10 pF
100 nF
2.4k
SUMMING STAGE
IC2A
TLC082
+ 5
NOTCH
OUTPUT
P24
Figure 4
An op amp and a switched-capacitor filter combine to

form a highly selective notch filter.
www.edn.com
DIRECTFET PACKAGE DRAIN CONNECTION

INCREASES BUCK CONVERTER POWER DENSITY
By Alex Milhalka, International Rectifier
International Rectifier HEXFET MOSFETs in the DirectFET

package are unique devices in which the silicon die attaches
directly to the PCB. The source and gate connections are on one
side of the die and the drain contact is on the other side. The
drain connects to the PCB via a copper can (DirectFET package).
Figure 1
In a synchronous buck converter, the control FET source, synchronous FET

drain and output inductor are all connected together, as shown in
Figure 1. Since the voltage at the node switches rapidly between VIN and
ground, this triple-point connection is known as the switch node.
When using DirectFET MOSFETs in the synchronous buck topology, the
trace between the control FET source and output inductor can be
eliminated and the can of the sync FET is used to provide this
connection as shown in Figure 2.
Figure 2
Figure 3 illustrates the current path (red arrows) when the control FET is
conducting. As can be seen the sync FET can provide the current path
from the control FET source to the output inductor. This is beneficial because
the can is equivalent to over 7 ounces of copper and has a maximum
resistance of 125microOhms. The can is, therefore, capable of passing
much current without being a factor in thermal design 30A at 10%
duty cycle dissipates only an additional 11 milliwatts in the can of the
sync FET due to conduction of the control FET.
The resulting board space saved by eliminating a PCB trace yields a
higher density design. Alternatively, the board area savings can be
used to increase the contact area of the lower FET source to the
PCB, providing better cooling of the synchronous FET, improving
thermal design and
increasing your buck
converter power density.
Figure 3
IR's proprietary DirectFET technology is covered by US Patent 6,624,522

and other US and foreign pending patent applications.
for more great design tips and product news,

please call 800.981.8699 or visit us at
http://dc2dc.irf.com/dt1
THE POWER MANAGEMENT LEADER
The best of
oscillators
Grounded resistor tunes oscillator

Vladimir Tepin, Taganrog, Russia
o vary the frequency of any
sine-wave oscillator, you should use
a pair of ganged variable resistors,
and you should thoroughly match their
characteristics over the entire variation
range to satisfy the oscillators balancing conditions. This restriction leads to
problems in the tuning range and high
cost, thereby limiting the range of applications. The sine-wave oscillator in Figure 1 is free of the cited disadvantage.
You can tune it over a wide frequency
range using only variable resistor R1. The
oscillator requires no balancing, so no
matching problems arise. The variable
resistor connects to ground, an advantageous fact in many applications. Like
most classic sine-wave RC oscillators, the
implementation comprises an operational amplifier, IC2, with two feedback
SW
C2
loops. One loop is a frequency-inde1 nF
IC1
IC2
pendent, positive-feedback loop using
OUTPUT
LT1361
two fixed resistors, R2 and R3, in this
example. The other loop is frequencyC1
10 nF
dependent. This loop uses capacitors
R3
C1 and C2; variable resistor R1; and a
R1
4.9k
R
2
single-pole, double-throw analog
1k
switch, IC1, driven by a periodic sequence of square-wave pulses apFigure 1
plied to the SW input.
Assuming a switching frequency,
In this sine-wave oscillator, the output freFS1/T, much higher than the oscillaquency is dependent only on the value of
tion frequency and assuming that the
the grounded resistor R1.
pulse width, , is half the switching period (0.5T), the approximate voltage where 01/2R
C1/C2 is the oscillation
transfer function of the frequency-de- frequency, d0
C1/C2 2
C2/C1, and
d12
C2/C1. Using this function and
pendent feedback loop is:
assuming the transfer coefficient of the
s2 + s 0d1 + 02
H(s) = 2
,
s + s 0d 0 + 0 2
(Grounded resistor contd on P46)
Frequency source feeds entire lab

Mitchell Lee, Linear Technology Corp, Milpitas, CA
lumbing a lab with a standard
frequency makes a lot of sense if the
lab uses multiple frequency counters, spectrum analyzers, and other
frequency-dependent test equipment.
Rather than spending time keeping all of
the instruments oscillators in calibration
or buying expensive,high-precision oscillators, you can use the circuit in Figure 1
to distribute a single calibrated frequency
source to the external-reference input of
each instrument. The circuit represents a
simple, 10-MHz source and distribution
amplifier. The output comes not from the
emitter or collector of the Colpitts-oscillator transistor, Q1, but rather from the
current flowing in the 10-MHz crystal.
The common-base stage, Q2, converts this
current into a voltage and establishes the
correct dc level for the output amplifier,
IC1. This IC contains four gain-of-two
buffers with 110-MHz, 3-dB bandwidth
and can drive double-terminated 50 or
75 loads.
As Figure 1 shows, the outputs use 75
impedance levels to take advantage of in-
P26
EDN B E S T
OF
expensive F-type connector hardware

and low-cost video coaxial cable. IC1 also
provides good isolation between its outputs, so that changes in loading on one
output do not affect the other outputs.
The circuit delivers more than 6 dBm to
each termination. If high accuracy and
low drift are critical needs, you can sub-
stitute Hewlett-Packards HP10811A

component oscillator for the Colpitts oscillator. Connect the HP10811As output
through a 510 resistor and a 10-nF coupling capacitor, directly to the emitter of
Q2. If you need more than four outputs,
you can duplicate the IC1 stage as many
times as necessary.
Figure 1
5V
10 F
47 nF
10k
Q1
2N3904
IC1
LT6551
330
10 MHz 7 TO 45 pF
Q2
2N3906
10k
RG-59/U
100 pF
10k
3.3k
100 pF
47 nF
330
47 nF
75
10 nF
75
10 nF
20k
RG-59/U
CLOCK
OUTPUTS
RG-59/U
75
10 nF
75
10 nF
RG-59/U
A laboratorywide distribution system is an alternative to multiple frequency sources.
www.edn.com
When youll see NOR flash in

high-density, high-performance
memory applications.
SLC NAND
READ
PROGRAM
MLC NAND
MAXIMUM
DENSITY
MLC NOR
27MB/s
20.5MB/s
55.2MB/s
50.MB/s
25s+50nsx1056
for 2K bytes
50s+50nsx1056
for 2K bytes
80ns+30nsx7
for 16 bytes
85ns+25nsx3
for 8 bytes
8.3MB/s
1.7MB/s
0.15MB/s
0.145MB/s
107s
for 16 bytes
440s
for 64 bytes
50nsx1056+200s 50nsx1056+1.2ms
for 2K bytes
for 2K bytes
ERASE
SLC NOR
1.5ms
2ms
2s
1.2s
128 Kbytes
128 Kbytes
64 Kbytes
128 Kbytes
2Gb
4Gb
128Mb
256Mb
Based on current manufacturers specifications.
There are plenty of misconceptions flying around about NAND vs. NOR Flash memory technology. The reality is that NAND
Flash memory from Toshiba is an ideal solution for high-density, high-performance applications such as mobile handsets
and PDAs as well as digital still and digital video cameras. In fact, Toshibas NAND Flash is available in densities
up to 16 times greater than NORthe highest in the industry. > With significantly faster programming and erase
times. Actually, the time to erase and reprogram the same amount of data is up to 25 times faster when using
Toshiba MLC NAND compared to MLC NOR.1 Thats a difference users will notice. Plus there are definite advantages
in Toshibas NAND Flash power consumption. NAND Flash uses up to 72% less current than NOR. > Think of all the real
possibilities high-density, high-performance NAND Flash from Toshiba can enable. The company that invented flash memory
helps you get back to reality and on to designing! Discover the truth about NAND at nandperformance.toshiba.com.
You know pigs will never be able to fly.
1
For MLC NAND, a 128Kbyte block takes 2 milliseconds (ms) to erase and 80ms to program (82ms for 128Kbytes). For MLC NOR, a 128Kbyte block takes
1.2 seconds (s) to erase and 0.88s to program (2s for 128Kbytes).
All trademarks and tradenames held within are properties of their

respective holders. 2004 Toshiba America Electronic Components,
Inc. FLSH-03-103
The best of
power
Switched-capacitor IC and reference form

elegant 48 to 10V converter
Wallace Ly, National Semiconductor, Santa Clara, CA
system designer must almost
always face a trade-off in choosing
the right part for an application. The
trade-off usually involves performance,
price, and function. An example is the issue of powering circuits from a telecomvoltage source. Telecom systems almost
exclusively use high-potential negative
rails, such as 48V. Digital circuits typically in use in such applications usually
operate from a brick-type power supply. However, analog circuits rarely require enough power to justify using a
costly brick. At the heart of these bricks
is nothing more than a specialized
switching converter in tandem with an
isolated flyback-transformer coil. But
some applications neither require nor
can tolerate the use of a coil-based approach. Figure 1 depicts a way to address
the problem. The circuit provides a small
R3
10k
amount of power to analog/digital
Q
V
N2222
circuits, such as the LMH6672 DSL
R
op amp.
C1
GND
1k
The LMV431 voltage reference,
LMV431
3.3 F
C1+
along with the voltage-setting resistors
R
280
sets the output voltage to approxiC2
V
mately (1 1 k/280)1.24V
C2+
5.7V. This output voltage then
FUSE
LM2682
F
i
g
u
r
e
1
goes to the base of Q1, the
2N2222 transistor. The configuration
OUTPUT 10V
INPUT 48V
of the transistor causes a VBE drop of
approximately 0.7V, resulting in a net This simple circuit provides a 10V power source
voltage of 5V for the next stage. The from 48V telecom power rails.
purpose of the transistor is to provide
additional current to the LM2682 LM2682 and the SOT-23-3 package of the
switched-capacitor converter. Note that LMV431 allow the circuit to consume litthe converter has a 5V reference (GND tle board space. In roughly the size of a
pin). Small capacitors C1 and C2 enable small transformer, the proposed circuit
the pumping and inverting action re- does an elegant job of powering lowquired to convert the 5V to 10V. Fur- power circuits from a negative high-voltthermore, the MSO-8 package of the age source.
1
IN
OUT
Buck-boost regulator suits battery operation

Kahou Wong, ON Semiconductor, Phoenix, AZ
The MC33166/7 has a 40V maximum
buck/boost converter can step divides the 14.1V output voltage to 5V
a voltage up or down. Such a con- for connection to the FB pin of the IC. switch rating, and it can accommodate
verter is appropriate for battery- So, the IC effectively regulates an input 95% duty cycle, so its adequate for the
powered applications. One application of VIN VOUT18 14.132.1V to an application. To implement synchronous
rectification for better efficiency, the dederives a regulated 14.1V at 1A from 12V output of 14.1V.
sign uses an additional transsolar panels with 9 to 18V variation.
former winding and a MOSIn this type of battery apFigure 1
INPUT
OUTPUT
FET. The auxiliary winding
plication, efficiency is an
MC33166/7
provides bias voltage to turn
important factor; hence, this design
COMP
on the MOSFET when the
uses an inexpensive synchronous-recV
GROUND
switching-node polarity turns
tifier-based MC33166/7 circuit. It is
SWITCH
negative. Note that the syndifficult to find a buck-boost conFB
chronous rectifier is an imtroller in the market. It is even more
5V
portant factor in the efficiendifficult to find an inexpensive one
cy of this circuit, because the
with an integrated high-current
input-to-output ratio is apswitch. One way to build a buck-boost
proximately 1-to-1. So, the
converter is to use a buck regulator
duty cycle is approximately
with an internal switch, such as the
50%, which means that the
MC33166/7 (Figure 1). The negativeMOSFET conducts for half the
polarity output voltage connects to This inexpensive buck-boost controller uses synchronous
switching-frequency period.
the ICs ground pin, and a resistor pair rectification for high efficiency.
IN
P28
EDN B E S T
OF
C1
3.3 uF
www.edn.com
C2
3.3 uF
Your Power Design

Is in Trouble.
Now the Bad News.
Your power IC supplier cant save you. The IC
that looked so good on the data sheet doesnt
work the way you expected. And dont even bother
asking their applications engineers to help you out
of this mess.
You could have chosen the proven source for highperformance power management Linear Technology.
With over 3,000 power management ICs in our
catalog, weve got the right part for your application.
Our power ICs are developed by experts who understand the subtleties that go beyond the data sheet.
Our applications engineers are ready to help you
design the right power solution from start to finish.
With Linears reputation for quality, reliability and
on-time delivery, your next power decision is easy.
Performance Driven.
www.linear.com
LT, LTC and
are registered trademarks of Linear Technology Corp.
The best of
power
Dual comparator thermally protects

lithium-ion battery
Mike Hess, Maxim Integrated Products, Sunnyvale, CA
ost manufacturers recom- MAX9032 are available in SOT-23 pack- configure its SELV input for charging a
mend that you dont change lithi- ages, and both offer built-in hysteresis of 4.1 or 4.2V battery. The SELI input sets
um-ion batteries at temperatures 2 or 4 mV, respectively.
the charge current to either 100 or 500
lower than 0C or higher than 50C. You
IC2 is a single-cell lithium-ion battery mA, and an open-drain output, CHG, incan monitor both thresholds by adding charger that can derive its power directly dicates the charge status. For near-dead
a thermistor and dual (window) com- from a USB port or from an external sup- batteries, a preconditioning capability
parator to a lithium-ion battery charger ply as high as 6.5V. The 0.5% accuracy of soft-starts the cell before charging. Oth(Figure 1). Set the low-temperature trip its battery-regulation voltage allows max- er safety features include continuous
point at 2.5C and the high-temperature imum usage of the batterys capacity. The monitoring of voltage and current and
trip point at 47.5C. A precision voltage chargers internal FET delivers as much as initial checking for fault conditions bereference is unnecessary, because the 500 mA of charging current, and you can fore charging.
comparators resistor
V
network is ratiometric,
so variations on the supply voltage, VBUS, do not
BATT
0.1 F
4.7 F
IN
affect the trip thresholds.
2.2 F
+ SINGLE
LI-ION
By driving the chargers
10k
13k
BATTERY
100k
V
1%
1%
SELV
enable input, EN, the
INA+
IC
270
+
comparators openMAX1811
500 mA
OUTA
SELI
Figure 1
INA
100 mA
_
drain outputs ensure
19.1k
10k
1%
CHG
OPEN-DRAIN
that charging is inhibited
IC
OUTPUTS
EN
LMX393
GND
when the battery temBATTERY PACK
EN
GND
perature is out of range.
NTC THERMISTOR
OUTA
INB+
+
(SUCH AS FENWAL
OUTB
ELECTRONICS
As an alternative, you can
OUTB
140-103LAG-RB1)
INB _
substitute a dual comDUAL SCHOTTKY
DIODE, SOT-323
parator with push-pull
CMSSH-3A
GND
10k AT 25 C
18k
1%
CMOS outputs, such as
HOT (47.5 C): 3.97k
NOTE:
the MAX9032, if you also
COLD (2.5 C): 28.7k
YOU SHOULD ADD THE DUAL SCHOTTKY DIODE
IF YOU SUBSTITUTE A CMOS-OUTPUT DUAL
add a tiny, SOT-323 dual
COMPARATOR, SUCH AS THE MAX9032.
diode (the dashed lines
in Figure 1). The dual
comparator and the While charging a lithium battery from a USB port, this circuit provides thermal protection for the battery.
BUS
CC
o
o
Reset supervisor waits for stable supply

Mike Mitchell, Texas Instruments, Dallas, TX
he power-up cycle of the supply
voltage in embedded-system applications is sometimes not a clean
event. This fact holds especially true in
battery-operated systems, because the
insertion of a battery often causes significant ringing or glitching on the supply line (Figure 1). In products with onoff switches, the contact bounce of the
switch can cause an unclean power-up.
P30
EDN B E S T
OF
A power-up cycle such as the one in Figure 1 can often cause a processor to enter a brownout condition. This condition constitutes an errant condition of
the processor, which requires a reset to
take place before the processor behaves
as expected. The processor is often
lost or in the weeds during a
brownout condition. Usually, a reset supervisor controls the reset line to the
processor and thus avoids the brownout

condition. Traditional supply-voltagesupervisor circuits hold the processor in
reset until the supply voltage reaches a
predetermined value. They also reset the
processor if the voltage dips below the
predetermined value. However, the level at which the SVS operates often does
not suit the system. For example, the
level may be lower than the minimum
www.edn.com
10A
&
16A
SIP DC/DC Converters
High Performance, Easy to Use, Lead Free, Low Cost
DATELs LSN Series are outstanding point-of-load
buck regulators. They have wide input ranges, high
efciencies, low noise and the best thermal performance.
They require no additional I/O
ltering for noise or EMI suppression. They are lead-free,
affordable and available from
stock.
Some SIPs are simply better.
They are called LSNs. Call
for a free sample today.
Output
Current
(Amps)
10
16
Fully rated over temp. for 10 or 16 Amps

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Efciencies to 96%; Noise as low as 10mVp-p
Standard SIPs with 3 vert./hor. orientations
UL/EN certied; EMC compliant; Lead-free
<$1 an Amp in OEM quantities
Application Notes and

Comprehensive Catalog at www.datel.com
VIN Range
(Volts)
Output Voltage
(Volts)
Untrimmed
VOUT
Accuracy
R/N
(mVp-p,
Max.)
Efciency
(%)
Package Size
(Inches)
DATEL
Model Number
3.3
3 to 3.6
1 to 2.5V, 7 models
1%
35
90.5 to 95.5
4.5 to 5.5
1 to 3.8V, 8 models
1%
35
89 to 96
12
10.8 to 13.2
1 to 5V, 10 models
1.25%
45 to 75
86 to 95.5
3.3/5
3 to 5.5
0.75 to 3.3V, 9 models
1.5%
50
86 to 95
12
10 to 14
0.8 to 5V, 10 models
1.25%
45 to 75
86 to 95.5
Vertical Models
2 x 0.36 x 0.5h
(Tyco compatible)
2 x 0.37 x 0.5h
Horizontal Models
2 x 0.5 x 0.37h
LSN-/10-D3
Nominal
VIN
(Volts)
All models have a VOUT trim range of 10% with the exception of the LSN-T/16-W3 and LSN-T/16-D12
models which are trimmable from 0.75 to 3.3V and 5V, respectively.
Ripple/noise is tested/specied over a 20MHz bandwidth and typically does not require the installation
of external I/O caps to achieve listed performance.
Listed specs are typical for nominal-line and half-load conditions.
Internet: www.datel.com
LSN-10A, D3
$11.90
LSN-/16-W3
LSN-10A, D5
LSN-10A, D12
LSN-/10-D12
LSN-/16-D12
Data Sheet @
www.datel.com
$14.95
LSN-16A, W3
LSN-16A, D12
Develop the specic model number by listing the selected VOUT (1.8, 3.3, etc.) in this position.
See data sheets for additional function and package options.
LSN-16A, W3 models have a wide input voltage range that accommodates both 3.3V and 5V
standard input voltages.
DATEL, Inc., 11 Cabot Boulevard, Manseld, MA 02048 Tel: (508) 339-3000, (800) 233-2765
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ISO 9001 Registered
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USA Price
(10k Qty.)
INNOVATION and EXCELLENCE
The best of
power
operating voltage of the processor, or it

may be higher than the desired operating voltage of the system. The reset circuit in Figure 2 provides a reset to the
processor based on stabilization of the
supply voltage and not on a predetermined value.
The circuit uses a TLV3491 from Texas
Instruments (www.ti.com). The comparator draws approximately 1 A and
operates from 1.8 to 5.5V, making it
well-adapted to battery-operated applications. The input to the minus terminal
is a simple resistor divider. The resistor
values should be relatively high to reduce
the power consumption of the circuit.
The input to the plus terminal is basically an RC circuit. The RC time constant provides a tunable power-up delay.
When you apply power or insert a battery, the output of the comparator is low,
holding the processor in the reset condition. The plus input of the comparator becomes higher than the minus input only after the supply voltage
stabilizes, resulting in a high output state and thus releasing the

processor for operation. The stabilization time for the supply
voltage depends on the RC-network component values. Here,
the use of low-value resistors carries no penalty, because no current flows through the RC network after supply stabilization.
By selecting R1, C1, R2, and R3,
you can guarantee a reliable reset signal to the processor for a
given dV/dt for VCC. The equations for the voltages at the comparators inputs are:
Figure 3
+
V = VCCVCC e
V = VCC
t
R1C1
The circuit in Figure 2 enables the processor well after

the stabilization of the power-supply voltage.
R3
.
R2 + R3
To hold the processor in reset, you

need the condition VV . That condition yields:
t
R3
VCC
> VCCVCC e R1C1 .
R2 + R3
Solving for t, you obtain
R2
t <R1C1 ln
.
R 2 + R 3
From the last equation, you
can calculate the amount of
time the processor stays in reset.
Therefore, as long as the supply
ramps to a steady state in a
shorter time, youre guaranteed
a reliable reset. The reverse-biased diode and resistor R4 pro-
Figure 1
Insertion of a battery supply often results in

glitching and ringing.
1
R4
1k
R1
150k
+
3
R2
46k
R3
1M
TLV3491 4
RESET
MSP430
MICROCONTROLLER
C1
0.1 F
Figure 2
This circuit resets a processor based on the stabilization time of the supply voltage.
P32
EDN B E S T
OF
vide a faster discharge path for the capacitor. This fast discharge allows the circuit to quickly react to negative glitches in
the supply voltage during normal operation, in which it may be desirable to reset
the processor. R4 allows you to tune the
response time of the circuit for any expected supply-voltage glitches. Removal
of the resistor yields the fastest response
time to supply-voltage glitches but may
result in undesired resets for the processor. The pullup resistor at the output of
the comparator is necessary because of
the comparators open-drain output. The
capacitor at the comparators output
smoothes any fast switching the comparator may encounter.
The current consumption of the circuit
in Figure 2 is approximately 1 A (the
current consumption of the comparator)
plus the current through R2 and R3. The
circuit costs less than many dedicated
supply-voltage supervisors. Figure 3 illustrates the performance of the circuit.
Figure 3 is a scope capture of the same
battery insertion of Figure 1. The top
trace is the supply voltage; the next trace
is the positive input to the comparator.
The negative input to the comparator is
the next trace, and the bottom trace is
the comparators output (connected to
the microcontrollers reset pin). You can
clearly see that the circuit holds the
processor in reset until the supply stabilizes. Thus, the performance depends
not on any predefined supply-voltage
level, but rather on stabilization time.
www.edn.com
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The best of
sensors
Safety device uses GMR sensor

J Pelegri-Sebastia and D Ramirez-Munoz, University of Valencia, Spain
his Design Idea presents a differential safety device to prevent risks
arising from current leakages in
household applications. The proposed
circuit uses a new method for differential current sensing (Figure 1). The
method entails the use of Helmholtz
coils and a magnetic sensor based on the
GMR (giant-magnetoresistive) effect.
The AC004-01 magnetic sensor from
NVE (www.nve.com) uses GMR technology (Reference 1). Two Helmholtz
coils carry the households input current. If no differential current between
phase and ground exists at the center of
the coils, then the magnetic field is uniform and null. But, in the presence of an
unbalanced magnetic field, corresponding to a leakage current to ground, a differential magnetic field appears at the
center of the Helmholtz coils (Reference

2). Thus, the sensors output is a nonzero voltage that the circuit in Figure 1
amplifies and compares with a preset
reference voltage. The refFigure
erence voltage corresponds
to the highest allowable leakage
currentgenerally, approximately 30 mA.
The sensors output, a differential voltage, connects via a
highpass filter to an INA118 instrumentation amplifier, a device with high common-mode
rejection (Reference 3). This
stage converts the sensors differential signal from a Wheatstone-bridge arrangement to a
unipolar output with an appropriate gain figure. This output
goes through a half-wave rectifier and a

lowpass filter and becomes a dc signal. If
this signal is greater than VREF1, then the
MOC3041 optotriac turns off, thereby
2
The sensors output (Channel 4) is zero because the

differential line current is zero.
220k
Figure 1
VCC
100 nF
V+ 5
GMR
SENSOR
GND V
4
FILTER
VCC
VCC
50
8
5V
1
3
7
+
10k
IC1
INA118
6
8
100 nF
1M
3.3k
4
8
J1
100 nF
VREF1
VREF2
100-kHz
FILTER
VCC
500k
SEN
IC1B
8
5
OPA2234
+
7
6
IN4148
4
REFERENCE VCC
VOLTAGE
VREF1
IC1A
OPA2234
1
1M
J2
SEN+
3 +
HALF-WAVE
RECTIFIER
AND FILTER
100
10 F
3k
J2
2
VREF2
VOUT
LM4040
2.5V
J3
1
2
VCC
VOUT2
COMPARATOR
1
3.3k
VCC
VREF1
1.3k
5 6 8
2 +
1k
VOUT
VCC
4 1
820
10k
2.5k
7
IC4
LM311
3
2
S1
1 ID
2 OD
T1 6
T2 4
J5
MOC3041
RELEASE
Q1
2N2905
1
10M
8.7k
RELEASE
SWITCH
J4
This circuit uses a GMR sensor to detect and disable dangerous differential line currents.
www.edn.com
OF
The best of
sensors
Figure 3
Figure 4
A ground current generates a nonzero magnetic field

in the sensor (Channel 4).
interrupting the power to the household

appliance. Figures 2 and 3 depict two
scenarios. The Channel 1 trace represents the line current; Channel 2 shows
the current circulating through the line;
and Channel 4 represents the sensors
output, which is proportional to the difference between line and ground currents. In Figure 2, the sensors output is
zero because the current difference is null.
The ground current exceeds 30 mA. An optotriac and a

relay disconnect power to the household appliance.
Figure 3 shows a ground current that

generates a nonzero magnetic field in the
sensor. In Figure 4, the ground current is
greater than 30 mA. The comparator
changes state, activating the optotriac
(Channel 1) and turning on the relay
(Channel 2, 20 mA/division). Channel 3
shows the live current, and Channel 4
shows the sensors output (1 mV/division).
References
1.Daugton,JM,Giant magnetoresistive
in narrow stripes, IEEE Transactions on
Magnetics, 1992.
2. Smith, CH, and RW Schneider, Low
magnetic field sensing with GMR sensors,
Sensors magazine, September 1999.
3. Casas, O, and R Pallas,Basics of analog differential filters,IEEE Transactions on
Instrumentation and Measurement, 1996.
Use a DAC to vary LVDT excitation

Anthony Di Tommaso and Ljubisa Milojevic, ABB Inc, Natrona Heights, PA
VDTs (linear variable differential transformers) are electromechanical measuring devices that
convert the position of a magnetic core
into electrical signals.You generate these
signals via excitation on the primary
side. The results on the secondary
sidetypically, two secondary windingsdepend on the position of the
core (Figure 1). The excitation typically ranges in amplitude from 1 to 10V
and in frequency from 1 to 10 kHz, depending on the type of LVDT you employ. Traditionally, for one circuit to
provide such variability in frequency
and amplitude, you can use either an LC
tank with adjustable components or a
sine-wave generator under microcontroller control. It can be difficult to
achieve precision over time and temperature with the LC-tank circuit because of variations in passive components. You also must manually perform
calibration. You can more easily obtain
precision over time and temperature
through the use of a microcontroller-
P36
EDN B E S T
OF
controlled sine-wave-generator chip, move offset. You need to eliminate as

and calibration can be automatic, but much offset in the signal as possible bethe method incurs a greater expense cause such offset adversely affects the
than the LC-tank circuit. The circuit in transformation process.You can use an op
Figure 2 presents an alternative.
amp to remove the offset because the offRather than using a sinusoidal signal to set is constantin this case, half the voltexcite the LVDT, a triangular wave comes age that powers the microcontroller. In
from the integration of a square-wave out- general, you should choose an op amp
put provided by a microcontroller timer. with low offset and low bias, not only for
With the use of a current-output DAC, the difference stage, but also later.
such as the AD7564 from Analog
Figure 1
Devices (www.analog.com), you
can create a circuit that provides an alterPRIMARY
SECONDARY
native at a lower cost than that of a sinewave-generator chip and with greater ease
3
of modification than with an LC-tank cir1
cuit. Beginning with the microcontroller,
4
the frequency of the excitation wave de5
pends on the configuration of the micro2
controllers timer.You can configure a freerunning timer, for example, to toggle the
6
output based on the comparison match of
a preset count. You base the count on the
desired frequency output and the timers
An LVDT is an electromechanical measuring
internal clock rate.You then adjust the outdevice that converts the position of a magput of the microcontrollers timer to renetic core into electrical signals.
www.edn.com
Automatic Display Brightness

Low Cost. Easy.
LX1970
Visible Light Sensor
Simplicity is the key to Microsemis new LX1970 Visible
Light Sensor.
Designing with it is easy. You need no optical filters, and
as few as a single resistor to build a complete ambient
light-sensing function.
Its easy for users as well, responding to light just like the
human eye. Its not fooled by ultraviolet or infra-red signals.
Set the LX1970 sensor once and a display will remain at an
eye-comfort level thereafter.
Dawn to midnight, indoors and out.
Its a simple solution that can extend battery
operation in portable products and component
life in stationary applications.
Key Specifications
Visit our website for all the LX1970s

technical information:
www.Microsemi.com.
Approximates human eye spectral response

Accurate/repeatable output current vs. light
Voltage scalable
Integrated high gain photo current amplifiers
Complementary current outputs
Temperature stable
8-pin MSOP package
www.Microsemi.com
2004 Microsemi Corporation. All trademarks are of Microsemi Corporation.
The best of
sensors
VCC
Figure 2
3
SDIN
CLK
RESET
GAIN_DAC_LD
FSIN
SDOUT1
15
SDIN
16
12
13
14
11
TIMER
OUT
R2
11k
24
5
9
2
7
IC2B
AD712
3V
VCC
Vcc
R1
11k
CLKIN
IOUT1A
CLR
IOUT2A
LDAC
VREFB
FSIN
IOUT1B
RFBA
19
21
22
23
25
28
IC1
AD7564
RFBB
NC
RFBC
RFBD
IOUT2C
IOUT2D
VREFD
VREFC
IOUT1C
18
A0
17
A1
R4
10k
IOUT2B
SDOUT
20
R3
10k
VDD/REFA
IOUT1D
26
10
C1
470 pF
4
8
VDD
VDD
DG AG
ND ND
1 27
Q1
MMBT2222A
4
2
3
IC2A
AD712
LVDT
PRIMARY
INPUT
Q2
MMBT2907
8
VDD
This circuit uses a triangular wave from a DAC to excite an LVDT.
Once you center it about common,

the signal becomes a triangular wave.
The integrator you use is basically a single-pole, lowpass filter with a configurable (via the DAC) corner frequency.
The corner frequency you choose guarantees that integration of the excitation
signal occurs. To accommodate variability in frequency and amplitude, the DAC
provides an easy interface. With two
channels of the AD7564, the circuit can
emulate variable resistors for the feedforward and the feedback of the integrating op amp. (The other two channels
could serve for the demodulation gain of
each LVDT secondary.) You can use
these resistors to form the corner frequency for the lossy integrator and to
establish the gain through the circuit, ensuring that the signal is integrated and
that the amplitude of the excitation signal is appropriate for the LVDT.
You need to make several calculations
in advance to determine the configuration of the DAC and the establishment
of the resistances. According to the data
sheet, the resistance of the R-2R ladder
in the Analog Devices AD7564 DAC is
typically 9.5 k. You can calculate the
feedback resistance using the following
formula: RFB1/(2fDC), where fD is the
desired corner frequency of the integrator and C is the value of the capacitor
you use. You can then assemble the data
word for that effective resistance
accordingly: NFB(40969500)/RFB,
Figure 3
TIMER OUTPUT
PRIMARY INPUT
SECONDARY 1
OUTPUT
SECONDARY 2
OUTPUT
Although what appears on the secondary side differs from

the excitation signal, it is sufficient because of the inherent
filtering properties of the LVDT.
P38
EDN B E S T
OF
3
VDD
where NFB is the digital word loaded into

the DAC. The feed-forward resistance of
the integrator circuit is then RI
RFB/(gain factor), where the gain factor
depends on the desired output amplitude.
The data word for that effective resistance
becomes NI(RFB/RI)NFB or NI(gain
factor)NFB. In most cases, you may need
to use additional drive current from the
output of the lossy integrator to drive
the primary coil of the LVDT. This approach may entail the addition of transistors and other components.
You have some flexibility in the type of
excitation signal the circuit uses because it
is common practice to calibrate an LVDT.
Figure 3 illustrates the output of the excitation circuit and the results on the secondary side of the LVDT. Although what
appears on the secondary side differs
from the excitation signal, it is sufficient
because of the inherent filtering properties of the LVDT. The output of each secondary side generally transforms into a
constant root-mean-square or mean-absolute-deviation value. In the situation of
two secondary coils, a comparison between those values occurs. As long as you
excite both coils in the same manner
which is guaranteed because only one primary coil existsand the output signal is
of sufficient resolution, then a triangular
wave can excite such an LVDT.
www.edn.com
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The best of
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Software snippet provides improved

subset-sum algorithm
Ivan Basov, Brandeis University, Waltham, MA
he subset-sum problem is one
of the most frequently occurring
NP (nondeterministic, polynomial-time)-complete) problems. It asks
whether a subset of numbers in a set
of positive integers adds up exactly to
a given value. A relaxed version of the
problem tries to identify a subset of
numbers that adds up to a maximum
value no greater than a given value.
This problem arises in transportation, network design, scheduling, logistics systems, robotics, and many
other areas. The problem permits you
to develop and illustrate the power of
different algorithmic tools. The problem is as follows:
Given a set of positive integer values W[1], W[2], ...W[m] and an integer n.0, does a subset of the values
add up to exactly n?
A well-known pseudo-polynomial
algorithm (Reference 1) defines a
table: T[ij], 1im and 1jn, to
be T[ij]true if and only if a subset
of W[1],...W[i] sums to exactly j.
The algorithm uses O(mn) time to
fill in a table that uses O(mn) space.
Table 1 with n13 shows the true
entries and leaves the false ones
blank. This Design Idea proposes an
improved algorithm that uses O(mn)
time to fill in an array that uses only
O(n) space:
SubsetSum(W, m, n)
1. Define a bit array A[j],
1 j n.
2. Initialize the array to zeros.
3. A[0]:1.
4. for i:1 to m do.
5. for j:n to 0 do.
6. if A[j]1
then A[j1W[i]]:1.
7. return A[n].
You can easily prove that the returned
value is 1 if and only if a subset of the
weights adds up to exactly n. The proof
is analogous to the one of the original
O(mn)-space algorithm. The following
routine implements the above algorithm
in C++. It just shifts a bit map m times
by W[j] bits and applies a bitwise OR operation with the bit map from the previous step.
int SubsetSum(int W[], int m, int n)
{
bit_vector x1;
for(i1; i <m; i++) x |x<<W[i];
return (x>>n) &1;
}
The bit_vector class overloads bitwise
operators and behaves as an (n+1) bits
integer (with bits ranging from 0 to n).
Now, consider a low-density subset-sum
problem, the case in which the above algorithms produce a bunch of zeros and
only a few ones in the bit array. You use
a dynamically growing linked list and
waste no space for empty elements:

SubsetSumLD(W, m, n)
1. Define, a linked list with only one
element with value 0 and with the
Head being equal to the Tail.
2. for i:1 to m do.
3. for Element :Head to Tail do.
4. if Element.value+W[i] n.
5. Insert(Element.value+W[i]).
6. if Head.valuen.
7. return 1.
8. else.
9. return 0.
The function Insert(value) inserts the
value into the list in descending sorted
order. The function does nothing if an
element with the same value already exists. The disadvantage of the subset-sum
algorithm is that it solves only a decisiona yes-or-no problemand does
not allow restoring the partition itself.
To overcome this disadvantage, you can
use an array of integers instead of an array of bits and store the number of ones
in the corresponding element. This solution requires O(n log(m)) space, and
the array represents the sum of the rows
of the table T[ij] of the original O(mn)space algorithm.
Reference
1. Garey, M R and Johnson, D S, A
Guide to the Theory of NP Completeness,
Freeman, San Francisco, 1979.
TABLE 1SUBSET-SUM ARRAY

i/j
W[1]=1
W[2]=9
W[3]=5
W[4]=3
W[5]=8
www.edn.com
0
T
T
T
T
T
1
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
10
11
12
13
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OF
The best of
software
Make noise with a PIC

Peter Guettler, APS Software Engineering GmbH, Cologne, Germany
5V
uilding a stable noise generator for audio-frequency pur1
VDD
GP5/CIN
poses requires only a few comGP4/COUT
GP3/MC
ponents. The circuit in Figure 1
IC
GP2
PIC12C508P
GP1
relies on linear-feedback shift regis8
VSS
GP0
ters and some simple software. An
eight-pin Microchip PIC12C508
ADDITIONAL
controller (IC2) with a short proPICs
gram generates pseudorandom
1
noise at its output pin, GP0. A single
GP5/CIN
VDD
GP4/COUT
controller is sufficient for simple apGP3/MC
IC
GP2
PIC12C508P
plications. To obtain Gaussian-disGP1
8
GP0
VSS
tributed noise, you can use a number of identical PIC controllers in
parallel in a true realization of the
NOISE
central-limit theorem. (The centralGENERATORS
limit theorem states that the sum
Figure 1
(Make noise contd on P46)
5V
10k
2
3
4
5
6
7
R1
nR
R
5V
5V
10k
6 _
2 _
2
3
4
5
6
7
IC1A
TL072P
3 +
0.1 F
DISABLE
220
VOUT
PINK NOISE
400 mV P-P
300
1k
5V
3.3k
2
nR
S1
4
3k
R2
IC1B
TL072P
5 +
6.8k
1 F 0.27 F
47 nF
47 nF
33 nF
1
SUMMING AMPLIFIER
3-dB/OCTAVE FILTER
OUTPUT BUFFER
This simple circuit generates Gaussian-distributed noise for audio applications.
Code provides adjustable differential drive for robots

Alton Harkcom, EGO North America, Newnan, GA
ntelligently modifying the plication. It begins by initializing all the specify the ratio of right-to-left motor
motor-drive commands to a robot signals and then calibrating them with balance. Adjust variables (AdjustRaw,
can give you control finesse during the joystick at the idle position (MID) AdjustHI, AdjustLO, and Adjust) speccompetitions. Moving a joystick hard and each extreme (LO and HI). The ify the adjustment value to the ratio valright, for example, might have different code uses several sets of variables. ue. The adjustment reduces the ratio
effects, depending on the robots speed Drive variables (DriveRaw, DriveHI, value to better control left/right balance
and direction. Software running on an DriveMID, DriveLO, and Drive) speci- at particular speeds. Range-conversion
inexpensive microcontroller (in this fy the combined drive speed for the mo- variables (RangedUpper, RangedLower,
case, an NECPD78F9814) manages this tors. Ratio variables (RatioRaw, Ratio- and Ranged) rerange the ADC inputs to
control by calculating separate drive and HI, RatioMID, RatioLO, and Ratio) the desired 0 to 100% values for the moadjust vectors and then combining
tor speed and direction. After
the vectors and calculating the apthe code calculates the Left and
@ DRIVE
DRIVE@ RATIO
propriate power ratio for two tread
Right motor vectors, another
VECTOR
CALCULATION
* CALIBRATE
motors (Figure 1). This demonroutine uses these vectors to
stration system uses a simple treaddrive the motors. If Right is
DRIVE VECTOR
ed toy vehicle to show
greater than 1, for example, the
*ENGAGE
~ LEFT SPEED
how the ratio-drive con- F i g u r e 1
drive routine enables a RightMOTOR# LEFT DIRECTION (2)
COMBINED
COMBINED VECTOR
cept works and requires no sensors
Forward PWM signal and disRATIO
VECTOR
~
RIGHT
SPEED
CALCULATION
CALCULATION
in the vehicle. The microcontroller
ables the reverse signal. For ex# RIGHT DIRECTION (2)
controls the tread motors with
perimentation purposes, you
ADJUST VECTOR
simple forward/reverse signals
can use a 1A quad half-H
based on the calculated motor
bridge to route the speed and
NOTES: *=INTERRUPT.
@=ADC INPUT.
ADJUSTMENT#=DIGITAL INPUT OR OUTPUT.
speeds and directions.
direction signals to the motors.
@ADJUST
VECTOR
~=PWM OUTPUT.
&=COMMUNICATION DATA.
CALCULATION
$=DATA-TABLE VALUES.
Listing 1, which you can downIn actual competitions, you
(0 TO 9)=NUMBER OF CONNECTIONS.
load from the Web version of this
need a heavier duty motor conDesign Idea at www.edn.com, An NEC microcontroller calculates the appropriate power
troller because the motor-stall
shows the main routine for this ap- ratios for two tread motors in a robot.
currents can exceed 1A.
P42
EDN B E S T
OF
www.edn.com
CHANGE is the only constant.

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2004 Electronics Workbench. All rights reserved.
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The best of
test
Interface a serial 12-bit ADC to a PC
5V
DS Oberoi and Harinder Dhingra, GCET, Jammu, India

ver the years, IC vendors have
devised various ways of effecting interfaces and paying special attention
to reducing the number of ICs interfaceI/O pins. The MAX187 is one such device, a 12-bit A/D converter. You can create an interface to this ADC using serial
data-communications techniques. Analog-to-digital conversion and data transfer from MAX187 require only three digital-I/O lines. You can create a simple
interface between the MAX187 and a PC
using the computers Centronics printer
port (Figure 1).You enable or disable the
MAX187 by setting the SHDN pin (Pin
3) to high or low level, respectively. If you
leave this pin open, then the internal reference (4.096V) becomes disabled, and
you must apply an external voltage reference to REF (Pin 4). Otherwise, this pin
connects to a 4.7-F bypass capacitor, C1.
C3
10 F
C2
0.1 F
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
P1
The digital data from

Figure 1
1
the MAX187 transfers
V
3
to the processing unit one
SCLK 8
SHDN
bit at a time by using an
IC
external clock at SCLK
7
MAX187
CS
(Pin 8).
A complete data trans2
6
V
DOUT
AIN
fer requires 13 external
clock pulses. The first
REF
GND
clock pulses falling edge
4
5
latches the first data bit
C
4.7 F
(the MSB) at the DOUT
pin (Pin 6). The output
data bit changes at the
falling edge of the next exIts easy to effect an interface of a 12-bit serial ADC to a PC.
ternal clock, and you can
read the serial data bits until the appear- state until the complete cycle of converance of the falling edge of the next clock sion and subsequent serial-data transfer
cycles. The analog-to-digital conversion has taken place. A change of state in the
starts when the ADCs CS pin (Pin 7)
(Interface contd on P46)
goes low. This pin must remain in the low
DD
IN
High-side current sensor monitors negative rail

Ken Yang, Maxim Integrated Products, Sunnyvale, CA
ll dedicated current-sense am- to load current flowing to ground, not to output by at least 1.2V. If, for instance,
plifiers provide high-side sensing on the GND pin. Output resistor ROUT con- the full-scale output is 1V, then
a positive supply, but you can adapt verts the current to a voltage, which an V 2.2V. To meet the devices maximum and minimum operating voltages,
such circuits for monitoring a negative optional ADC then digitizes.
Saturation in the internal transistors, 0VEE(32V ), and ((V )
supply (Figure 1). The positive-supply
pin, V , connects to the systems posi- which occurs at approximately ((V ) VEE))3V. Figure 2 shows the variation
tive supply, and the ground pin, GND, 1.2V), limits the maximum output volt- of current measurement accuracy with
connects to the negative supply, VEE. age. Thus,V must exceed the full-scale load current.
That arrangement
monitors the negaFigure 1
Figure 2
R
tive supply and pro0.2
vides a positive out0
R =0.2, R =500,
+
V
put voltage for the
V =3.3V, V =5V.
(32VV+) TO 1V
_
1
external interface
2
1
RS+
RS
typically, an A/D
LOAD
SENSING 2
5
converter. The RS
ERROR
GND
(%)
IC
3
pin of the current8
MAX4172
V+
A/D
sense amplifier, IC1,
CONVERTER
+
V+
4
6
2.2 TO 5V
connects to the load,
OUT
_
and the RS pin
R
5
0
0.2
0.4
0.6
0.8
1
connects to the negLOAD CURRENT (A)
ative supply. IC1s
current-source outConnecting this positive-supply monitor allows it to moniThe current-sensing error of the circuit in Figure 1
put drives a current
tor a negative current and generate a positive output voltvaries with load current.
that is proportional
age for the ADC.
OUT
EE
EE
OUT
P44
EDN B E S T
OF
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ail 7.1
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General-purpose
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flexibility to measurements
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Tone
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(Prevent contd from P22)
2. Select an appropriate value for capacitor C2, which sets the filters differential (signal) bandwidth. Set this value
as low as possible without attenuating
the input signal. A differential bandwidth of 10 times the highest signal frequency is usually adequate.
3. Select values for capacitors C1A and
C1B, which set the common-mode bandwidth. For decent ac common-mode rejection, these capacitors should have values 10% or lower of the value of C2. The
common-mode bandwidth should al-
Figure 2
INSTRUMENTATION
AMPLIFIER
sides. All component leads

should be as short as possible.
C2
VOUT
Resistors R1 and R2 can be comIN
mon 1% metal-film units.
R1B
C1B
However, all three capacitors
need to be reasonably high-Q,
Capacitor C2 shunts C1A/C1B and reduces ac
low-loss components. Capacicommon-mode-rejection errors arising from
tors C1A and C1B need to be
component mismatch.
5%-tolerance devices to avoid
ways be less than 10% of the instru- degrading the circuits common-mode rementation amplifiers bandwidth at uni- jection.Good choices are the traditional 5%
ty gain.
silver micas, miniature micas, or the new
You should build the RFI filter using a Panasonic 2% PPS film capacitors (Digipc board with a ground plane on both key part number PS1H102G-ND).
R1A
C1A
+IN
(Interface contd from P44)

(Grounded resistor contd from P26)
positive-feedback circuit to be
R2/(R2 R3), you obtain the oscillation
condition in the form d1/d2
2
C2/C1/(2
C2/C1
C1/C2). The
oscillation condition does not depend
on R1. It thus becomes obvious that
controlling grounded resistor R1 results
only in the variation of the oscillation
frequency and does not affect the condition for oscillation. This situation
means that you can tune this oscillator
over a wide range of frequencies, preserving the output waveform.
PSpice simulations prove the possi-
(Make noise contd from P42)
of an infinite number of noise sources

has Gaussian distribution, regardless of
the individual noise distribution of each
generator.) Using an infinite number of
noise generators is impractical,but 10 to
16 are sufficient in most cases. And, because the smallest member of the PIC
family is an inexpensive chip with low
current consumption, the circuit is easy
to realize.
All noise generators run the same
program (Listing 1 on the Web version
of this Design Idea at www.edn.com).
Perfectionists might program each PIC
with an individual initial value for the
shift register, but, because all controllers
run uncorrelated with their own inter-
P46
EDN B E S T
OF
bility of tuning the oscillation frequency over three decades (20 Hz to 20 kHz)
by varying R1 from 1.2 M to 1.2 k.
This design uses an LT1361 (www.
linear.com) for IC2, R21 k, R34.9
k, C110 nF, C21 nF, and FS500
kHz. The output-voltage amplitude is
3.2 to 3.3V. The total harmonic distortion in the 0- to 100-kHz band does not
exceed 3%. Its useful to note that, because the oscillation frequency is proportional to the conductance of the
variable resistor (G11/R1), you can
use the oscillator as a linear, wideband
conductance-to-frequency or resistance-to-period converter.
nal oscillators and start out of reset at

different times, this measure is unnecessary. Op amp IC1A sums and levelshifts the noise signals. Summing resistors R1 and R2 must have a value of 10
k times the number of noise generators you use. The output signal of IC1A
feeds a 3-dB/octave filter to obtain
pink noise.Buffer IC1B decouples the filter and provides low output impedance.
The signal amplitude is approximately
400 mV p-p with a flat spectral distribution of 20 Hz to 20 kHz. Closing S1
or applying a low level at pin GP4 immediately stops all noise generators and
freezes the prevailing signal amplitude.
You can download the PIC software
from the Web version of this Design Idea
at www.edn.com.
DOUT pin from low to high level indicates the EOC (end-of-conversion) status. Then, serial 12-bit data is available for
transfer. Software controls the MAX187s
operation. The software should be able to
generate all the control signals for successful conversion and also should be able
to detect the EOC status. It should also
be able to generate 13 external clock pulses to read serial 12-bit data and convert it
into parallel data.
The software for the MAX187s operation is in Turbo C , Version 3.0
(which you can download from the Web
version of this Design Idea at www.
edn.com). In the code, Port defines the
Centronics port of the PC to which the
MAX187 interfaces. Write Port defines
the port for initiating the analog-to-digital conversion and generating the external clock pulses. Read Port defines the
port for reading the EOC and serial data
from the ADC. After pulling CS and
SCLK low, the EOC loop checks for the
EOC status. If a valid EOC does not appear, this loop remains operational. As
soon as a valid EOC appears, the first of
the 13 clock cycles appears, which latches the first data bit (MSB). After this action, the routine calls a subroutine
(get_adc()). The subroutine generates
the rest of the external clock cycles to read
the 12 bits of serial data. The function
also converts the received serial data into
parallel data (adc_val). It converts by
multiplying the previous data by two by
shifting adc_val to the left by one bit and
adding one to the parallel data if the serial bits value is one. Once the parallel
data is available, the function returns the
value and displays it on the screen.
www.edn.com
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