EXPERIMENT No 1

Half Adder / Full Adder and Half Subtractor / Full Subtractor

Aim: (a) Realization of half /full adder using logic gates
(b) Realization half/full subtractor using logic gates
Components required:Sl.N
o
1
2
3
4
5
6
7
8
9

Name of
The
Compone
nt
AND gate
OR gate
Not gate
EXOR
gate
NAND
gate
NOR gate
Patch
chords
Trainer
Kit

IC
Numbe
r

Quantit
y

7408
7432
7404
7486
7400
7402

1
1
1
3
3
3

(a) ADDER
Theory:
An Adder is a circuit which performs addition of binary numbers
Producing sum and carry. An half adder is a digital circuit which performs
addition of two binary numbers which are one bit each and produces a sum and
a carry(one bit each). A full adder is a digital circuit which performs addition of
three binary numbers (one bit each), to produce a sum and a carry(one bit
each). A Full adders are basic block of any adder circuit as they add two
numbers along with the carry from the previous addition.
The basic rules of binary addition are
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = (10)2
Column by column addition, similar to decimal addition is performed a logic circuit known as
half adder adds two 1 bit signals. In actual addition there is often a third bit, the carry bit that
must be added. Hence to add 3 bits at a time a logic circuit known as a Full adder is used.

Half Adder
a Half Adder Using Logic Gates
Block Diagram

Logic Diagram

Half Adder Using NAND Gates

Half Adder Using NOR Gates

Truth Table

A
0
0
1
1

B
0
1
0
1

Sum
0
1
1
0

Carry
0
0
0
1

Full Adder
Block Diagram

(a) Full Adder Using Logic Gates

Truth
Table (Full

Cin

A
0
0
0
0
1
1
1
1

B Cin Sum
0 0
0
0 1
1
1 0
1
1 1
0
0 0
1
0 1
0
1 0
0
1 1
1

Cout
0
0
0
1
0
1
1
1

Adder)

(b) Full Adder Using NAND Gates

(c) Full Adder Using NOR Gates

Procedure:1. Place the IC in the socket of the trainer kit.

2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for half adder and full adder circuits using basic and universal
gates.
(b) SUBTRACTORS
Theory:
Subtractors are digital circuits which perform subtraction of binary
numbers to produce a difference and a borrow if any. A half subtractor subtracts
two one bit numbers to give their difference and a borrow if any. A full
subtractor subtracts two one bit numbers along with a borrow (from previous
stage) to generate a difference and a borrow.
Half Subtractor
Block Diagram

(a) Half Subtractor using Logic Gates

Truth Table
A B
Diff
0
0
0
0
1
1
1
0
1
1
1
0

Logic Diagram
Borrow
0
1
0
0

(b) Half Subtractor Using NAND gates

(c) Half Subtractor Using NOR gates

Full Subtractor
Block Diagram

(a) Full Subtractor Using Logic Gates

Truth Table
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Bin
0
1
0
1
0
1
0
1

Diff
0
1
1
0
1
0
0
1

Borrow
0
1
1
1
0
0
0
1

Bin

(b) Full Subtractor Using NAND Gates

A
B
Bin

(c) Full Subtractor Using NOR Gates

Procedure:1. Place the IC in the socket of the trainer kit.

(complex boolean Expressions are simplified by using Kmaps).
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for half subtractor and full subtractor circuits using basic and
universal gates.
Result: Realized both half Adder and Subtractor and full Adder and Subtractor circuits
using basic and universal

EXPERIMENT-4
Binary to Gray Code Conversion and Vice Versa
Aim: Realization of Binary to Gray code conversion and viceversa
Components Required:Sl.No
1

Name of The
Component
EXOR gate

IC Number

Quantity

7486

2
3
4

NAND gate
Patch chords
Trainer Kit

7400

Theory:
The reflected binary code, also known as Gray code after Frank Gray, is a binary
numeral system where two successive values differ in only one digit. The reflected binary
code was originally designed to prevent spurious output from electromechanical
switches. Today, Gray codes are widely used to facilitate error correction in digital
communications. . Gray codes are used in position encoders (linear encoders and rotary
encoders), in preference to straightforward binary encoding. This avoids the possibility
that, when several bits change in the binary representation of an angle, a misread could
result from some of the bits changing before others. Rotary encoders benefit from the
cyclic nature of Gray codes, because the first and last values of the sequence differ by
only one bit. Gray codes are also used in labeling the axes of maps
(1) Binary to Gray code converter
Truth Table
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

BINARY
B2
B1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

G3 = (8,9,10,11,12,13,14,15)

B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

GRAY CODE
G2
G1
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0

G0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

G2 = (4,5,6,7,8,9,10,11)

G1= (2,3,4,5,10.,11,12,13)

(a)

G0 = (1,2,3,5,6,9,10,13,14)

Binary to Gray code converter Using XOR Gates Only

(b)
converter Using NAND Gates only

Binary to Gray code

(2) Gray to Binary converter

G3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

GRAY CODE
G2
G1
G0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

BINARY CODE
B2
B1
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1

B0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0

(a) Logic Diagram for Gray to Binary

(b) Gray to Binary Using NAND Gate

Procedure:1. Place the ICs in the socket of the trainer kit.

2. Make connections for the gate as shown in the circuit diagram.
3. Apply different combinations of the input according to the truth table and verify
the corresponding outputs as shown in the truth table.
Result: Realized both Binary to Gray code conversion and viceversa .

EXPERIMENT NO-8
FLIP-FLOPS
Aim: - Truth Table verification of flip-flops
(i) JK Master slave (ii) T type (iii) D type.
Theory:
Sequential circuits employ storage elements in addition to logic gates. Their
outputs are a function of the inputs and the state of the storage elements. The state of the
storage elements, in turn is a function of the previous inputs. As a consequence, the
outputs of a sequential circuit depend not only on present values of inputs, but also a past
inputs and the circuit behavior must be specified by a time sequence of inputs and
internal states.
A Flip-Flop circuit can maintain a binary state indefinitely until directed by an
input signal to switch states. The major differences among various types are in the
number of inputs they possess and in the manner in which the inputs affect the binary
state.
Components Required:-

(a)

Sl.No

Name of The
Component

IC
Number

Quantity

1
2
3
4
5

Dual J.K FlipFlop

NAND gate
NOT gate
Patch chords
Trainer Kit

7476
7400
7404

1
1
1

J-K Flip flop :-

Symbol of MS-JK FF

Pin Diagram

Logic Diagram:

Truth Table
Table 1
Inputs
Clk Cr pr
1
1 1

Output
Q
Qn+1

Operation Performed
Normal FF(Table-2)
(F.F. enabled)

F.F. Cleared(Reset)

F.F. Preset(Set)

Note: - Keep Pr= Cr=1 for verifying the

truth tables JK MS F.F, T and D type FF.

Table 2
Clk
0

Inputs
J
K
X

Output
Qn+1

COMMENTS

Qn

No Change

Qn

No change

Reset

Qn

Set
Toggle

(b)

T- Type FF using MS JK FF

(c ) D - Type FF using MS JK FF

Procedure:1) Rig up the circuit as shown in the diagram.

2) Apply the i/p to these flip-flops as per the Truth table and observe the o/p
3) Verify with the truth table.
Result: Realized truth table of all flip-flop.

EXPERIMENT-9
COUNTERS
Aim -Realization of 3-bit counters as a sequential circuit and mod-N counter design
(7476, 7490, 74192, 74193)

1) Asynchronous type

2) Synchronous type

Theory:
A counter is essentially a register that goes through a pre-determined sequence of
states. The gates in the counter are selected in such a way as to produce the prescribed
sequence of binary states.
Counters are available in two categories: Ripple counters (asynchronous) and
synchronous counters. In a ripple counter, the flip-flop output transition serves as a
source for triggering other flip-flops. In otherwords, the input of some or all the flip-flops
are triggered not by the common clock pulses rather by the transition that occurs in other
flip-flops outputs. In a synchronous counter, the inputs of all flip-flops receive the
common clock.
Components Required:-

Sl.No
1
2
3
4
5
6

Name of The
Component
JK flip flop
NANDgate(3 pin)
AND gate
OR gate
Decade Counter
Decade Up/down
Counter
MOD 16 counter
Patch chords
Trainer Kit

IC Number

Quantity

7476
7408
7432
7490
74192

2
2
1
1
1
1

74193

(1) Realization of 3-bit binary Asynchronous counters using IC7476

Pin Diagram

Number of
Flip Flop outputs
Truth Table for
clock pulses
Qc
Qb
Qa
Truth Table for
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
0
0
0
Number of
clock pulses
0
1
1
1
2
1
3
1
4
0
5
0
6
0
7
0
8
1

Flip Flop
outputs
Qc
Qb
Qa

1
1
0
0
1
1
0
0
1

Up Counters
Down Counters

1
0
1
0
1
0
1
0
1

(a) 3-Bit Asynchronous UP Counter

(b) 3-Bit Asynchronous Down Counter

(c ) Realization of MOD 4 Counter

Truth Table
Number of clock
pulses
0
1
2
3

Flip Flop outputs

Qc
Qb
Qa
0
0
0
0

0
0
1
1

0
1
0
1

(2) Realization of 3 Bit Synchronous Counter Using IC7476

(a) 3-Bit Synchronous UP Counter
Truth Table
Present State

Next State

Excitation

Qc

Qb

Qa

Qc

Qb

Qa

Jc

Kc

Jb

Kb

Ja

Ka

Simplification:

Present State

Next State

Excitation

(b)

Qc

Qb

Qa

Qc

Qb

Qa

Jc

Kc

Jb

Kb

Ja

Ka

3-

0
0
0
1
1
Bit Synchronous Down Counter

Truth Table

Simplification

(3) Realization of MOD N Counters Using IC7490

Pin Diagram of IC7490

Internal Diagram

Functional Table
R1

R2

S1

S2

Qd

Qc

Qb

Qa

MOD-2 COUNTER

MOD-5 COUNTER

(a) 7490 AS MOD-2 / MOD-5 COUNTER

(b) 7490 AS MOD-10 COUNTER

(c) 7490 AS MOD-8 COUNTER

(d) 7490 AS MOD-6 COUNTER

(4) Realization of MOD N Counters Using IC-74193

Pin details of IC 74193(Synchronous counter)
[MOD-16 UP/DOWN COUNTER]

Functional Table:

H
L
L
L
L

Load

Up

Down

Qd

X
L
H
H
H

X
X
Cp
H
H

X
X
H
Cp
H

0
D

Qc

Qb

Qa

0
0
0
C
B
A
COUNT UP
COUNT DOWN
NO CHANGE

(a) Realize a counter which counts from (6-12) Using IC 74193

Invalid state 1101

(b) Realize a counter which counts from (15-6) Using IC 74193

Invalid state---0101
Note:-Lo and Bo are used basically for cascading the counters
(5) Realize a MOD-N counter using IC74192 Synchronous Counter
Pin Details of IC-74192

(a) MOD-6 UP COUNTER: Invalid state o110

(b) 3 to 9 Counter

Procedure:1) Rig up the circuit as shown in the diagram.

2) Apply the inputs to these counters as per the Truth table and observe the o/p
verify with the truth table.

Result: Realized truth table of all Counters.

Experiment No. 10
Schmitt Trigger
Aim:
Design and test the Schmitt trigger for the given value of LTP and UTP.

Components and Equipments Required:

A 741op-amp, Resistors, Bred Board, Diode, Dual Power Supply, Function Generator
and CRO.
THEORY:
Schmitt Trigger is also known as Regenerative Comparator. This is a square wave
generator which generates a square based on the positive feedback applied. As shown in the fig.
below, the feedback voltage is Va. The input voltage is applied to the inverting terminal and the

feedback voltage is applied to the non-inverting terminal. In this circuit the op-amp acts as a
comparator. It compares the potentials at two input terminals. Here the output shifts between +
Vsat and Vsat. When the input voltage is greater than Va, the output shifts to Vsat and when
the input voltage is less than Va, the output shifts to + Vsat. Such a comparator circuit exhibits a
curve known as Hysterisis curve which is a plot of Vin vs V0. The input voltage at which the
output changes from + Vsat to Vsat is called Upper Threshold Point (UTP) and the input
voltage at which the output shifts from Vsat to + Vsat is called Lower Threshold Point (LTP).
The feedback voltage Va depends on the output voltage as well as the reference voltage. A Zero
Cross Detector is also a comparator where op-amp compares the input voltage with the ground
level. The output is a square wave and inverted form of the input.

Circuit Diagram:

+12V
741

10V(p-p)
1kHz,
m(t)

-12V

V0
R1 = 90k

R2 = 10k
VREF = 3.3V

Design:
V UT =
V =

R1
(+V sat )
R1 + R 2

R1
(V sat )
R 1 + R2

UTP = 4V and LTP = 2V

R1
R2
UTP=
V ref +
V
R1 + R 2
R1 + R2 sat
LTP=

R1
R2
V ref
V
R 1+ R2
R 1+ R 2 sat

UTP+ LTP=

2 R1
V
R1 + R2 ref

(1)

UTPLTP=

2 R2
V
R1 + R2 sat

(2)

From Equation (2)

2 R (10)
42= 2
R1 +R2

From Equation (1)

R +R
V ref = 1 2 (UTP + LTP)
2 R1

R1 = 9R2
R2 = 10kHz
R1 = 9kHz

Vref = 3.3V

Waveforms:

Vin
4V

5V

2V

-5V
UTP

+Vsat
0
-Vsat
V0

LTP
4V

2V

Vin
UTP
LTP
Procedure:
1. Before wiring the circuit, check all the components using multimeter and IC tester.
2. Make the connections as shown in circuit diagram, figure (j).
3. Set the signal generator (input voltage) amplitude say 10 V(p-p) and observe the input(V in) and
output(V0) signals of the circuit simultaneously on CRO screen.
4. Feed Schmitt trigger output to y channel and input to x channel, and set x-y mode to observe
the hysteresis curve on the CRO.
5. Plot the graph.

Result:

Observation

Experiment No. 5
Astable Asymmetrical Multivibrator
Aim:
Design and test astable multivibrator, (Asymmetrical) using 555 timer.

Components and Equipments Required:

555 Timer, Resistors, Capacitors, Bred Board, Power Supply, Function Generator and
CRO.
THEORY: A 555 timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations, some of the applications of 555 are square wave generator, astable
and monostable multivibrator. Astable multivibrator is a free running oscillator has two quasi
stable state in one state o/p voltage remains low for a time interval of Toff and then switches over
to other state in which the o/p remains high for an interval of Ton the time interval Ton and Toff
are determined by the external resistors a capacitor and it does not require an external trigger,
when the power is switched on the timing capacitor begins to charge towards 2/3 Vcc through
RA & RB, when the capacitor voltage has reached this value, the upper comparator of the timer
triggers the flip flop in it and the capacitor begins to discharge through RB when the capacitor
voltage reaches 1/3 Vcc the lower comparator is triggered and another cycle begins, the charging
and discharging cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and discharging
periods t1and t2 respectively. Since the capacitor charges through RA and RB and discharges
through RB only the charge and discharge are not equal as a consequence the output is not a
symmetrical square wave and the multivibrator is called an asymmetric astable multivibrator

Circuit Diagram:
VCC = 5V

RA=6.8k

8
7

RB=3.6k

4
555
Timer
3
V0

2
6
1
C=0.1F

Design:
f = 1 kHz, T = 1/ f = 1ms.
TON = 0.75ms, TOFF = 0.25ms.
C = 0.1F
TON = 0.693(RA + RB) C
TOFF = 0.693(RB) C
0.75ms = 0.693(RA + RB) C
0.25ms = 0.693(RB) C
RB = 3.6k
0.75 ms
R A + R B=
=10.82 k
0.693 0.1 F
RA = 10.82k RB = 7.2k ( 6.8 k)
RB = 3.6k

5
C=0.01F

Waveforms:

0.25ms

0.75ms

Procedure:
1. Make the circuit connections as shown in circuit diagram, figure (e).
2. Switch on the power supply.
3. Observe the output on the CRO.
4. By varying the RA pot, adjust the TON period near to 0.75ms.
5. Similarly by varying the RB pot, adjust the TOFF period.
6. Observe the voltage across capacitor (VC) at pin no. 2 or 6.
7. Plot the output waveform and voltage across capacitors with respect to time.

Result: