Electromagnetic Modelling of Microwave Packages

Author: Manoj Kumar Shrestha

Supervisor : Dr. Peter Aaen, John Atherton(Industrial Supervisor)

1. ABSTRACT
The objective of this project is to predict effects of packaging on high frequency GaAs integrated circuit using
electromagnetic simulations. The simulation approach will be validated with measured S-parameters up to 40 GHz.
The development of the proposed modelling, measurement, and simulation capabilities will help designers predict
the performance of packaged microwave power transistors before manufacture. The project will develop these
methods for quad-flat no-lead (QFN) packages.
Industrial Sponsor
WIN Semiconductor Inc. is the leading global provider of GaAs wafer services for the wireless, infrastructure and
networking markets. It has established two advanced GaAs wafer fabs for low cost manufacturing of high speed and
high quality GaAs ICs (monolithic microwave ICs) and FICs (radio frequency ICs). Win provides foundry
services to design houses as well as ID partners. Dr. ohn Atherton from WIN is the industrial supervisor for the
project. WIN Semiconductor is providing support for manufacturing of all test-fixtures, packaged devices, probes and
materials to perform these measurements in our laboratories. The cost of this support is valued at over 5k and
there will be no costs incurred to the University during this study.

2. SCOPES AND OBJECTIVES

Develop an electromagnetic modelling method: ackage mechanical drawing will be provided by WIN
semiconductors to create D-model. Epro simulation environment will be setup using material properties and
CB details for the imported model. The model will be used to design validation test structures. The validation test
structures will include empty packages; wires shorted to the flange and packaged high Q-capacitance.
Develop an S-parameter test-fixture to create a CB test fixture and calibration standards: The impedance and
output power measurements of QFNs are always a problem due to their low impedance and lead widths. A thrureflect line calibration technique will be devised to measure the device under test. The individual two port Sparameters of each fixture half will be obtained. By de-embedding the S-parameters of a test fixture an accurate
calibration can be made. TL calibration technique will be used in collaboration with end launch connectors to
establish accurate reference planes for the comparison of simulation results.
After the test structure is manufactured, it will be used to compare the data between measured and simulated
results.

Stretch Goal:
Extraction of equivalent circuit of the finalized model and simulation of a packaged IC circuit will be carried out
if project objective is met ahead of time; where package modelling method will be used along with a small/large
scale signal model of the IC to demonstrate the validity of the approach.

4. TRL CALIBRATION , DE-EMBEDDING AND IMPLEMENTATION USING CONDUCTOR

BACKED CO-PLANAR WAVEGUIDE

hysical Structure
of CBCW

Block Diagram of Test Fixture

Conductor Backed Co-planar

Waveguide(CBCBW)
Contains center strip and two
ground planes on either side plus
one on the bottom of the substrate.
Consists of three modes of
propagation Co-planar wave
mode, icro-strip mode and
arallel plate mode.

De-embedding

= 1

5. MOMENTUM VISUALIZATION OF TRL STANDARDS

Current Density pictured for TL

standards at 40 GHz

6. RETURN LOSS PLOT FOR ALL TRL STANDARDS

3. BACKGROUND & INTRODUCTION

Quad flat no-lead packages are designed for surface mount manufacturing techniques used in low cost high volume
production of ICs. ackages are used for handling fragile die and for environmental protection. The QFN package
is a plastic encapsulated package with a copper lead frame. It is a leadless package where electrical contact to the
CB is made by soldering the leads on bottom surface of the package. As the leads are embedded in the plastic it
prevents from bending during the assembly attachment. The semiconductors that are packaged often dissipate heat
and the exposed copper paddle allows heat to be conducted downwards away from the chip. These copper paddles
acts as good F ground as well as means to control the parasitic environment.
Computer-aided design methodologies are used in design of
complex wireless systems to reduce time and increase design
robustness and this model will allow WIN customer to use
a full CAD-based design methodology. Once the model is
finalized the final step will be comparing the results
QFN package, cross-sectional view and layout on PCB. [1,2]
between the simulated version and measured version.
Electromagnetic professional (Epro) is software design
platform for analysing the D electromagnetic effects f components which includes high speed packages, bond wires,
antennas. It uses finite element analysis (FE) for analysing and characterizing electronic packaging structures.
Simulation is numerical analysis methods that solve electromagnetic field distribution problems described by axwells
equation.

Theoretical Analysis to calculate

the modes of CBCW : =
0
2

Current Density for LINE standard at 10 GHz(left) and 40

GHz (ight), eturn Loss chart showing resonance above 22
GHz (Design by WIN semiconductors).

Three different types of

modes of propagation in
CBCW

eturn Loss plot for all TL standards

In the above diagram we can see that the return loss for TRL standards are performing are well up to 40 GHz as the return
loss is confined below -10 dB for both THRU and LINE case.

8. BIBLIOGRAPHY
[1] Toshiba Electronics Europe , Available at http://www.toshiba-components.com/ASIC/QFN.html (Accessed: 17th April
2014)
[ [] .N. Simons, Coplanar Waveguide Circuits, Components and Systems, ohn Wiley Sons, New ork, N 2001
[4] Scott A. Watenberg . F measurements of Die and ackages, Artech House,1 an 2002, Technology Engineering.
[5] Wen-Teng To, Ching-Kunang C. Tzuang, S. T. eng, Ching-Cheng Tien, Chung-Chi Chang, and enq-Wen Huang,
esonant henomenon in Conductor-Backed Coplanar Waveguides (CBCWs), in IEEE Transactions on icrowave
Theory and Techniques VOL 41, No. 12, December 199
[6] OHN COONOD, ogers Corp, Chandler, AZ , BIAN AUTIO, Sonnet Software Inc., North Syracuse, N,
Comparing icrostrip and CW performance , in icrowave ournal , uly 2012
[7] Nirod K. Das, ethods of Suppression or Avoidance of parallel-late ower Leakage from Conductor-Backed
Transmission Lines, in IEEE Transactions on icrowave Theory and Techniques, VOL 44, No 2, February 1996
[] Aladdin H. Assisi, Applying Electromagnetic Simulation to Optimize Via Hole Separation in a Conductor-Backed
Coplanar Waveguide, in 26th National adio Science Conference (NSC2009), arch 17-19, 2009
[9] ick Sturdivant, icrowave and illimter Wave Electronic ackaging, Artech House, 1 Dec 201
[10] David . ozar, icrowave Engineering, rd Edition, New ork, ohn Wiley Sons, Inc , 2005
[11] Felix D. bairi Hjalmar Hesselbom, High Frequency Design and Characterization of SU- based Coplanar Backed
Coplanar Waveguide Transmission Lines, id Sweden University, Campus Ostersund, Department of Information
Technology and edia (IT).

Where,
r = Dielectric constant of the
substrate.
Wppl =
Width of the Ground lane.
Lppl= Length of the Ground plane.
m,n = number of modes.

7. CONCLUSIONS
In the above work we have
analysed the design provided by
the WIN semiconductors and with
the help to electromagnetic
simulation software ADS studied
the electromagnetic behaviour
shown within our frequency range
up to 40 GHz. We have understood
that the resonance behaviour
shown in Conductor Backed Coplanar Waveguide is implanted to
design calibration kit is due to
parallel-plate modes for which the
area of ground plane is responsible.
As in our optimized design we have
reduced the width of the ground
plane to 1 mm and pushed the
lower order frequency mode above
our working frequency range. This
can be also verified from the
simulated results.