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Assistant Professor, 2Associate Professor, Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, India,
bharathi891@gmail.com, dlrani79@gmail.com
Abstract
Digital signal processing, Digital control systems, Telecommunication, Audio and Video processing are important applications in
VLSI. Design and implementation of DSP systems with advances in VLSI demands low power, efficiency in energy, portability,
reliability and miniaturization. In digital signal processing, linear-time invariant systems are important sub-class of systems and are
the heart and soul of DSP.
In many application areas, linear and circular convolution are fundamental computations. Convolution with very long sequences is
often required. Discrete linear convolution of two finite-length and infinite length sequences using circular convolution on for
Overlap-Add and Overlap-Save methods can be computed. In real-time signal processing, circular convolution is much more
effective than linear convolution. Circular convolution is simpler to compute and produces less output samples compared to linear
convolution. Also linear convolution can be computed from circular convolution. In this paper, both linear, circular convolutions are
performed using vedic multiplier architecture based on vertical and cross wise algorithm of Urdhva-Tiryabhyam. The implementation
uses hierarchical design approach which leads to improvement in computational speed, power reduction, minimization in hardware
resources and area. Coding is done using Verilog HDL. Simulation and synthesis are performed using Xilinx FPGA.
Keywords: Linear and Circular convolution, Urdhva - Tiryagbhyam, carry save multiplier, Overlap Add/ Save Verilog
HDL.
----------------------------------------------------------------------***----------------------------------------------------------------------1. INTRODUCTION
2. CIRCULAR CONVOLUTION
N 1
X 1 K x1 n e j 2 nk / N
k= 0, 1 N-1
(1)
k= 0, 1 N-1
(2)
n 0
N 1
X 2 K x2 n e j 2 nk / N
n 0
k=0,1,N-1
(3)
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
654
N 1
x3 n x1 n x2 m n N m=0,1 N-1
(4)
n 0
Here
x m n N x m n N
(5)
x2 0
....... x2 2 x1 1 x3 1
x2 1
......
... ....
x
N
1
x
N
2
.......
x
0
2
2
2
x1 N 1 x3 N 1
(6)
DURATION SEQUENCE
In discrete time, the output sequence y[n] of a linear time
invariant system, with impulse response h[n] due to any input
sequence x[n] is the convolution sum of x[n] with h[n] and is
given as
y n x n * h n x k h n k
(7)
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
655
Let the length of input and impulse sequences, x[n] and h[n] be
L and M. The starting time of input and impulse sequences are
represented by n1 and n2 respectively.
x(L-M+1) x(L-1) are the last (M-1) samples and from x1(n)
and x(L0 x(2L-1) are L new samples
and
y n x k h n k
(8)
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
656
Example
Multiplication of 1234 and 2116
Adder
5. MULTIPLICATION TECHNIQUE
Jagadguru Swami Sri Bharati-Krishna Swamiji introduced his
research on mathematics based on sixteen sutras for
multiplication. A multiplier is the key block in Digital Signal
processing. In the increasing technology, researchers are trying
to design multipliers which offer high computational speed, less
delay, low power and area efficient arithmetic building blocks
[7].
1 2
2 5
1 1
9 9
2
4
2 6
1 1
1 2
Step1:
(3x6) + (4x1) = 22. 2, the carry is placed below the third digit.
Step3:
Normal multiplier
Vedic multiplier
Step4:
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
657
Step6:
1
(1x 2)=2.
Impulse sequence is h(n)= [h3,h2,h1,h0]
6. SIMULATION RESULTS
6.1. Circular Convolution
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
658
CONCLUSIONS
The example taken here is
x(n)= [ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12] (Decimal format)
h(n)= [4,5 ] (Decimal format)
y(n)= [8h 3C,8h67,8h5E,8h55,8h4C,8h43,8h3A,8h31,
8h28,8h1F,8h16,8h0D,8h04 ]
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Fig. 5 Linear convolution for long duration sequence OverlapSave method
[8]
[9]
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
659
BIOGRAPHIES:
Ms. M. Bharathi, M.tech, is currently
working as an Assistant Professor in ECE
department
of
Sree
Vidyanikethan
Engineering College, Tirupati. She has
completed M.tech in VLSI Design, in
Satyabhama University. Her research areas
are Digital System Design, VLSI Signal Processing.
Ms. D.Leela Rani received the M.Tech.
Degree from Sri Venkateswara University,
Tirupati. She is currently working towards
the Ph.D. degree in the Department of
Electronics and communication Engineering,
SVU College of Engineering,Tirupati.
Currently she is working as an Associate professor in Sree
Vidyanikethan Engineering College (Autonomous). Her
research areas include, Atmospheric Radar Signal Processing
and VLSI Signal Processing.
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Volume: 02 Issue: 11 | Nov-2013, Available @ http://www.ijret.org
660