A Low Leakage, Low Power Sample and Hold

Circuit

ECE501
Department of EECS, University of Tennessee
Knoxville, TN-37996

Project Report
by
Arnab Jyoti Baruah

Major Professor:
Dr. Jeremy Holleman
Masters Committee:
Dr. Syed Kamrul Islam
Dr. Nicole McFarlane

Abstract This project presents an ultra-low power sample and

hold circuit designed to be used in data processing systems. This
circuit was designed to minimize leakage currents during the circuits
hold mode. Previous designs for low-leakage sample and hold circuits
needed an additional voltage reference for the circuit. This work
eliminates the need for the additional reference while still achieving
low leakage. The circuit can operate at 100pW using a 1V power
supply. The tracking bandwidth of the circuit is 269Hz. When
sampling with a 500mV input range, the circuit exhibits an ENOB
(effective number of bits) of 7.2 bits.

INTRODUCTION
As the demand for connectivity increases in the world today, handheld
and portable electronic systems have seen a dramatic rise in production
and will continue to be used for more custom applications in the future. As
a direct consequence, such systems will have a limited power budget and
will require efficient power usage. While such systems will be
predominantly digital, real world interfacing (with analog components
such as A/D and D/A convertors) is still required. There will also be space
for novel analog computational blocks [1] which will help bring down the
total power consumption without compromising performance.
A key building block in such systems is a sample and hold circuit.
Earlier work [2] demonstrating low power and low leakage use structures
to minimize the leakage by minimizing the voltage across the drain-bulk
interface of the switching transistor. This was done by using an external
reference voltage to bias the body and drain/source terminal of the
switching transistor. In this project, we introduce a novel technique to
eliminate this extra reference voltage. We also demonstrate that this circuit
operates with two orders of magnitude less power than previously
published circuits [2][3], making it useful in ultra-low power designs.
I.

DESIGN DESCRIPTION
In [2], the leakage current at the drain of a switching transistor is divided
into two parts: diode leakage from the drain-bulk interface and
subthreshold conduction in the channel under the gate. The diode leakage
current is given by:
II.

= [ 1]

(1)

where is the diode current, is the voltage across the drain and
the bulk node, is the diode saturation current and is the thermal
voltage (~26 mV at 300K). Since diode current is a function of the voltage
across the diode, creating a virtual short across the diode terminals (the
switching transistors drain and bulk) minimizes the diode leakage current.
Subthreshold current is given by the following equation:
= 0

) . [1 (

)]

(2)

where I0 is a process dependent current. Since the gate overdrive is

already at the minimum value for a transistor switch that is turned off,
minimizing the drain-to-source voltage VDS represents the best strategy for
minimizing subthreshold conduction. Considering these two conditions,
the sample and hold circuit shown in Figure 1 was designed.
Circuit Description
The heart of the sample and hold circuit is the transistor M1. Either a
PFET or a triple well NFET could have been used for the switch as it was
required to drive the bulk node of the transistor. In this design a PFET was
chosen. Transistor M2 isolates the switch M1 from the input source.
During the sampling phase (when the signal Sample_bar is low),
switches M1 and M2 turn on and the input signal is sampled by capacitor
C1. Node A tracks the input signal as long as switches M1 and M2 are on.
Ideally, unity-gain buffer U1 drives transistor M1s bulk (node B) to the
same voltage as transistor M1s drain (node A). However, op-amp U1
introduces an offset. If the offset of the opamp is low, the voltage across
the parasitic drain-to-bulk diode will be on the order of a few millivolts,
minimizing the diode leakage.
A.

When the holding phase starts (Sample_bar switches high) switches M1

and M2 turn off. Also, NFET transistor M3 turns on, shorting switch M1s
source to its bulk. Since the virtual short between M1s drain and bulk
remains, M1s drain-to-source voltage is the offset of unity-gain buffer
U1s offset (a few millivolts). This small VDS (equation 2) minimizes M1s
subthreshold leakage during the holding phase. By minimizing both the
voltage across the M1s drain-to-bulk parasitic diode and the M1s drainto-source voltage, this circuit both minimizes leakage current and
maximizes the sample and hold circuits hold time. The bulk of M2 was
tied to Vdd as leakage from M2 didnt affect the held voltage on the
sampling capacitor C1.
Another unity-gain buffer U2 drives the signal stored on the capacitor
to the next block. While foregoing this buffer would further reduce the
power dissipation of the circuit, this buffer isolates the sample and hold
circuit from subsequent blocks. The sample and hold circuit can be used
as a unit cell in implementing a delay line for discrete-time systems.
Sample_bar

In

M1

M2

Vdd

Sample_bar

M3

Vdd

Vdd

C1

U2

Out

Vss

Vss

U1
Fig. 1 Schematic of the Sample and Hold circuit

Figure 3 shows the schematic of the opamp used. During the design
phase, the primary consideration was minimizing voltage droop at node A.
Since this specification is tied to the opamps offset, Monte Carlo (MC)
simulations were used to estimate the average voltage droop and leakage
current. These simulations were used to optimize the device sizes in the
opamp.

(a)

(b)
Fig. 2 (a)Monte Carlo simulation results for voltage droop for a holding a voltage of 416.2 mV for
140 ms.(b)Monte Carlo simulation results for leakage currents after 140 ms for holding a voltage of 416.2 mV

Figure 2 shows the results of a 200 point MC simulation to estimate the

average voltage droop and leakage current for a voltage of 416 mV held
for 140 ms. It can be seen that the 3 range for the leakage current and
voltage droop are -21 fA to 37 fA and -36 mV to 19 mV respectively.
Vdd
MD1,2

MC1,2
Out

Vdd
Inp

MB1,2

Inn

Iref
MA1

MA2

Fig. 3 Schematic of the Opamp

RESULTS
The circuit was implemented in 0.13 m CMOS technology. The supply
voltage of the circuit is 1 V. The sampling capacitor C1 is 153 fF.
III.

Power Consumption
The test board for the sample and hold circuit provided bias currents in
the nano-ampere range, which were subsequently scaled on-chip to tens of
pico-amperes. During measurement, the total current dissipation of the
circuit was 100 pA.
A.

Swing limits and Tracking Bandwidth

The swing limit of the output signal was limited by the output swing
limits of the opamps U1 and U2. As the input voltage of the sample and
hold circuit approaches the rails, the loop gain of the M1-U1 feedback loop
collapses. This leads to nonlinearity for voltages sampled near the rails.
Since project specifications did not dictate rail to rail signal inputs, the
range of this sample and hold was smaller than the supply. This limitation
can be remedied by using rail to rail opamps.
The circuit is capable of sampling inputs between 140.3 mV and
891.1 mV, giving it an output swing range of about 750 mV (Figure 4(a)).
However best results occurred between 250 mV to 750 mV, leading to an
output swing range of about 500mV centered at mid-supply. (Figure 4(b)).
B.

(a)

(b)

Fig. 4 Track and hold operation demonstration. The input signal is a 275 Hz sinewave sampled at twice the
Nyquist frequency: (a) operation over a range of 1 Vp-p input signal. (b) operation over a 500 mV range centered at
0.5 V (mid-supply).

The circuits bandwidth is limited by the bandwidth of the opamps during tracking
mode. In this case, it was observed to be about 269Hz using simulations (as shown
in Figure 5).

Fig. 5 Tracking mode frequency response of the circuit.

Voltage droop and leakage current

Leakage current is estimated based on voltage droop at the output node (which is
the buffered version of node A).
The equation used to estimate this current is

= [ ]
(3)

where is the total capacitance at node A. This value was calculated to be

~160 fF using simulations
In order to measure droop, the test setup had to create a long hold time. The
function generator was set to output a 10 mHz clock with a 20% duty cycle, giving
an 80 sec window for the capacitor C1 to discharge.
As expected from the simulations, the ability of the circuit to minimize leakage
was a function of the held voltage. The leakage is much more when the voltage is
closer to the supply rails as the opamps gain diminishes.
C.

Fig.6 Estimated leakage currents using voltage droop measurements for different sampled voltages across the
input dynamic range of the circuit.

ENOB and Noise measurements

To estimate the circuits accuracy in terms of estimated number of bits, an FFT
was taken of a sampled output. A 500 mV, 101 Hz signal input was sampled at
400 Hz. The output generated a 400 point FFT (1 Hz/bin), which was used to
calculate the signal to noise and distortion ratio (SNDR). The sample and hold circuit
achieved an SNDR of 45.2 dB, which translates to an estimated number of bits of
7.2 bits. The actual measured signal to noise ratio (SNR) is 47.76 dB and the
spurious free dynamic range (SFRD) is 52.31 dB. The noise floor is estimated to be
approximately 68.76 dB below the signal level.
D.

Fig. 7 A 400 point FFT showing the SNDR, SNR and SFDR.

The circuits noise during the tracking phase is dominated by flicker noise.
Noise measurements were made using the SR770 FFT Network Analyzer at
specific frequencies. This is illustrated in Figure 8.

Fig. 8 Noise measurements during tracking. (The dots represent measured points).

TABLE I.

PERFORMANCE COMPARISION
This work

[2]

[3]

Technology (m)

0.13

1.5

0.13

Supply voltage
(V)
Power(W)

3.3

0.6

100 1012

10 109

28 109

ENOB(bits)
SNR(dB)

7.2
47.76

9.6
73

CONCLUSION
This sample and hold circuit is demonstrated to work over a signal range of
750 mV with a 1 V power supply. The average power consumption of the circuit is
100 pW. For a signal swing range of 500 mV centered about mid-supply, the circuit
has 7.2 bits of accuracy. Over that swing limit, the leakage current in hold mode is
well below 10 fA, leading to seconds of hold time. These leakage currents are very
close to [2] for mid-rail voltages and vary by an order of magnitude over the chosen
dynamic range.
IV.

As mentioned previously, the leakage of the circuit is dependent on the held

voltage, getting worse near the supply rails. Replacing U1 and U2 with rail-to-rail
opamps will improve the dynamic range of the circuit.
Another way to improve the dynamic range of the circuit will be to use a
transmission gate instead of M1 as the switch, allowing sampling of rail-to-rail input
voltages. The same feedback technique demonstrated in this work can be used to
minimize leakage for the transmission gate.

REFERENCES
[1] J. Lu, S. Young, I. Arel and J. Holleman, A 1 TOPS/W Analog Deep Machine-Learning Engine With FloatingGate Storage in 0.13 m CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 270-281, Jan. 2015.
[2] M. O'Halloran and R. Sarpeshkar, "A 10-nW 12-bit accurate analog storage cell with 10-aA leakage," in IEEE
Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1985-1996, Nov. 2004.
[3] C. Sawigun and W. A. Serdijn, "Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB
Current-Mode Subthreshold CMOS Sample and Hold Circuit," in IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 58, no. 7, pp. 1615-1626, July 2011.