Scribd Logo
Încărcați

Bine ați venit la Scribd!

  • Microelectronics I Notes Supplement Latchup in Bulk CMOS

    Încărcat de

    hardeep
    30 vizualizări2 pagini
    Latchup can occur in bulk CMOS circuits when both parasitic bipolar transistors conduct, creating a low resistance path between the power supply and ground. This happens when the product of the gains of the two transistors is greater than one. Latchup results in circuit malfunction and possible device destruction. It can be triggered by noise spikes or improper connections that cause one transistor to turn on, which then draws current to turn on the other in a self-sustaining feedback loop. Preventing latchup involves reducing the transistor gains, lowering parasitic resistances, and protecting against voltage transients and electrostatic discharge.

    Descriere originală:

    Latch-Up in CMOS Designs

    Titlu original

    Latch-Up in CMOS Designs

    Drepturi de autor

    © © All Rights Reserved

    Formate disponibile

    PDF, TXT sau citiți online pe Scribd

    Vi se pare util acest document?

    Este necorespunzător acest conținut?

    Raportați acest document
    Latchup can occur in bulk CMOS circuits when both parasitic bipolar transistors conduct, creating a low resistance path between the power supply and ground. This happens when the product of the gains of the two transistors is greater than one. Latchup results in circuit malfunction and possible device destruction. It can be triggered by noise spikes or improper connections that cause one transistor to turn on, which then draws current to turn on the other in a self-sustaining feedback loop. Preventing latchup involves reducing the transistor gains, lowering parasitic resistances, and protecting against voltage transients and electrostatic discharge.

    Drepturi de autor:

    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    30 vizualizări2 pagini

    Microelectronics I Notes Supplement Latchup in Bulk CMOS

    Încărcat de

    hardeep
    Latchup can occur in bulk CMOS circuits when both parasitic bipolar transistors conduct, creating a low resistance path between the power supply and ground. This happens when the product of the gains of the two transistors is greater than one. Latchup results in circuit malfunction and possible device destruction. It can be triggered by noise spikes or improper connections that cause one transistor to turn on, which then draws current to turn on the other in a self-sustaining feedback loop. Preventing latchup involves reducing the transistor gains, lowering parasitic resistances, and protecting against voltage transients and electrostatic discharge.

    Drepturi de autor:

    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 2

    MicroelectronicsINotesSupplement

    LatchupinBulkCMOS
    AbyproductoftheBulkCMOSstructureisapairofparasiticbipolartransistors.Thecollectorofeach
    BJTisconnectedtothebaseoftheothertransistorinapositivefeedbackstructure.Aphenomenoncalled
    latchupcanoccurwhen(1)bothBJT'sconduct,creatingalowresistancepathbetweenVddandGND
    and(2)theproductofthegainsofthetwotransistorsinthefeedbackloop,b1xb2,isgreaterthanone.
    Theresultoflatchupisattheminimumacircuitmalfunction,andintheworstcase,thedestructionofthe
    device.

    CrosssectionofparasitictransistorsinBulkCMOS

    EquivalentCircuit
    LatchupmaybeginwhenVoutdropsbelowGNDduetoanoisespikeoranimpropercircuithookup
    (VoutisthebaseofthelateralNPNQ2).IfsufficientcurrentflowsthroughRsubtoturnonQ2(IRsub>
    0.7V),thiswilldrawcurrentthroughRwell.IfthevoltagedropacrossRwellishighenough,Q1will
    alsoturnon,andaselfsustaininglowresistancepathbetweenthepowerrailsisformed.Ifthegainsare
    suchthatb1xb2>1,latchupmayoccur.Oncelatchuphasbegun,theonlywaytostopitistoreducethe
    currentbelowacriticallevel,usuallybyremovingpowerfromthecircuit.

    Themostlikelyplaceforlatchuptooccurisinpaddrivers,wherelargevoltagetransientsandlarge
    currentsarepresent.

    Preventinglatchup
    Fab/DesignApproaches
    1.Reducethegainproductb1xb1
    movenwellandn+source/drainfartherapartincreaseswidthofthebaseofQ2andreduces
    gainbeta2
    >alsoreducescircuitdensity
    buriedn+layerinwellreducesgainofQ1
    2.Reducethewellandsubstrateresistances,producinglowervoltagedrops
    highersubstratedopinglevelreducesRsub
    reduceRwellbymakinglowresistancecontacttoGND
    guardringsaroundpand/ornwell,withfrequentcontactstotherings,reducestheparasitic
    resistances.

    CMOStransistorswithguardrings

    SystemsApproaches
    1.Makesurepowersuppliesareoffbeforepluggingaboard.A"hotplugin"ofanunpoweredcircuit
    boardormodulemaycausesignalpinstoseesurgevoltagesgreaterthan0.7VhigherthanVdd,
    whichrisesmoreslowlytoispeakvalue.Whenthechipcomesuptofullpower,sectionsofit
    couldbelatched.
    2.CarefullyprotectelectrostaticprotectiondevicesassociatedwithI/Opadswithguardrings.
    Electrostaticdischargecantriggerlatchup.ESDentersthecircuitthroughanI/Opad,whereitis
    clampedtooneoftherailsbytheESDprotectioncircuit.Devicesintheprotectioncircuitcan
    injectminoritycarriersinthesubstrateorwell,potentiallytriggeringlatchup.
    3.Radiation,includingxrays,cosmic,oralpharays,cangenerateelectronholepairsasthey
    penetratethechip.Thesecarrierscancontributetowellorsubstratecurrents.
    4.Suddentransientsonthepowerorgroundbus,whichmayoccuriflargenumbersoftransistors
    switchsimultaneously,candrivethecircuitintolatchup.Whetherthisispossibleshouldbe
    checkedthroughsimulation.

    S-ar putea să vă placă și