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  • Exercise of FPGA-Based Digital System Design: DAC and ADC Verification

    Încărcat de

    Đặng Hoài Sơn
    8 vizualizări2 pagini
    This document describes an exercise to design and test a driver for an ADC and DAC on FPGA hardware. It involves: 1) Realizing a circuit that takes the ADC as input and outputs to the DAC using all 8 bits. 2) Connecting the ADC and DAC pins to the FPGA as specified in a table. 3) Verifying the circuit by sending a signal to the ADC input from a signal generator and checking the DAC output on an oscilloscope.

    Descriere originală:

    FPGA

    Titlu original

    5-ADC-DAC_15-16_2016

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    This document describes an exercise to design and test a driver for an ADC and DAC on FPGA hardware. It involves: 1) Realizing a circuit that takes the ADC as input and outputs to the DAC using all 8 bits. 2) Connecting the ADC and DAC pins to the FPGA as specified in a table. 3) Verifying the circuit by sending a signal to the ADC input from a signal generator and checking the DAC output on an oscilloscope.

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    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
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    8 vizualizări2 pagini

    Exercise of FPGA-Based Digital System Design: DAC and ADC Verification

    Încărcat de

    Đặng Hoài Sơn
    This document describes an exercise to design and test a driver for an ADC and DAC on FPGA hardware. It involves: 1) Realizing a circuit that takes the ADC as input and outputs to the DAC using all 8 bits. 2) Connecting the ADC and DAC pins to the FPGA as specified in a table. 3) Verifying the circuit by sending a signal to the ADC input from a signal generator and checking the DAC output on an oscilloscope.

    Drepturi de autor:

    © All Rights Reserved
    Descărcați ca PDF, TXT sau citiți online pe Scribd
    Indicator pentru conținut neadecvat
    din 2

    Exercise of

    FPGA-Based Digital System Design


    Prof. C. Abbate - A.A. 2015/2016

    DAC and ADC verification


    Introduction.
    In this exercise a driver for ADC and DAC will be realized and tested on FPGA hardware.

    ADC converter (ADC0820).


    In the next picture is reported the typical time diagram for the ADC operation. Download the ADC
    datasheet form the network. As we can see, the data out of the ADC is available after the second
    low value of WRneg (see the third signal on the graph). In order to synthetize the ADC signals,
    please realize the network on the figure. Moreover, analyze the circuit operation.

    Circuit for ADC time operation

    Please, realize a circuit that has as input the ADC and as output the DAC using all the 8 bits. Write
    a test beng in order to simulate the circuit.
    Assign the ADC and DAC pins as in the next table.
    1

    ADC and DAC connected as cascaded circuit

    ADC
    Connector

    DAC

    FPGA location

    Connector

    FPGA location

    CSneg Pin 10(P2) -> Pin 92 _CPLD(J11)

    CSneg1 Pin 5(P2) -> Pin 99_CPLD(J11) [set to 0]

    RDneg Pin 12(P2) -> Pin 89_CPLD (J11)

    CEneg1 Pin 7(P2) -> Pin 97_CPLD (J11) [set to 0]

    WRneg- Pin 6(P3) -> Pin 83_CPLD (J12)

    DI0 Pin 21(P3) -> Pin 68_CPLD (J11)

    IntNeg Pin 14(P2) -> Pin 1_CPLD (J11) [set to Vcc]

    DI1 Pin 23(P3) -> Pin 67_CPLD (J11)

    DB0 Pin 3(P3) -> Pin 86_CPLD (J12)

    DI2 Pin 25(P3) -> Pin 66_CPLD (J11)

    DB1 Pin 5(P3) -> Pin 84_CPLD (J12)

    DI3 Pin 27(P3) -> Pin 62_CPLD (J11)

    DB2 Pin 7(P3) -> Pin 82_CPLD (J12)

    DI4 Pin 29(P3) -> Pin 58_CPLD (J11)

    DB3 Pin 9(P3) -> Pin 78_CPLD (J12)

    DI5 Pin 31(P3) -> Pin 57_CPLD (J11)

    DB4 Pin 17(P3) -> Pin 70_CPLD (J12)

    DI6 Pin 33(P3) -> Pin 55_CPLD (J11)

    DB5 Pin 15(P3) -> Pin 72_CPLD (J12)

    DI7 Pin 35(P3) -> Pin 54_CPLD (J11)

    DB6 Pin 13(P3) -> Pin 74_CPLD (J12)


    DB7 Pin 11(P3) -> Pin 76_CPLD (J12)

    Experimental verification of the circuit


    In order to verify the circuit operation, send to the ADC input a signal generated by a signal
    generator an verify the DAC output by using the oscilloscope.

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