1) TP is used for all active CMOS related process options with optimal usability, accuracy & quality. 2) TP device library enables development teams to design analogue circuits and layouts with high efficiency. 3) Provides relevant setup and techfiles for the design entry tools. 4) The electrical and physical verification rule decks ensure that the designs are conform with the technology design rules to guarantee manufacturability with adequate yield. 5) High accurate parasitic extraction runsets ensure a proper timing