09 Memories

Digital IC-konstruktion
Cell-phone ASIC complexity and cost
Memories
Viktor wall
p of Electrical and Information Technology
gy
Dept.
Lund University
Parts of this material was adapted from the instructor material to

Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective
Viktor wall, ASIC/DSP, CCCD, Dept. of Applied Electronics, Lund University, Sweden-www.tde.lth.se/home/vikt-vikt@tde.lth.se
C t
Courtesy:
Sven
S
Mattisson,
M tti
EMP
Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden. www.eit.lth.se/
Market for Memories
E h Canceller
Echo
C
ll Chip
Chi
According to a new technical market research report, semiconductor

Memory: Technologies and Global Markets, the value of the global
semiconductor memory industry was nearly $46.2 billion in 2009, but is
expected to increase to nearly $79 billion in 2014, for a 5-year compound
annual growth rate (CAGR) of 11.3%.
The largest segment of the market, DRAM, or dynamic random access
memory, is projected to increase at a CAGR of 10.4% to $41.5 billion in 2014,
after
ft b
being
i
valued
l d att nearly
l $25.2
$25 2 billi
billion in
i 2009.
2009
NAND, or nonvolatile/NANO RAM, which is the second-largest segment of
th market,
the
k t iis estimated
ti t d att $12.8
$12 8 billi
billion in
i 2009,
2009 and
d is
i expected
t d to
t increase
i
at a 5-year CAGR of 15% to reach more than $25.7 billion in 2014.
RAMs
Size
ca. 5 x 6 mm2
10 RAMs
250kbits
ROMs
2 ROMs
30kbits
Source:
So
rce Semiconductor
Semicond ctor Memor
Memory: Technologies and Global Markets
Markets, April 2010
From http://www.electronics.ca/presscenter/articles/1272/1/Global-Market-ForSemiconductor-Memory-To-Be-Worth-79-Billion-In-2014/Page1.html
Report Price: Price:USD $4,850.00!!!

$4 850 00!!!
Motivation behind the quest for new memory technologies!

0.35m, 5 Metal Layer CMOS, >2 million transistors. Anders Berkeman 2002
Semiconductor Memory Classification
Random
Access
Nonvolatile Read-Only
y
RWM
Memories
(Nonvolatile)
Non-Random (NVRWM)
XXPROM & Flash
Read-Write Memories
(RWM)
Access
SRAM
FIFO
PROM
ROM
DRAM
LIFO(Stack)
EPROM
PLA
Shiftregister
g
Registerg
Bank CAM
Nonvolatile = data kept when supply voltage turned of

PROM =
Fuse based One time programmable
EPROM =
Usually erasable by UV-light

UV light
Usually high voltage for programming
removed from circuit when programmed
E2PROM
FLASH
CAM = contents addressable memory

Nonvolatile = data kept when supply voltage turned off
PROM = Programmable rom
EPROM = erasable programmable ROM
E2PROM & Flash= electrically erasable programmable ROM
EEPROM or
E2PROM =
Flash=
Individual bytes can be erased slow but versatile

g than EPROM
Larger
Larger sections are erased faster than EEPROM
E
Emerging
i Technologies
T h l i
MRAM = Magnetoresistive RAM
Electric current switches the magnetic polarity and
Change in magnetic polarity sensed as resistance change
We have registers, why memories?

D Flip-flop : 252m2
Memory element : 30m2
FeRAM or FRAM = Ferroelectric RAM

Crystal polarize when electric field applied
Polarization will lead to different charge when read
Polymer memories
Change
g in resistance due to ionic transport
p
with
applied electric field
AND MORE...
Memory Classification by ports
Flip-flops vs. SRAM

Alcatel Microelectronics 0
0.35m
35m CMOS technology process
Process and library dependent.
Single port: Read & Write
1.8
Flip-flops
Flip
flops
Dual port memory
Single port memory
Double width memory
1.6
1.4
Dual Port: Read and Write separate

Multiple ports
1.2
squa
are mm
Dual address port
1
0.8
More ports makes more efficient

addressing
add
ess g sc
schemes
e es poss
possible
b e but
increase the cost of the memory,
i.e. cost, complexity, ...
0.6
0.4
0.2
0
500
1000
1500 2000 2500 3000

memory elements
3500
4000
4500
Memory Addressing
D al Port F
Dual
Functionality
nctionalit by
b using
sing
Single Port Memories
M bits
S ingle port R A M
32 16
32x16
S ingle port R A M
32x16
A ddress counter
0
1
31:16
31:16
S ingle port R A M
32x32
15:0
15:0
ADDR
nW E
Word 1
S2
SN-3
SN-2
SN-1
Word N-3
Word N-2
Word N-1
Storage
Cell
Addres
ss Decod
der
S0
Word 0
N Words
W
=
Address b
bits
b)
NW
Words =
N Ad
ddress bits
a)
S0
S1
log2 N
a) 2 single port memories

b) 1 single port memory with double word length
M bits
Word 0
Word 1
Storage
Cell
Word N-3
Word N-2
Word N-1
A ddress counter
IInput-Output
tO t t
(M bits)
IInput-Output
tO t t
(M bits)
Decoder reduce number of address bits

from N to log2 N
Column Decoding
Large Memories
2K Columns
Addrress bits
Address
s Decode
er
S0
Word 0
Word 1
Word N-3
Word N-2
Word N-1
Sense Amplifiers/
Drivers
Large memories
Disproportional
height and width
bizarre
bi
shape
h
long delays
AK
AK+1
AL-1
Bit Line (BL)
Reduced
R
d
d Height
H i ht by
b
Column Decoding
Addrress Deco
oder
M bits
bit
Reduced
to 2L-K
One complete
O
l t word
d
line is accessed
Word Line (WL)
Long Wordline
Wasted power
Sense Amplifiers/
Drivers
A0
Column Decoder
AK-1
Input-Output
(M bits)
bit )
(unless all words are

used through memory
management)
Input-Output
(M bits)
Hierarchical Memory
Hierarchical Memory, contd.
Enable single memory

Row
Addr
Row
Addr
Col
Addr
Bl k
Block
Addr
Col
Addr
Block
Addr
Memory Bus
Mux/Drivers
Global Data Bus
A smaller memory is accessed

Length of WL and BL are reduced
Large Buffers
L
B ff
to drive bus
Global Data Bus
Variations of hierarchical memory structure

reduced size of buffers
Example of Splitting Memories

Lookup table of ca.
3000 words
d split
lit
into 3 memory
blocks (PLAs)
Signal Properties within Memory

M bits
Lookup table of ca.

3000 words split
into 6 memory
blocks (PLAs)
A
Address
s Decode
er
Addrress bits
S0
Memory Core Dominant
Word 0
W d1
Word
Storage
Cell
Register cells
>10tran/bit
Simpler storage cells

g
of signal
g
properties
p p
but
degradation
within confined environment
Word N-3
Reduced voltage swing

reduced delay & power consumption
Word N-2
Word N-1
Sense amplifiers to convert to full

swing
Sense Amplifiers/
Di
Drivers
Input-Output
(M bits)
Difference in size due to PLA minimization!

ROM array
Memory Generators
Silicon Vendors and/or cell library usually offers
a memory generators to handle internal
memory issues.
VDD
Pull Up
Word
GND
Addr
Row
Addr
Word
Col
Addr
Block
Addr
Word
GND
Memory Bus
Mux/Drivers
Word
bit
Global Data Bus
bit
bit
bit
The placements of transistors decide memory content.

Pseudo NMOS NOR ROM
MOS ROM Cells
VDD
Initially BL pulled up
Pull Up
BL
BL
WL
BL pulled
ll d
down when
WL=1
WL
1out
0out
No transitors
= always
pulled up
WL[0]
GND
A
0
0
1
1
B
0
1
0
1
Q
1
0
0
0
WL[1]
One transistor ON
pulls down Bit Line
WL[2]
NMOS NOR ROM

GND
WL[3]
GND lines
overhead
Area Reduced by Mirroring
BL[0]
BL[1] BL[2] BL[3]
MOS NOR ROM Layout
Pseudo NMOS NOR ROM

VDD
Pull Up
WL[0]=0
GND
A
0
0
1
1
B
0
1
0
1
Q
1
0
0
0
WL[1]=0
One transistor ON
pulls down Bit Line
WL[2]=1
NMOS NOR ROM

GND
WL[3]=0
GND lines
overhead
Area Reduced by Mirroring
1
0
1
0
Select WL[2] WL[0,1,3]=0 and WL[2] = 1
Cell (11 x 7)
One layer to program

memory
ROM programming can

be delayed until last
programming steps
((Reprogramming
p g
g with
same layout)
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Pseudo NMOS NAND ROM

VDD
Pull Up
BL[0]
[ ]
WL[0]
WL[1]
BL[1]
WL[3]
BL[3]
[ ]
on
on
WL[2]
BL[2]
on
A
0
0
1
1
B
0
1
0
1
Q
1
1
1
0
All transistors ON
pulls down Bit Line
Non-selected WL =1
Pseudo NMOS NAND ROM

A
0
0
1
1
VDD
Pull Up
BL[0]
BL[1]
BL[2]
BL[3]
WL[0]
B
0
1
0
1
Q
1
1
1
0
All transistors ON
pulls down Bit Line
Non-selected WL =1
WL[1]
WL[3]
off
off
WL lines reversed
Address lines reversed
WL[2]
NMOS NAND ROM

No Supply lines by series transistors
Select WL[2] WL[0,1,3]

WL[0,1,3]=1
1 and WL[2] = 0
Transistor on selected line shuts off path to GND
Large Pull-Up device
Long delay
MOS NAND ROM Layout
Equivalent Transient Model for MOS NOR ROM

VDD
Cell (8 x 7)
Model for NOR ROM
Pull Up
Programmming using
the Metal-1 Layer
y Onlyy
V DD
WL[0]
GND
BL
WL[1]
No contact to VDD or GND necessary;
d ti ll reduced
drastically
d
d cell
ll size
i
Loss in performance compared to NOR ROM
rword
WL
WL[2]
C bit
cword
GND
WL[3]
BL[0] BL[1] BL[2] BL[3]
Polysilicon
Wire capacitance and gate capacitance

Wire resistance (polysilicon)
Diffusion
Metal1 on Diffusion
Word line parasitics
Bit line parasitics

Resistance not dominant (metal)
Drain and Gate-Drain capacitance
E i l t Transient
Equivalent
T
i V t Model
M d l for
f MOS NAND ROM
Decreasing Word Line Delay
DD
Pull Up
BL[0]
BL[1]
BL[2]
Model for NAND ROM

V DD
BL[3]
Driving the word line from both ends
WL[0]
Driver
BL
WL[1]
CL
r bit
WL[3]
r word
WL
Polysilicon Word Line
WL
cbit
Metal Word Line
cword
WL[2]
Using Metal Bypass
Word line parasitics
Metal Word Line
Similar to NOR ROM
Bit line parasitics
WL
Resistance of cascaded transistors dominates

Drain/Source
/S
and complete gate capacitance
P l ili
Polysilicon
Word
W d Line
Li
Contact
Pseudo NMOS
Problems
VOL depends on transistor ratios
Static power consumption
Pre-charged NOR ROM

VDD
prech
Pre-charge
devices
NOR field
One transistor ON
pulls
ll down
d
Bit Line
Li
WL[0]
GND
Alternative
Fully complimentary
Large area
Pre-charged memories
4 x 4 NMOS NOR
Precharged
g ROM
WL[1]
WL[2]
GND
WL[3]
BL[0]
BL[1]
BL[2]
BL[3]
Clocked
R d
Reduced
d static
t ti
power consumption
Wh t iis a Fl
What
Flash
h memory?
?
Wh t iis a Fl
What
Flash
h memory?
?
ROM Read Only Memory
ROM Read Only Memory

data doesnt
doesn t change
data remain when powered down
RAM Random Access Memory
RAM Random Access Memory

data can be both read and stored
data disappears when powered down
FLASH
FLASH
data can be both read and stored

data remain when powered down
Fl ti Gate
Floating
G t Transistor
T
i t (FAMOS)
Flash EEPROM
electrically programmable VTH

Floating gate
BL
Control gate
Control gate
WL
n+
Floating gate
n+
Control gate is connected to wordline

Floating gate is left unconnected
If charged heavily negative High VTH No channel
If charged removed Low VTH Channel
erasure
n1 source
Thin tunneling oxide
programming
i
n1 drain
p-substrate
EPROM, EEPROM and Flash has different ways of

controlling
t lli the
th charge
h
off the
th floating
fl ti gate
t
FLASH stucture
FLASH write,
write e.g.
e g trap charge
VDD
VDD
Pull Up
Pull Up
word0
word0
GND
GND
word1
word1
word2
word2
GND
GND
word3
d3
word3
d3
= trapped charge. Transitor is always off Same content as ROM.
Floating gate transistors everywhere!

Basic Operations in a NOR Flash Memory

Memory
Write

Memory
Read
12 V
G
BL 0
BL 1
6V
D
BL 1
1V
WL 0
12 V
S
BL 0
5V
G
0V
WL 1
0V
6V
0V
WL 0
5V
D
0V
WL 1
0V
1V
0V

Memory
Erase
cell
BL 0
array
NOR
BL 1
G
12 V
WL 0
0V
S
NOR and NAND Flash

fast read access
slow erasure and programming are slow
Samsung:
g 512Mbit/133MHz
NAND
12 V
WL 1
0V
open
open
slower read access

larger storage density
fast erasure and programming
2008 Samsung: 32 Gbit/20MHz
2009 Samsung: 64 Gbit/20MHz - 32 Gbit/40MHz
(from www.samsung.com)
Living in the stage of 20GB memory after passing through the dark
dark-age
age of 1GB in 2002...
from www.samsung.com
Cross-sections of Floating Gates
Flash
l h
Courtesy Intel
EPROM
O
R d W it Memories
Read-Write
M
i (RAM)
6-transistor SRAM Cell

WL
Static (SRAM)
Data stored as long as supply is applied

Large cells (6 transistors/cell)
Fast
Differential
M2
M5
Vdd
M4
Q
Q
M1
M6
M3
Dynamic (DRAM)
Periodic refresh required

Small cells (1-3 transistors/bit)
Slower
Single Ended
BL
BL
Transistor sizing important

t ensure ffunctionality
to
ti
lit
Write: 6-transistor SRAM Cell
Read: 6-transistor SRAM Cell
WL
Vdd
Q
M5
WL
M4
Q=0
Q=1
M1
M6
Q=Vdd
Write 0 when Q=1:

Pull Q below switching
threshold, Vdd/2, for
toggle
toggle.
Vdd
Q
Vdd
M5
M4
Q=0
Q=1
M1
M6
Vdd
Q=Vdd
For writing 1 use BL

BL=1
BL=0

to
ti
lit
BL
Read 1:
BL and BL
precharged to 1
BL
BL dicharged
through M1-M5
Important not to
change
c
a ge Q
Q!

to
ti
lit
6-transistor SRAM Cell, layout
Content addressable memory (CAM)

Content-addressable
The time required to find an item stored in memory can be reduced considerably if
the item can be identified for access by its content rather than by its address
address. A
memory that is accessed in this way is called content-addressable memory or CAM.
CAM provides a performance advantage over other memory search algorithms, such
as binary or tree-based searches or look-aside tag buffers, by comparing the desired
information against the entire list of pre-stored entries simultaneously, often
resulting in an order-of-magnitude reduction in the search time.
CAM iis id
ideally
ll suited
it d for
f severall functions,
f
ti
including
i l di Ethernet
Eth
t address
dd
lookup,
l k
data
d t
compression, pattern-recognition, cache tags, high-bandwidth address filtering, and
fast lookup of routing, user privilege, security or encryption information on a packetby-packet
by
packet basis for high
high-performance
performance data switches, firewalls, bridges and routers.
For example, the search key could be the IP address of a network user, and the
privileges
g and his location on the
associated information could be users access p
network.
Source: Content-Addressable memory (CAM) and its network applications
Midas Peng and Sherri Azgomi, Altera International Ltd.
EE Times Asia
10 transistor CAM Cell

10-transistor
WL
M2
M5
3 transistor DRAM Cell
match precharged
Vdd
M4
Q
Q
M1
If Q = BL
e g BL=1 & Q=1
e.g.
M6
Write cycle
WWL
match remains high

match
1
BL
BL
if Q = BL for all bits

Priority if several
lines are valid?
For instance in
switches and routers
X
M1
M3
M2
VDD-VT
Read cycle
CS
BL1
Write
VDD
WWL
RWL
match is pulled down
M3
BL1
RWL
BL2
Read
BL2
VDD-V
VT
Inversed Value is Read
1 ttransistor
i t DRAM C
Cell
ll
3 transistor DRAM Cell, layout
BL
WWL
WL
RWL
M3
M1
M2
M1
CS
BL1
Write
BL2
Read
CBL
CS
Write:
Data placed on BL
WL raised and CS charged
g
or discharged
Read:
BL precharged
Charge distribution gives
stored
t
d value
l
CS: Gate capacitance of M2

Nondestructive read
Charge loss due to Leakage
Destructive Read, needs

restore!
R t
Restore
off 1 ttransistor
i t DRAM C
Cell
ll
BL
VBL
V(1)
VPre
V(1) = small change
WL
M1
CBL
1 transistor DRAM Cells
CS
V(0)
Sense amp. activated
Word line activated
Destructive Read, needs restore!

Feedback of sense amplifier output to BL
Sense Amplifier
Differential Sensing
PC
VDD
S.A.
VDD
Operation
EQ
Pre-charge (PC) bitlines and

E
Equalize
li (EQ)
WL
Signal Restoration
Low swing in core
Reduced power consumption
Requires signal restoration
Disable PC and EQ
E bl WL
Enable
Memory cell
x
Sense
Differential input
Common Mode rejection
((Only
y in 6-transistor cell))
BL
Differential
Sense
Amplifier
Turn on Sense
BL
Sense Amplifiers
Sense Amplifiers
VDD
EQ
BL
VDD
Analog Amplifiers.
y
x
SE
BL
SE
VDD
Cross C
C
Coupled Inverters
Initialized to metastable point by
equalization (EQ)
Very fast
Rail-to-rail swing on Bit Lines (BL)

increased power consumption
Good
G d for
f 1T-cell
1T ll restore
t
SE
VBL
SE
VPre
V(1)
V(1)
V(0)
Sense amp. activated
Word line activated
2 to 4 D
2-to-4
Dynamic
namic NOR Decoder
GND
GND
OFF
WL3=11
WL2=10
ON
Add
Address
Decoders
D
d
WL1=01
WL0=00
VDD
A0
1
WLs are precharged
A0
A1
All but one WL is pulled down
A1
A0A1=11
Consumes power
2-to-4 Dynamic NAND Decoder
2-to-4 Dynamic NAND Decoder
VDD
VDD
WL3=11
OFF
WL3=11
VDD
VDD
WL2=10
VDD
S i Transistors
Series
T
i t
WL2=10
ON
VDD
WL1=01
WL1=01
VDD
Slow
VDD
WL0=00
A0
A0
A1
A1
WL0=00
A0A1=11
A0
A0
All but one WL stays high

A1
A1
Less Consumed power
PLA versus
ers s ROM
PLA = Programmable
P
bl Logic
L i Array
A
PLA- Programmable
g
Logic
g Array
y
Structured approach to random logic, i.e.
implementing Boolean function
Two level logic, NOR-NOR or NAND-NAND
X0X1
AND
plane
l
Product terms
OR
plane
l
X2
F
Functionality
ti
lit Identical
Id ti l to
t ROM
Main difference:
ROM fully populated
PLA: One element per minterm, several WL valid
X0
X1
X2
f0
f1
f 0 x0 x 1 x 2
Importance reduced due to Multi-level-logic synthesis

(Synopsys)
f 1 x0 x 1 x 2 x 2 x0 x 1
Pre charged PLA

Pre-charged
PLA, NOR
NOR-NOR
NOR
PLA
Pull upp
GND
NAND - NAND
Pull upp
VDD
GND
GND
GND
GND
AND - OR
GND
GND
NOR - NOR
VDD
x0
x0
x1
x1
x2
x2
f 0 x0 x 1 x 2
f0
f1
f 1 x0 x 1 x 2 x 2 x0 x 1
P
Pre-charged
h
d PLA,
PLA NOR-NOR
NOR NOR
Pull upp
GND
Pull upp
VDD
GND
GND
GND
GND
GND
GND
VDD
x0
f 0 x0 x1 x2
x0
x1
x1
x2
x2
x0 x1 11 WL 1 f 0 0 f 0 1
f0
f1
x0 x1 0 WL 0 f 0 1 f 0 0
E
Espresso=
B
Boolean
l
Minimization
Mi i i ti
.i 7
.o 20
Input
.type f
.phase 11111111111111111111
0000010 00000100101010010000
0000011 00000100101010010000
0000100 -------------0110100
0010011 00001111101011000100
0011010 00100100001100010101
0101100 -------------1110000
1011010 0010010000110
0010010000110--10101
10101
1110110 10000101011111010000
1110111 10000101011111010000
1111100 10001010101111110000
1111101 10001010101111110000
1111110 10001--0101111110000
1111111 10001010101111110000
.e
.i 7
.o 20
#.phase
.p 9
0000100
11111-1
111110
1111100101100
0000010010011
-011010
11101111111-.e
Minimized
11111111111111111111
00000000000000110100
00000010000000000000
00000010000000000000
00000000000001110000
00000100101010010000
00001111101011000100
00100100001100010101
10000101011111010000
10001000101111110000
AND Plane OR Plane
Embedded RAM
I it a problem?
Is
bl ? Why
Wh is
i it a problem?
bl ?
FFT Design
D i
8k points FFT for DVB
(Digital Video Broadcasting)
Line memories for efficient dataflow

In
I total
t t l 75 distributed
di t ib t d memories,
i
(15/core
(15/
+ 15 line)
li )
Several embedded
memories whos
who s
properties and size
is crucial to the
implementation
OFDM Synchronization
Frame
Memories are a
dominant part of
the construction
Stefan Johansson
Funding: INTELECT

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Digital IC-konstruktion

Cell-phone ASIC complexity and cost

Parts of this material was adapted from the instructor material to

Market for Memories

According to a new technical market research report, semiconductor

Report Price: Price:USD $4,850.00!!!

Motivation behind the quest for new memory technologies!

Semiconductor Memory Classification

XXPROM & Flash

Nonvolatile = data kept when supply voltage turned of

Fuse based One time programmable

Usually erasable by UV-light

CAM = contents addressable memory

Individual bytes can be erased slow but versatile

We have registers, why memories?

Memory element : 30m2

FeRAM or FRAM = Ferroelectric RAM

Memory Classification by ports

Flip-flops vs. SRAM

Single port: Read & Write

Dual Port: Read and Write separate

Dual address port

More ports makes more efficient

1500 2000 2500 3000

a) 2 single port memories

Decoder reduce number of address bits

Bit Line (BL)

(unless all words are

Hierarchical Memory, contd.

Enable single memory

A smaller memory is accessed

Global Data Bus

Variations of hierarchical memory structure

Example of Splitting Memories

Signal Properties within Memory

Lookup table of ca.

Memory Core Dominant

Simpler storage cells

Reduced voltage swing

Sense amplifiers to convert to full

Difference in size due to PLA minimization!

Global Data Bus

The placements of transistors decide memory content.

Pseudo NMOS NOR ROM

MOS ROM Cells

NMOS NOR ROM

Area Reduced by Mirroring

BL[1] BL[2] BL[3]

MOS NOR ROM Layout

Pseudo NMOS NOR ROM

NMOS NOR ROM

Area Reduced by Mirroring

One layer to program

ROM programming can

Pseudo NMOS NAND ROM

Pseudo NMOS NAND ROM

Address lines reversed

NMOS NAND ROM

Select WL[2] WL[0,1,3]

Large Pull-Up device

MOS NAND ROM Layout

Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM

Wire capacitance and gate capacitance