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Overview
1.1
Features
Type
Package
TLE 5206-2
PG-TO220-7-11
TLE 5206-2GP
PG-DSO-20-37
TLE 5206-2G
PG-TO263-7-1
TLE 5206-2S
PG-TO220-7-12
TLE 5206-2
PG-TO220-7-11
PG-DSO-20-37
PG-TO263-7-1
PG-TO220-7-12
Description
The TLE 5206-2 is an integrated power H-bridge with DMOS output stages for driving
DC-Motors. The part is built using the Infineon multi-technology process SPT which
allows bipolar and CMOS control circuitry plus DMOS power devices to exist on the
same monolithic structure.
Operation modes forward (cw), reverse (ccw), brake high and brake low are invoked
from just two control pins with TTL/CMOS compatible levels. The combination of an
extremely low RDS ON and the use of a power IC package with low thermal resistance and
high thermal capacity helps to minimize system power dissipation. A blocking capacitor
at the supply voltage is the only external circuitry due to the integrated freewheeling
diodes.
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Overview
1.2
TLE 5206-2
TLE 5206-2GP
GND
N.C.
N.C.
N.C.
N.C.
VS
Q1
EF
IN1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
N.C.
N.C.
N.C.
N.C.
VS
Q2
N.C.
IN2
GND
AEP01680
TLE 5206-2S
EF
OUT1
GND
IN1
VS
IN2
OUT2
AEP01990
TLE 5206-2G
2 3
4 5 6
1 2
6 7
OUT1 IN1
IN2 OUT2
EF GND V S
AEP01991
OUT1
EF
IN1
OUT2
IN2
GND
VS
AEP02513
Figure 1
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Overview
1.3
Pin No.
P-TO220
Pin No.
P-DSO
Symbol
Function
OUT1
EF
IN1
Control Input 1;
TTL/CMOS compatible
1, 10,
11, 20
GND
Ground;
internally connected to tab
12
IN2
Control Input 2;
TTL/CMOS compatible
6, 15
VS
14
OUT2
2, 3, 4, 5, N.C.
16, 17, 18,
19
Data Sheet
Not Connected
Rev.1.1, 2007-07-31
TLE 5206-2
Overview
1.4
VS
EF
2
Error Flag
Diagnosis and Protection Circuit 1
IN1
IN2
IN
1
OUT
1 2
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
OUT1
OUT2
4
GND
Figure 2
Data Sheet
AEB02405
Block Diagram
Rev.1.1, 2007-07-31
TLE 5206-2
Overview
1.5
Circuit Description
Input Circuit
The control inputs consist of TTL/CMOS-compatible schmitt-triggers with hysteresis.
Buffer amplifiers are driven by this stages.
Output Stages
The output stages consist of a DMOS H-bridge. Integrated circuits protect the outputs
against short-circuit to ground and to the supply voltage. Positive and negative voltage
spikes, which occur when switching inductive loads, are limited by integrated
freewheeling diodes.
A monitoring circuit for each output transistor detects whether the particular transitor is
active and in this case prevents the corresponding source transistor (sink transistor) from
conducting in sink operation (source operation). Therefore no crossover currents can
occur.
1.6
IN2
OUT1
OUT2
Comments
Value
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Overview
1.7
Monitoring Functions
Protective Function
Various errors like short-circuit to + VS, ground or across the load are detected. All faults
result in turn-OFF of the output stages after a delay of 50 s and setting of the error flag
EF to ground. Changing the inputs resets the error flag.
a. Output Shorted to Ground Detection
If a high side transistor is switched on and its output is shorted to ground, the output
current is internally limited. After a delay of 50 s all outputs will be switched-OFF and
the error flag is set.
b. Output Shorted to + VS Detection
If a low side transistor is switched on and its output is shorted to the supply voltage,
the output current is internally limited. After a delay of 50 s all outputs will be
switched-OFF and the error flag is set.
c. Overload Detection
An internal circuit detects if the current through the low side transistor exceeds the
trippoint ISDL. In this case all outputs are turned off after 50 s and the error flag is set.
d. Overtemperature Protection
At a junction temperature higher than 150 C the thermal shutdown turns-OFF, all four
output stages commonly and the error flag is set with a delay.
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Diagnosis
2
Diagnosis
Various errors as listed in the table Diagnosis are detected. Short circuits and overload
result in turning off the output stages after a delay tdSD and setting the error flag
simultaneously [EF = L]. Changing the inputs to a state where the fault is not detectable
resets the error flag (input toggling) with the exception of short circuit from OUT1 to
OUT2 (load short circuit).
Flag
Overtemperature or undervoltage
IN:
0 = Logic LOW
1 = Logic HIGH
OUT:
0
0
1
1
0
1
0
1
L
X
X
H
L
X
X
H
1
0
0
1
Not detectable
0
0
1
1
0
1
0
1
GND
GND
GND
GND
L
X
L
X
1
1
0
0
Not detectable
Not detectable
0
0
1
1
0
1
0
1
L
L
X
X
GND
GND
GND
GND
1
0
1
0
Not detectable
0
0
1
1
0
1
0
1
VS
VS
VS
VS
X
H
X
H
0
0
1
1
0
0
1
1
0
1
0
1
X
X
H
H
VS
VS
VS
VS
0
1
0
1
0
0
1
1
0
1
0
1
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
EF:
Not detectable
Not detectable
Not detectable
Not detectable
Not detectable
Not detectable
1 = No error
0 = Error
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
3
Electrical Characteristics
3.1
Parameter
Symbol
Limit Values
Unit
Remarks
min.
max.
0.3
40
40
0.3
0.3
Voltages
Supply voltage
Logic input voltage
Diagnostics output voltage
VS
VIN1, 2
VEF
IOUT1, 2
IOUT1, 2
IOUT1, 2
Temperatures
Tj
Tstg
40
150
50
150
Junction case
RthjC
K/W
P-TO220-7-11/12,
P-TO263-7-1
Junction ambient
RthjA
65
K/W
P-TO220-7-11/12
75
K/W
P-TO263-7-1
K/W
PG-DSO-20-37
50
K/W
PG-DSO-20-37
Junction temperature
Storage temperature
Thermal Resistances
Junction case
Junction ambient
RthjC
RthjA
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Data Sheet
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
3.2
Operating Range
Parameter
Symbol
Supply voltage
VS
Remarks
max.
VUV ON 40
VUV ON
0.3
VUV ON V
VUV OFF V
Outputs in tristate
condition
0.3
40
150
0.3
3.3
VIN1, 2
Tj
Electrical Characteristics
Symbol
Limit Values
min.
typ.
max.
10
Current Consumption
Quiescent current
IS
mA
VS = 13.2 V
Under Voltage Lockout
UV-Switch-ON voltage
UV-Switch-OFF voltage
UV-ON/OFF-Hysteresis
Data Sheet
VUV ON
VUV OFF
VUV HY
5.3
3.5
4.7
5.6
0.2
0.6
VS increasing
VS decreasing
VUV ON VUV OFF
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
3.3
Symbol
Limit Values
min.
typ.
max.
220
350
6 V < VS < 18 V
Tj = 25 C
500
6 V < VS < 18 V
350
500
800
230
350
500
400
600
1000 m
VS ON < VS 6 V
Tj = 25 C
VS ON < VS 6 V
6 V < VS < 18 V
Tj = 25 C
6 V < VS < 18 V
VS ON < VS 6 V
Tj = 25 C
VS ON < VS 6 V
Outputs OUT1, 2
Static Drain-Source-On Resistance
Source
IOUT = 3 A
Sink
RDS ON H
RDS ON L
IOUT = 3 A
Data Sheet
ISDH
ISDL
tdSD
10
10
Tj = 40 C
Tj = 25 C
Tj = 150 C
Tj = 40 C
Tj = 25 C
Tj = 150 C
25
50
80
10
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
3.3
Symbol
Limit Values
min.
typ.
max.
ISCH
20
Sink current
ISCL
15
t < tdSD
t < tdSD
20
IOUT = 3 A
td ON H
10
resistive load
Sink ON
td ON L
10
20
IOUT = 3 A
resistive load
Source OFF
td OFF H
IOUT = 3 A
resistive load
Sink OFF
td OFF L
IOUT = 3 A
resistive load
tON H
15
30
IOUT = 3 A
resistive load
Sink ON
tON L
10
IOUT = 3 A
resistive load
Source OFF
tOFF H
IOUT = 3 A
resistive load
Sink OFF
tOFF L
IOUT = 3 A
resistive load
Clamp Diodes
Forward Voltage
High-side
Low-side
Data Sheet
VFH
VFL
1.5
1.1
1.5
11
IF = 3 A
IF = 3 A
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
3.3
Symbol
Limit Values
min.
typ.
max.
Leakage Current
ILKH
ILKL
100 35
OUT1 = VS
35
100
OUT2 = GND
VINH
VINL
VINHY
IINH
IINL
2.8
2.5
1.7
1.2
0.4
0.8
1.2
10
VIN = 5 V
VIN = 0 V
VEFL
IEFL
0.25
0.5
10
IEF = 3 mA
VEF = 7 V
TjSD
150
175
200
TjSO
120
170
Temperature hysteresis
30
Source
Sink
Logic
Control Inputs IN 1, 2
H-input voltage threshold
L-input voltage
Hysteresis of input voltage
H-input current
L-input current
Error Flag Output EF
Low output voltage
Leakage current
Thermal Shutdown
Data Sheet
12
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
FU ; S
EF
IN1
V EF
IN2
V IN1
2
3
5
EF
VS
IN1
TLE 5206-2
IN2
V IN2
4700 F
63 V
470 nF
OUT1
OUT2
OUT1
OUT2
R Load
VS
GND
V OUT1 V OUT2
FL
AES02406
Figure 3
IOUT
Data Sheet
Test Circuit
Overcurrent
Short Circuit
Open Circuit
ISD
ISC
IOC
13
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
VIN
V
5
t r = t f <_ 100 ns
50%
OUT
Source
t dONH
A
3
t dOFFH
80%
50%
20%
OUT
Sink
A
3
80%
50%
20%
t ONH
t OFFH
t OFFL
t ONL
80%
50%
20%
80%
50%
20%
t dOFFL
t dONL
AET01994
Figure 4
100 F
3
5
EF
VS
IN1
TLE 5206-2
IN2
OUT1
1
100 nF
OUT2
N =3A
BL = 6 A
GND
4
AES02407
Figure 5
Data Sheet
Application Circuit
14
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
Application Modes
1. Simple CW/CCW-Control
For low-cost application simple CW/CCW-Control without any speed regulation is
recommended. A low-speed two-line interface is sufficient for the brake low,
clockwise, counter clockwise and brake high command.
2. Sign/Magnitude Control
For this mode two ports with PWM capability are necessary. Motor turns clockwise
(current flows from OUT1 to OUT2; means: OUT1 is switched HIGH continuously and
OUT2 is PWM controlled.
To achieve motor counter clockwise turning change input signals to:
IN1 = PWM; IN2 = H.
IN2
PWM
Motor speed
=0
= 0.1
= 0.5
= 0.9
=1
Fastest
High
Medium
Low
t
Brake to Zero
V OUT1 - V OUT2
VS
Motor
Short
Circuit
t
AED02408
Figure 6
Data Sheet
15
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
IN1, 2
SCH
SDH
OUT1, 2
VOUT1, 2
R Short x SCH
t dSD
V FL
EF
AED01997
Figure 7
IN1, 2
SCL
SDL
OUT1, 2
VOUT1, 2
VS
R Short x SCL
V FU
t dSD
EF
AED01998
Figure 8
Data Sheet
16
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
Diagrams
Quiescent Current IS (active)
versus Junction Temperature Tj
AED02398
0.6
R ON
mA
6
0.5
0.4
0.3
V S = 18 V
0.2
3
VS =6V
1
-50
50
100
0.1
0
-50
C 150
50
100
Tj
Tj
AED02400
3.0
V INH, L
C 150
AED02401
1.3
VF
V INH
2.5
1.2
High Side Transistor
2.0
1.1
V INL
1.5
1.0
1.0
0.9
0.5
0.8
0
-50
50
100
0.7
-50
C 150
Tj
Data Sheet
50
100
C 150
Tj
17
Rev.1.1, 2007-07-31
TLE 5206-2
Electrical Characteristics
Overcurrent Shutdown Threshold ISD
versus Junction Temperature Tj
AED02402
12
AED02403
0.6
V EF
SD
10
0.5
Low Side Transistor
0.4
High Side Transistor
0.3
0.2
0.1
0
-50
50
100
0
-50
C 150
Tj
Data Sheet
18
50
100 C 150
Tj
Rev.1.1, 2007-07-31
TLE 5206-2
Package Outlines
4
Package Outlines
PG-TO220-7-11
(Plastic Transistor Single Outline Package)
10 0.2
9.9 0.2
1.27 0.1
3.7 0.3
10.2 0.3
8.6 0.3
1.6 0.3
0.05
7x 0.6 0.1
0.5 0.1
2.4
0...0.15
3.9 0.4
0.25
A C
8.4 0.4
Typical
Metal surface min. X=7.25, Y=12.3
All metal surfaces tin plated, except area of cut.
GPT09083
6x 1.27
1)
9.25 0.2
0...0.3
2.8 0.2
3.7 -0.15
1)
12.95
15.65 0.3
17 0.3
8.5
4.4
1)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page Products: http://www.infineon.com/products.
Dimensions in mm
19
Rev.1.1, 2007-07-31
TLE 5206-2
Package Outlines
5 3
-0.02
0.25 +0.0
7
1.3
1.2 -0.3
11 0.15 1)
2.8
3.5 max.
0 +0.15
3.25 0.1
PG-DSO-20-37
(Plastic Dual Small Outline Package)
15.74 0.1
1.27
0.4
Index Marking
0.1
6.3
+0.13
0.25
20
11
1
1 x 45
10
A 20x
14.2 0.3
Heatsink
0.95 0.15
0.25
15.9 0.15 1)
A
1) Does not include plastic or metal protrusion of 0.15 max. per side
GPS05791
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page Products: http://www.infineon.com/products.
Dimensions in mm
20
Rev.1.1, 2007-07-31
TLE 5206-2
Package Outlines
PG-TO263-7-1
(Plastic Transistor Single Outline Package)
4.4
10 0.2
1.27 0.1
0...0.3
B
0.05
2.4
0.1
4.7 0.5
2.7 0.3
7.551)
10.3
9.25 0.2
(15)
8.5 1)
0...0.15
7x0.6 0.1
6x 1.27
0.5 0.1
0.25
A B
8 max.
1)
Typical
Metal surface min. X=7.25, Y=6.9
All metal surfaces tin plated, except area of cut.
GPT09114
0.1 B
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page Products: http://www.infineon.com/products.
Dimensions in mm
21
Rev.1.1, 2007-07-31
TLE 5206-2
Package Outlines
PG-TO220-7-12
(Plastic Transistor Single Outline Package)
10 0.2
9.9 0.2
1.27 0.1
2.4
13 0.5
0.05
0.5 0.1
0...0.15
2.4
7x 0.6 0.1
6x 1.27
1)
9.25 0.2
2.8 0.2
3.7 -0.15
0...0.3
110.5
1)
12.95
17 0.3
15.65 0.3
8.5
4.4
1)
0.25
A B C
Typical
Metal surface min. X=7.25, Y=12.3
All metal surfaces tin plated, except area of cut.
Data Sheet
22
Rev.1.1, 2007-07-31
TLE 5206-2
Revision History
5
Revision History
Version
Date
Rev. 1.1
Data Sheet
Changes
23
Rev.1.1, 2007-07-31
Edition 2007-07-31
Published by
Infineon Technologies AG
81726 Munich, Germany