Documente Academic
Documente Profesional
Documente Cultură
Introduction
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: viren@ee.iitb.ac.in
EE-309: Microprocessors
Lecture
1
(21
July
2015)
CADSL
Course Outline
v ISA
&
8085
Architectures
[1
week]
v 8051
Architecture
&
Programming
[2
Weeks]
v Device
Interfacing
[2
weeks]
v ISA
and
CISC
Processor
Design
[3
Weeks]
v RISC
Processor
Design
[3
Weeks]
v Pipelined
Design
[2
Weeks]
v Memory
System
Design
[1
Week]
21 Jul 2015
EE-309@IITB
CADSL
Software
Hardware
EE-309
Instruction Set
Architecture
21 Jul 2015
EE-309@IITB
CADSL
Instructions
Program
(code size)
Cycles
Instruction
(CPI)
Time
Cycle
(cycle time)
EE-309@IITB
CADSL
INSTRUCTION SET
ARCHITECTURE
21 Jul 2015
EE-309@IITB
CADSL
EE-309@IITB
CADSL
hardware
21 Jul 2015
EE-309@IITB
CADSL
Interface Design
A
good
interface:
Lasts
through
many
implementaNons
(portability,
compaNbility)
Is
used
in
many
dierent
ways
(generality)
Provides
convenient
funcNonality
to
higher
levels
Permits
an
ecient
implementaNon
at
lower
levels
use
Interface
use
imp 2
use
21 Jul 2015
time
imp 1
imp 3
EE-309@IITB
CADSL
EE-309@IITB
CADSL
EE-309@IITB
10
CADSL
21 Jul 2015
EE-309@IITB
11
CADSL
Instruction
C
Statement
f
=
(g+h)
(i+j)
Assembly
instrucNons
add
t0,
g,
h
add
t1,
I,
j
sub
f,
t0,
t1
EE-309@IITB
12
CADSL
EE-309@IITB
13
CADSL
EE-309@IITB
14
CADSL
21 Jul 2015
EE-309@IITB
15
CADSL
EE-309@IITB
16
CADSL
ISA Classification
Type
of
internal
storage
in
a
processor
is
the
most
basic
dierenNator
Stack
Architecture
Accumulator
Architecture
General
Purpose
Register
Architecture
Memory-Memory
Architecture
21 Jul 2015
EE-309@IITB
17
CADSL
EE-309@IITB
18
CADSL
Stack Architectures
InstrucNon
set:
add,
sub,
mult,
div,
.
.
.
push
A,
pop
A
B
A
A*B
EE-309@IITB
A
A*B
C
A
A*B
B
C
A
A*B
B*C
A
A*B
19
A+B*C result
A*B
CADSL
21 Jul 2015
EE-309@IITB
20
CADSL
Thank You
21 Jul 2015
EE-309@IITB
21
CADSL