1

VLSI Data Conversion Circuits

Problem Set:3
Theertham RaviTeja(ee15s023)

I. P ROBLEM 1 4th ORDER MODULATOR ; NTF DESIGN ,I NVESTIGATING THE EFFECTS OF

QUANTIZER NONIDEALITIES FOR 2- LEVEL AND 4- LEVEL QUANTIZERS ,I MPROVING THE SQNR OF
2- LEVEL QUANTIZER
A. NTF(Z) and L(z)
A 4th order NTF with an OBG of 1.5 is synthesized using the following function of toolbox in
MATLAB.
NTF = synthesizeNTF(4,64,0,1.5,0);

The resultant NTF is

1 4z1 + 6z2 4z3 + z4
1 3.195z1 + 3.8928z2 2.1361z3 + 0.444z4
1
1 which yields
L(z) is found using the relation L(z) = NTF(z)
NTF(z) =

0.805z1 2.1072z2 + 1.8639z3 0.556z4

L(z) =
1 4z1 + 6z2 4z3 + z4

(1)

(2)

B. STF of the given architecture

U (z) V (z) L(z) + U (z) = V (z) E(z)




V (z) 1 + L(z) = U (z) 1 + L(z) + E(z)
E(Z)
V (z) = U (z) +
1 + L(z)
On comparing Eq(5) with V(z) = STF(z) U(z) + NTF(z) E(z) we get STF(z) = 1.
C. Analytically estimating in-band quantization noise for a 5-level quantizer with = 2 and OSR = 64


To calculate the In-band noise power,we can approximate the magnitude of In-band NTF asNTF(ej ) = 4
where 163.889


OSR
2 Z
9  OSR
2


IBN =
2 8 dw =
2 
12
12 9
9
0

h i9

2
=

= 5.239 1010
108
OSR

(3)

D. estimating MSA
To estimate MSA, we excite the modulator with slowly varying ramp from zero to Full-Scale(FS) and
monitor the output of loop filter (i.e.,input to the quantizer). Once the input exceeds MSA the input to the
quantizer blows up as the modulator becomes unstable.The same can be seen from Fig. 1. In this case,
for 5-level quantizer, MSA is found to be 3.661.

300
250
200

20 log |y|

150
100
50
0

X: 3.661
Y: 10.85

-50
-100
0

0.5

1.5

2.5

3.5

Fig. 1: estimating MSA

E. modulator simulation
The modulator is simulated using the following function of toolbox in MATLAB.
[v,xn,xmax,y] = simulateDSM(u,NTF,nlev,[]);

The simulated SQNR turned out to be 104.16 dB as shown in Fig.2. To calculate the SQNR analytically,
we compute signal power and noise power and express the ratio of the signal power to noise power in dB.
In order to give room for the shape quantization noise riding on input, we have chosen the input amplitude
of sinusoid as 3.2628, which is 1dB less than MSA that gives us signal power of 5.3229 units. We have
already computed the In-band noise power analytically in part C, which turned out to be 5.2391010 units.
!
P

5.3229
signal
SQNR = 10 log
= 10 log
= 100.07 dB
(4)
Pnoise
5.239 1010
F. Non-ideal quantizer with ADC levels displaced from ideal values
To invoke the ADC thresholds non-ideality, we can slightly change the simulateDSM such that it uses
the non-ideal quantizer which incorporates ADC threshold error rather than the ideal one. The quantizer
transfer characteristics of this non-ideal quantizer looks as shown in inset of Fig.3. To examine the effect
of ADC threshold error on SQNR, we can view this error as being injected at the same point where the
quantization error gets injected. Therefore we can expect it to be shaped away by the modulators NTF.
The simulation also confirms our reasoning as we can see the degradation in SQNR is 2 dB for 100
iterations as shown in Fig.3.

-20

dBFS/NBW

-40

-60

-80
SNR = 104.16dB
NBW=0.00018

-100

-120

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 2: PSD of the modulator output

dBFS/NBW

-20
-40
-60
-80

SNR = 103.48dB
2

NBW=0.00018
v

-100

Error in ADC thresholds

threshold error
ideal

0
-2

-120

-4
-4

-2

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f /fs

Fig. 3: PSD of the modulators output with error in thresholds of ADC

G. Non-ideal quantizer with DAC levels displaced from ideal values

The displacement of DAC levels from the ideal values can be easily incorporated in the simulation by
recognizing that any error in the DAC level is injected into the loop at the same point where input does.
The displacement of DAC level can be thought of as injecting the code dependent error at the input.
Since this error sees STF(=1) of the modulator, it (atleast in-band frequency components of error) affects

the SQNR drastically which is also evident from the simulation. We can also see that the noise-floor has
increased considerably along with harmonics as shown in the Fig.4. This makes sense because if we now
join the mid-point of each level of the DAC, we get a non-linear curve.

-20

dBFS/NBW

-40

-60
4
-80

Error in DAC levels

with DAC
level error
ideal

SNR = 34.33dB
2

NBW=0.00018

-100

-2
-120
-4
-5

0.05

0.1

0.15

0.2

0.25

0.3

-140
0.35

0.4

0.45

0.5

f/fs

Fig. 4: PSD of the modulators output with error in DAC levels

H. 1-bit quantizer in loopEffect of deviations in ADC thresholds and DAC levels for the same
Since the quantizer is now replaced by the 2-level version whose output levels can take either +4 or 4,
the wiggling of shaped quantization noise riding over input also increases which can affect the MSA of
the modulator.To estimate the MSA we proceed in the same way as done in part D. We should expect the
MSA to be less than the value we got when a 5-level quantizer was in the loop. It is indeed in agreement
with the simulation as shown in Fig.5, the MSA is now 2.631. To simulate the modulator, we proceeded
on the same lines as we did in part E but now since the MSA is less,the amplitude of sinusoid fed to the
modulator is changed accordingly (1 dB less than the MSA) to 2.3448. The simulated SQNR turned out
to be 92.64 dB as shown in Fig.6. To calculate the SQNR analytically we proceed as follows,
2.34482
= 2.749
2


OSR
2 Z
2
9  OSR


In band noise power =
2 8 dw =
2 
12
12 9
9
signal power =

h i9

=
2
= 8.3836 109
108
OSR
!
P

2.749
signal
SQNR = 10 log
= 10 log
= 85.121 dB
Pnoise
8.3836 109

(5)

To see the effect of ADC threshold deviation on SQNR, we proceed in the same lines as done in part
F. we find that change in ADC threshold hardly affects the SQNR as evident from Fig.7 which could be

300
250
200

20log|y|

150
100
50
0

X: 2.631
Y: -34.25

-50
-100
0

0.5

1.5

2.5

Fig. 5: PSD of the modulators output with error in DAC levels

-20

dBFS/NBW

-40

-60

-80
SNR = 92.64dB
NBW=0.00018

-100

-120

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 6: PSD of the modulators with 2-level quantizer in loop

explained by the same ideas as reasoned in part F. To see the effect of DAC level deviation on SQNR, we
proceed in the same lines as done in part G.The key idea here is that in the case of a 2-level quantizer,
even though there is an error in DAC levels, it can be modeled as gain error and offset which are benign.
The linearity of the DAC is retained even in case of non-idealities that creep in the DAC implementation.
This is the advantage that 2-level quantizer possesses over the multi level counterparts. One thing that

-20

-60

Error in ADC threshold

4
SNR = 91.39dB
NBW=0.00018

-80

with ADC
threshold error
Ideal

dBFS/NBW

-40

-100
-2
-120

-4
-2

-1

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0
0.4 u

1
0.45

2
0.5

f/fs

Fig. 7: PSD of the modulators output with 1-bit quantizer in the loop whose threshold is deviated from
ideal value
has to be observed in the output PSD shown in Fig.8 is that the 1st and 2nd bins in the FFT are now full
signifying that the way we modeled the DAC level error as offset and gain error is true.

-20

-60
0

-80

DAC levels
displaced

SNR = 92.03dB
NBW=0.00018

Ideal case

-50

-100

Error in DAC thresholds

DC bin

dBFS/NBW

dBFS/NBW

-40

-100

-120
0

f/fs

10

-5
-2

-3

-1

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 8: PSD of the modulators output with 1-bit quantizer in the loop whose output levels are deviated
from ideal value

I. Improvement to the single bit design by using a 5-level quantizer and a digital filter outside the
modulator

v1
u

L(Z)

N T F (Z)

v2

Fig. 9: Improvement to the single bit design

v and v1 are processed as shown in Fig.9. The idea behind proceeding this way is as follows. If we
model both the 2-level and 5-level quantizers as additive noise sources and denote the quantization error

added by them by e1 and e2 respectively and carry out the analysis in z-domain, we can write
V = U + NTF E1
V1 = U + (NTF 1) E1 + E2
V1 NTF + V = U(1 + NTF) + NTF2 E1 + NTF E2
!
* 1

2 + L(z)

+
NT F 2 E
V2 = U
| {z }1
1
+ L(z)


8th order shaped 2-level quantization error

N T F E2
| {z }

(6)

4th order shaped 5-level quantization error

If analog modulators NTF precisely matches with the digital implementation of NTF outside the modulator
to process v1 , then we can get 8th order noise shaping of E1 , which is 2-level quantization error. In addition
we also get 4th order shaped quantization error of 5-level quantizer which would be very less since its
step-size() is 2. Since the major chunk of error in the in-band E1 is now shaped by 8th order NTF
we can expect improvement in SQNR which is also confirmed by our simulation results which computes
SQNR to be 98.37 dB as shown in the Fig.10. To investigate the effect of non idealities in the quantizers

-20

dBFS/NBW

-40

-60

-80
SNR = 98.37dB
NBW=0.00018

-100

-120

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 10: PSD of the modulators output with 1-bit quantizer in the loop whose output levels are deviated
from ideal value
in the improved architecture, we re-simulate the modulator with ADC and DAC error introduced each at
a time. As evident from Fig.11 and Fig.12, we can see that SQNR has hardly changed. This makes sense,
as seen earlier in part H, it is the advantage that we get when there is a two level quantizer in the loop.

-20

dBFS/NBW

-40

-60

-80
SNR = 96.70dB
NBW=0.00018

-100

-120

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 11: output PSD of the improved single-bit modulator with ADC threshold error

-20

dBFS/NBW

-40

-60

-80
SNR = 96.38dB
NBW=0.00018

-100

-120

-140
0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f/fs

Fig. 12: output PSD of the improved single-bit modulator with DAC level deviated from ideal value

II. D ETERMINING THE LOOP FILTER COEFFICIENTS OF CTDSM FOR A GIVEN NTF AND DAC PULSE
SHAPE

The desired NTF for the loop filter architecture in Fig.13 is NTF(z) = (1 z1 )2 . The loop filter

10

k1
1
s

p(t)

k2

1
s

l(t)

Fig. 13: loop filter architecture given

transfer function corresponding to given NTF(z) is given by
1
1
NTF(z)
z 2
2 z 1
=
+
(1 z 1 )2 (1 z 1 )2

L(z) =

(7)

Taking inverse Z-transform we get

l(n) = [ 0 2 4 6 8 10 . . . .] [ 0 0 1 2 3 4 . . . .]
= [ 0 2 3 4 5 6 . . . .]

(8)

A. Impulsive DAC

1
s

3 4

3 4

2
1

1
s2

0
0

Fig. 14: pulse responses at the output of integrators

From Fig.14 we can write as follows
k1 [ 0 1 1 1 1 1 . . . .] k2 [ 0 1 1 2 3 4 . . . .] = [ 0 2 3 4 5 6 . . . .]

(9)

and solve for k1 and k2 by taking any pair of equations, we get k1 = 1 and k2 = 1.
B. RZ DAC
From Fig.15, pulse response of single integrator path is denoted as l1 (t) and is given by
(
2t 0 < t < 1/2
l1 (t) =
1 t > 1/2
where as pulse response of double integrator is denoted as l2 (t) and is given by
(R t
(
1
2t
dt
0
<
t
<
t2 ,
0 < t < 12
2
l2 (t) = 10 R t
=
+ 1 1dt 12 < t <
t 14 , 12 < t <
4
2

(10)

(11)

11

0 0.5

1
s

4 5

4 5

0 0.5

1
s2

7
4
3
4

Fig. 15: pulse responses at the output of integrators

we can write as follows



3 7 11
k1 [0 1 1 1 . . . .] + k2 0
. . . . = [0 2 3 4 5 . . . ]
4 4 4
3
k1 + k2 = 2
4
7
k1 + k2 = 3
4

(12)

(13)
and solve for k1 and k2 by taking any pair of equations, we get k1 =

5
4

and k2 = 1.