ADA2200SDP-EVALZ User Guide

UG-787
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com

Software Programmable Evaluation Board for the

ADA2200 Synchronous Demodulator
evaluation of the ADA2200 by simplifying signal connections
to standard test equipment. Inputs, outputs, supplies, and other
circuit test points on the board are easily accessed via test clips,
differential probes, or standard SMA cables. On-board signal
conditioning circuitry offers many options for testing different
circuit schemes.

FEATURES
Simple synchronous demodulation development platform
USB powered
Evaluation board compatible with Analog Devices, Inc.,
system demonstration platform (SDP-S or SDP-B)
SPI or EEPROM programmable
Input and output signal conditioning circuitry
Synchronization signals available for external devices

The ADA2200SDP-EVALZ evaluation board mates with the

EVAL-SDP-CS1Z SDP-S board or the EVAL-SDP-CB1Z SDP-B
controller board. The controller board provides an interface
between the ADA2200SDP-EVALZ evaluation board and a PC
USB port. The controller board can be purchased separately.

ADDITIONAL EQUIPMENT
PC running Windows XP or more recent version
SDP-S (EVAL-SDP-CS1Z) or SDP-B (EVAL-SDP-CB1Z)
controller board
Function generator
Oscilloscope and/or digital voltmeter

The PC resident ACE software provides an intuitive GUI, allowing

all of the ADA2200 modes of operation to be configured over the
SPI port. The ACE software also has plug-in modules for many
other Analog Devices evaluation boards and CFTL demo boards.

SOFTWARE
GENERAL DESCRIPTION

Figure 2 shows the recommended configuration for initial

evaluation. See the Quick Start Procedure section for more
details.

This user guide describes the SDP-compatible evaluation

board for the ADA2200 synchronous demodulator. The
ADA2200SDP-EVALZ evaluation board facilitates the

Full specifications for the ADA2200 are available in the product

data sheet, which should be consulted in conjunction with this
user guide with using the evaluation board.

ACE software (see the ACE Software User Guide)

12875-001

EVALUATION BOARD PHOTOGRAPH

Figure 1.

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.

Rev. 0 | Page 1 of 12

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ADA2200SDP-EVALZ User Guide

TABLE OF CONTENTS
Features .............................................................................................. 1

Input Driver ...................................................................................6

Additional Equipment ..................................................................... 1

Output Filter ..................................................................................6

Software ............................................................................................. 1

Digital Outputs ..............................................................................7

General Description ......................................................................... 1

Jumpers ...........................................................................................7

Evaluation Board Photograph ......................................................... 1

Measuring Signals..............................................................................8

Revision History ............................................................................... 2

Input Signal Synchronization ......................................................8

Quick Start Procedure ...................................................................... 3

Output Signal Synchronization ...................................................8

Configuration Software ................................................................... 4

Signal Measurements ....................................................................8

Overview........................................................................................ 4

Amplitude Measurements ............................................................8

Software Tab Views .......................................................................... 5

Phase Measurements.....................................................................8

Detailed Board Description ............................................................ 6

Amplitude and Phase Measurements .........................................9

Power Supplies .............................................................................. 6

Evaluation Board Schematic ......................................................... 10

System Clock ................................................................................. 6

REVISION HISTORY
12/14Revision 0: Initial Version

Rev. 0 | Page 2 of 12

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QUICK START PROCEDURE

8.

Verify that a square wave (~7.8125 kHz) is present at

RCLK_OUT (J3). Connect RCLK_OUT to VINP (J7) with
an SMA cable.
9. Use the RCLK signal present on P1 to trigger an oscilloscope.
Observethat the demodulated output signals on TP27 and
TP28 and the SYNCO signal on TP29 match the waveforms
shown in Figure 3.
10. Measure the filtered output across J9 and J10 with a digital
multimeter (DMM). The output voltage should read
approximately 1.56 V.

Figure 2 shows the recommended configuration for initial

evaluation. Perform the test procedure in this section to ensure
that the bench setup is working properly prior to testing new
evaluation configurations.
Set up the ADA2200SDP-EVALZ default test bench by
completing the following steps:

3.

4.
5.

6.
7.

Table 1. Default Jumper Settings

Designator
P1
P2
P4
P5
P7

Position
Open
Open
Open
Open
2 and 3

P8

2 and 3

P9
P10
P12
JP1

1 and 2
1 and 2
Open
Open

Description
VINP test point
VINN test point
VOP test point
VON test point
INP of ADA2200 connected to +OUT
of AD8476 input buffer
INN of ADA2200 connected to OUT
of AD8476 input buffer
VOP connected to U4 LPF
Use external clock oscillator
VIP, VIN test point
AC-couple RCLK_OUT
OSCILLOSCOPE

RCLK_OUT

SMA CABLE

SYNC_OUT

CLKIN
2
CH1 5.00V BW CH2 100mV
CH3 5.00V BW CH4 100mV

M2.00m s
T

A CH1

3.00V

3.92000m s

DMM
VOP

VINP

ADA2200

VINN

VON
SDP
CONTROLLER
BOARD

USB

12875-002

2.

Install the ACE software on the PC by following the

instructions in the ACE Software User Guide. Exit the
ACE software program.
The ADA2200SDP-EVALZ evaluation board is configured
to work with the EVAL-SDP-CS1Z SDP-S controller board
by default. To use the EVAL-SDP-CB1Z SDP-B controller
board, remove R43.
Verify that the jumper configuration on the ADA2200SDPEVALZ evaluation board matches the settings shown in
Table 1.
Plug the SDP controller board into P3 of the
ADA2200SDP-EVALZ evaluation board.
Power the two boards by connecting J2 of the SDP-S
controller board to a PC USB port. A green LED lights on
each board when power is available.
Press S1 momentarily to reset the ADA2200.
Apply a 500 kHz clock to the CLKIN input. The input is high
input impedance and expects LVCMOS (3.3 V) level inputs.

Figure 2. Suggested Configuration for Quick Start, Showing Connections to Standard Test Equipment
OUTN

OUTP

2
3
1

RCLK

SYNCO

CH1 2V BW
CH2 500mV
CH3 500mV BW CH4 2V

B
B

W
W

M20s
T
3s

A CH1

1.72V

12875-003

1.

Figure 3. Expected RCLK_OUT, VOP, VON, and SYNC_OUT Waveforms

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ADA2200SDP-EVALZ User Guide

CONFIGURATION SOFTWARE
The ACE software enables configuration of the ADA2200 over a
USB port. This section introduces the key features of the program.
See the ACE Software User Guide for download instructions
and a more complete description of the program.

OVERVIEW
With the SDP controller board and the ADA2200SDP-EVALZ
evaluation board connected together, plug the USB cable from
the PC into the SDP controller board. (Always plug the SDP
controller board and the ADA2200SDP-EVALZ evaluation
board together before connecting the USB cable to the PC).
Start the ACE software. The program opens in the Start view
tab; this tab shows which boards the program recognizes as
connected to your PC. The tab shows the ADA2200SDPEVALZ evaluation board as attached, as shown in Figure 4.
In the System tab, double-clicking the ADA2200SDP-EVALZ
evaluation board image opens the ADA2200 Eval Board tab, as
shown in Figure 5. This tab enables some basic configuration of

the ADA2200SDP-EVALZ evaluation board to be performed

through the menus available on the left hand side of the screen.
To make any changes effective in the hardware, click the Apply
button.
In the ADA2200 Eval Board tab, double-clicking the ADA2200
image opens the ADA2200 tab. This tab displays the ADA2200
block diagram and allows changes to the device configuration,
as shown in Figure 6. This tab also shows the frequencies expected
on some of the key clock signals. For the frequencies to match
the hardware, enter the actual CLKIN frequency in the CLKIN
field. The changes are not made to the hardware configuration
until the Apply Changes button is clicked.
In the ADA2200 tab, clicking the Proceed to Memory Map
button on the bottom right hand corner of the window opens
the ADA2200 Memory Map tab, as shown in Figure 7. This tab
allows access to all of the registers of the ADA2200. The changes
are not made to the hardware configuration until either the
Apply All or Apply Selected button is clicked.

Rev. 0 | Page 4 of 12

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12875-004

12875-006

SOFTWARE TAB VIEWS

Figure 4. Start Tab View

12875-005

12875-007

Figure 6. ADA2200 Tab View

Figure 5. ADA2200 Eval Board Tab View

Figure 7. ADA2200 Memory Map Tab View

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ADA2200SDP-EVALZ User Guide

DETAILED BOARD DESCRIPTION

POWER SUPPLIES

To bypass the AD8476, install the shunts of P7 and P8 between

Pin 1 and Pin 2. Alternatively, remove the shunts of P7 and P8,
and apply the input signal between TP18 and TP19.

The ADA2200SDP-EVALZ evaluation board accepts +5 V

power from the USB_VBUS pin of P3. The ADP151 regulates
this supply to +3.3 V and supplies the VIO and 3V3 rails for the
board.

OUTPUT FILTER

To run the board from an external power supply while still

using the ADP151 to regulate the power rails, remove E3 and
apply power to P6. Use a voltage from 3.6 V to 5.5 V to supply
the board through P6.

The OUTP and OUTN from the ADA2200 each have an RC

filter on the output, which can be used to set the bandwidth of
the demodulated output. By default, the output of the RC filter
appears on the VOP and VON connectors.

To run the board by supplying an external power supply to the

VIO and 3V3 rails directly, remove R55 and supply power to
TP35. Use a voltage from 3.0 V to 3.6 V to supply the board
through TP35.

Reconstruction Filter

This section provides details about the on-board circuitry

operation and some of the circuit options that are available.

SYSTEM CLOCK
By default, the ADA2200 CLKIN input is generated by the onboard ceramic resonator circuit. This circuit generates a
500 kHz clock. A footprint for a crystal is also provided to
facilitate generating frequencies of up to 1 MHz.
To run from an external clock source, install a jumper between
Pin 1 and Pin 2 of P10, which connects the clock input (J1)
buffer to the ADA2200 CLKIN pin. Note that the R32 of the
clock input is uninstalled by default. Signal sources expecting
a 50 termination drive twice the expected voltage onto this
connector.

INPUT DRIVER
By default, the AD8476 (A2) is configured to receive a singleended input on the VINP connector and to convert the signal to
differential. The differential output of the AD8476 is connected
to the INP and INN inputs of the ADA2200. The input impedance
of VINP is approximately 10 k. The AD8476 has unity gain;
therefore, 1 V applied to VINP results in 1 V differential applied
across INP to INN.
To use a differential input (between VINP and VINN) to the
AD8476, remove R25 and install a 0 resistor at R57.

Footprints are supplied for a low-pass filter (LPF) before the

INP and INN inputs of the ADA2200. For best performance,
keep the R30 and R31 series input resistors below 1 k.

There is an optional differential to single-ended reconstruction

filter on the evaluation board. To route the ADA2200 outputs
through the filter, install R26 and R27. To route the output of
the reconstruction filter to the VOP connector, install the shunt
of P9 between Pin 2 and Pin 3.
The board component population sets the reconstruction filter
corner frequency at 20 kHz. The following equations detail how
to redesign the filter for different frequency responses.
Choose the desired values for 3 dB frequency (fC), quality factor
(Q), gain (G), k (a number between 1 and 2 to give convenient
capacitor values), and R26 (R). The component values can be
calculated as follows:

C = 2 fC
R27 = R
C15 = k Q R (G + 1)/(2 C G R2)
R33 = G R
R47 = R52 = 2 R33
R34 = R35 = R R33/(2 R R33 C15 (C/Q) R R33)
C16 = C19 = 1/(2 R34 R33 C15 C2)
An excel spreadsheet that performs these calculations is
available on the ADA2200 Evaluation Board Wiki Page.

Rev. 0 | Page 6 of 12

ADA2200SDP-EVALZ User Guide

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DIGITAL OUTPUTS

Table 2. Jumper Descriptions

RCLK_OUT and SYNC_OUT

Designator
P7

The RCLK signal from the ADA2200 is buffered by U6 and

appears on the RCLK_OUT connector (J3).

Shunt
1 and 2
2 and 3

The SYNCO signal from the ADA2200 appears on the

SYNC_OUT connector (J2). It is good practice to disable the
SYNCO signal when it is not being used, to minimize any
coupling of this signal on the board.

SPI Port Outputs

The SPI port signals are routed to the SDP connector through
the A3 and A4 switches. The switches isolate the ADA2200
from the SPI bus during initial boot up to avoid contention with
signals on the SDP board.
By default, the ADA2200SDP-EVALZ evaluation board is
configured so that the ADA2200 is running in 3-wire SPI mode.
To run the ADA2200 in 4-wire mode, install R41.

P8

1 and 2
2 and 3

P9

1 and 2
2 and 3

P10

1 and 2
2 and 3
Open
1 and 2

JP1

JUMPERS
Table 2 provides a summary of the jumper configuration
options for the ADA2200SDP-EVALZ evaluation board.

Rev. 0 | Page 7 of 12

Description
VINN (J8) connects to INN of
ADA2200
VINN (J8) connects to AD8476 input
driver
VINP (J7) connects to INP of ADA2200
VINP (J7) connects to AD8476 input
driver
VOP (J9) connects to OUTP
VOP (J9) connects to VOUT of the
ADA4841-1 reconstruction filter
amplifier
Use external clock for CLKIN
Use on-board clock for CLKIN
AC-couple RCLK_OUT
DC-couple RCLK_OUT

UG-787

ADA2200SDP-EVALZ User Guide

MEASURING SIGNALS
By default, the ADA2200 filters and demodulates signals located
exactly at 1/64 of its clock frequency (fCLKIN). For example, when
using the 400 kHz on-board oscillator, the demodulated signal
frequency must be 6.25 kHz. The ADA2200 provides the RCLK
reference signal to facilitate synchronization of the modulation
signal to this internal demodulation clock.
The RCLK signal can be used directly to excite a sensor, or as a
trigger for an excitation drive signal, or as a reference clock to a
phase-locked loop (PLL) used as the excitation signal clock source.

OUTPUT SIGNAL SYNCHRONIZATION

The SYNCO output synchronization pulse generated by the
ADA2200 is available on the SYNC_OUT connector. The
ADA2200 generates this pulse every time the output is updated
and ready to be sampled. The frequency of this pulse is 1/8 the
clock frequency. By default, the pulse polarity is positive, and it
is generated 6.5 clock cycles after the last output update.
When the ADA2200 is clocked by the on-board oscillator
circuit, the frequency of the SYNCO pulse is 50 kHz; the pulse
duration is one clock cycle or 2.5 s (12.5% duty cycle); and the
pulse occurs 16.25 s after the last output update. The polarity
and its occurrence relative to the output update event can be
configured for different applications.
Table 3. Default Clock Frequencies Relative to fCLKIN
Ratio
1
1
1/2
1/8
1/16
1/8
1/64
1/64
1/64

Description
Master clock
Input sampling rate
Input sampling Nyquist rate
Output sampling rate
Output sampling Nyquist rate
Synchronization pulse frequency
Reference clock frequency
Band-pass filter center frequency
Mixer frequency

If the ADA2200 output is sampled by an ADC, synchronizing

the ADA2200 CLKIN input to the ADC conversion clock
eliminates the need for an analog reconstruction filter. When
the ADC samples the ADA2200 output synchronously, the
ADC sampling inherently rejects the frequency artifacts created
by the ADA2200 output sampling. The demodulation process
creates output ripple at the mixing frequency. This output ripple
can be removed digitally by performing a cycle mean of the
output samples or by a moving average filter.

AMPLITUDE MEASUREMENTS
If the relative phase of the input signal to the ADA2200 remains
constant, the output amplitude is directly proportional to the
amplitude of the input signal. Note that the signal gain is a function
of the relative phase of the input signal. Figure 8 shows the
relationship between the cycle mean output and the relative phase.
1.2
1.0
0.8
0.6
0.4
83
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
0

45

90

135

180

225

RELATIVE PHASE (REL )

270

315

360

12875-008

Signal
fCLKIN
fSI
fSI_NYQ
fSO
fSO_NYQ
fSYNCO
fRCLK
fC
fM

high frequency components can be removed by following the

ADA2200 with a reconstruction filter.

CYCLE MEAN VALUE

INPUT SIGNAL SYNCHRONIZATION

Figure 8. Phase Transfer Function with Phase Delay of 83, 1 V rms Input

The cycle mean output voltage is

VCYCLEMEAN = Conversion Gain VIN(RMS) sin(REL DEL)
= 1.05 VIN(RMS) sin(REL DEL)

SIGNAL MEASUREMENTS
The signal present at the output of the ADA2200 depends on
the amplitude and relative phase of the signal applied at its
inputs. When the amplitude or phase is known and constant,
any output variations can be attributed to the modulated
parameter. Therefore, when the relative phase of the input is
constant, the ADA2200 performs amplitude demodulation.
When the amplitude is constant, the ADA2200 performs phase
demodulation.
The sampling and demodulation processes introduce additional
frequency components onto the output signal. If the output
signal of the ADA2200 is used in the analog domain or if it is
sampled asynchronously to the ADA2200 sample clock, these

Therefore, the highest gain, and thus the largest signal-to-noise

ratio measurement, is obtained when operating the ADA2200
with REL = DEL + 90 = 173. This value of REL is also the
operating point with the lowest sensitivity to changes in the
relative phase. Operating with REL = DEL 90 = 7 offers the
same gain and measurement accuracy, but with a sign inversion.

PHASE MEASUREMENTS
If the amplitude of the input signal to the ADA2200 remains
constant, the output amplitude is a function of the relative
phase of the input signal. The relative phase can be measured as

Rev. 0 | Page 8 of 12

REL = sin1(VCYCLEMEAN/(Conversion Gain VIN(RMS))) + DEL

= sin1(VCYCLEMEAN/(1.05 VIN(RMS))) + DEL

ADA2200SDP-EVALZ User Guide

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Note that the output voltage scales directly with the input signal
amplitude. A full-scale input signal provides the greatest phase
sensitivity (V/REL) and thus the largest signal-to-noise ratio
measurement.
The phase sensitivity also varies with relative phase. The
sensitivity is at a maximum when REL = 83. Therefore, the
optimal measurement range is for input signals with a relative
phase equal to the phase delay of 45. This range provides
the highest gain and thus the largest signal-to-noise ratio
measurement. This range is also the operating point with the
lowest sensitivity to changes in the relative phase. Operating at
a relative phase equal to the phase delay of 135 to 225
offers the same gain and measurement accuracy, but with a
sign inversion.

If the signal amplitude remains nearly constant for the duration

of the measurement, it is possible to measure both the I and the
Q components of the signal by toggling the PHASE90 bit
between two consecutive measurements. To measure the I
component, set the PHASE90 bit to 0. To measure the Q
component, set the PHASE90 bit to 1.
After both the I and Q components have been obtained, it is
possible to separate the effects of the amplitude and phase
variations. Then, calculate the magnitude and relative phase
using the following formulas:
A = I 2 + Q2
REL = cos 1 Q A + DEL

The phase sensitivity with a 4 V p-p differential input operating

with a relative phase that is equal to the phase delay results in a
phase sensitivity of 36.6 mV/REL.

Or alternatively,

AMPLITUDE AND PHASE MEASUREMENTS

The inverse sine or inverse cosine functions linearize the

relationship between the relative phase of the signal and the
measured angle. Because the inverse sine and inverse cosine
are only defined in two quadrants, the sign of I and Q must be
considered to map the result over the entire 360 range of
possible relative phase values. The use of the inverse tangent
function is not recommended because the phase measurements
become extremely sensitive to noise as the calculated phase
approaches 90.

When both the amplitude and relative phase of the input signals
are unknown, it is necessary to obtain two orthogonal
components of the signal to determine its amplitude, relative
phase, or both. These two signal components are referred to as
the in-phase (I) and quadrature (Q) components of the signal.
A signal with two known rectangular components is represented
as a vector or phasor with an associated amplitude and phase
(see Figure 9).
II

REL = sin 1 I A + DEL

I
A
Q

III

IV

12875-009

Figure 9. Rectangular and Polar Representation of a Signal

Rev. 0 | Page 9 of 12

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ADA2200SDP-EVALZ User Guide

EVALUATION BOARD SCHEMATIC

CLOCK INPUT

SYNC OUTPUT

RCLK OUTPUT

PROTOTYPE
AREA

ADA2200

SIGNAL INPUT

SIGNAL OUTPUT

ADA2200
CONFIG
EEPROM

SDP CONFIG
EEPROM

EXT. POWER
INPUT PINS
SDP CONNECTOR

12875-010

BOARD STACKUP
LYR 1: SIGNAL
LYR 2: GND PLANE
LYR 3: PWR PLANE
LYR 4: SIGNAL

Figure 10. Evaluation Board Block Diagram

Rev. 0 | Page 10 of 12

SCK

SDO

N4

N3

I2C_ISOB

SCL

SDA

I2C BUS

FSM2JSMA

3V3

100

N2

N1

10K

R14

R5

C2

DNI

R45

WP

SCL

A2

A1

A0

GND

VCC

WPF

WHT

TP1

AT24C02C-PUM

R11

LAYOUT INSTRUCTIONS:
PLACE TSSOP-8 UNDER
DIP-8 SOCKET

SDA

DNI

5 SDO

U1

1UF

C31

R51
0

(8-LEAD PDIP OR EQUIVALENT)

AT24C02C-XHM-B

WPF 7

A2

A1

A0

390

R12

10K

DNI

680

R43

58

E3

63
64

MOSI
SS

EN

NC

VIN

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

MISO

MSCK

GND

VOUT

VIO

U5

VSS

VCC

WP

SCL

A2

A1

A0

GND

8
VDD

R18

49.9

S2

D2

IN1

0.1UF

C25

1UF

C26

ADG721BRMZ

IN2

D1

S1

49.9

R16

R15

R17

24LC32A-I/MS

SDA

SPI_ISOB

U2

SDP
CONFIG
EEPROM

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

ADP151AUJZ-3.3-R7

NC

NC

GND

GND

VIO(+3.3V)

GND

PAR_D22

PAR_D20

PAR_D18

PAR_D16

PAR_D15

GND

PAR_D12

PAR_D10

PAR_D8

PAR_D6

GND

PAR_D4

PAR_D2

PAR_D0

PAR_WR_N

PAR_INT

GND

PAR_A2

PAR_A0

PAR_FS2

PAR_CLK

GND

SPORT_RSCLK

SPORT_DR0

SPORT_RFS

SPORT_TFS

SPORT_DT0

SPORT_TSCLK

GND

SPI_SEL_A

SPI_MOSI

SPI_MISO

SPI_CLK

GND

SDA_0

SCL_0

GPIO1

GPIO3

GPIO5

GND

GPIO7

TMR_B

TMR_D

CLKOUT

NC

GND

NC

NC

NC

WAKE_N

SLEEP_N

GND

UART_TX

EXT. POWER INPUT (+5V)

1UF

C24

600OHM

DNI

VIN

NC

GND

GND

USB_VBUS

GND

PAR_D23

PAR_D21

PAR_D19

PAR_D17

GND

PAR_D14

PAR_D13

PAR_D11

PAR_D9

PAR_D7

GND

PAR_D5

PAR_D3

PAR_D1

PAR_RD_N

PAR_CS_N

GND

PAR_A3

PAR_A1

PAR_FS3

PAR_FS1

GND

SPORT_TDV0

SPORT_TDV1

SPORT_DR1

SPORT_DT1

SPI_D2

SPI_D3

SERIAL_INT

GND

SPI_SEL_B_N

SPI_SEL_C_N

SPI_SEL1/SPI_SS_N

GND

SDA_1

SCL_1

GPIO0

GPIO2

GPIO4

GND

GPIO6

TMR_A

TMR_C

NC

NC

GND

NC

NC

NC

EEPROM_A0

RESET_OUT_N

GND

UART_RX

69157-102HLF

P6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

62

A3

R19

R55

SDA

SCL

I2C_ISOB

R20

BMODE1
TBD0603
100K

RESET_IN_N

IN2

D1

S1

GND

8
VDD

DNI

DNI

1K

R60

E1

S2

D2

IN1

VIO

C5

600OHM

RED

TP35

49.9

R36

ADG721BRMZ

R21
R22

R28

EEPROM TO BE INSTALLED:

DNI

110-43-308-41-001000

DNI

DNI

S2

D2

PIN 1

A1

IN1

A2

X2

WHT

GND

8
VDD

A0

* DO NOT INSTALL
3V3

TBD0603

SCK

C3

TP32

DNI

IN2

D1

S1

VIO

DNI

10K

R10

0.33UF

A1

ADG721BRMZ

0.1UF

C23

RESETB

BOOTB

100

R9

0.01UF

10K

R13

680

0
TBD0603

59

R46

S1

R8

TBD0603

A4

5-1814832-1

J8

69157-102HLF

P2

69157-102HLF

P1

VINN

VINP

R23

0.1UF

EXCKIN

5-1814832-1

J1

CSB

SDI

VINNA

VINPA

WHT

TP21

DNI

R57

R56

CLOCK INPUT

OPTIONAL +3.3V INPUT

SDO

SCK

5-1814832-1

J7

1MEG
1MEG

S2

DNI

1UF

SIGNAL INPUT

R25

3V3

R44

VIO

49.9
390

DS1

SML-310MTT86

3V3

1K

R29

600OHM

DNI

10K

R59

R58
10K
DNI

E2

3V3

BLK

DNI

10K

R3

DNI

10K

R1

INN

VOCM

INP

TP5

0.1UF

C38

BLK

V S
6

A2

BLK

AD8476

OUT

+OUT

0.1UF

NC

TP6

+V
S

C11

INPUT DRIVER

C27

61

0.01UF

TP9

BLK

GND

VCC

VINNO

VINPO

VINNBYP

VINPBYP

BLK
TP11

BLK

POSSIBLE TO ADTDF2

PLACE AS CLOSE AS

NC7SP17P5X

TP10

U3

P7

P8

R49

WHT

BLK

SDO

TP13

WHT

TP19

R41

BLK

TP16

TBD0603
DNI

BLK

C1

BLK

1K

R42

TBD0603

TP17

SELECTION

EXT/INT CLOCK

TBD0603
DNI

C12

69157-102HLF

RCLK

TP14

DNI

49.9

10

R31

10

R30

P12

C37

TP18

49.9

TP12

3V3

DNI

C13

VIN

CLKIN

GND

VCC

3V3

Y1

P10

CLKIN

U6

NC7SP17P5X

2
500KHZ

Y2

DNI

49.9

R50

GND

VDD

12

YEL

RCLK/SDO

BOOT

RST

VOCM

INN

INP

4.096MEGHZ

13

RCLK

BOOTB

CS/A0

OUTN

OUTP

C36

0.1UF

16

1MEG

JP1

10K

R48

RCLKOUT

2 69157-102HLF

2K

R54

XOUT

15
2

SDI
SCK

14

CSB

VON

10

VOP

11

ADA2200

R53

XOUT

SYNCO

SCLK/SCL

U4

0.1UF

C18

1UF

C28

SDIO/SDA

3V3FILT

J3

5-1814832-1

SYNCO

VOPF

P9

3V3

VOP

VON

R26

21K

R47

DNI

10.5K

R27

DNI

10.5K

DNI

680PF

C15

R52
21K

R33

20K

R35

20K

R34

10.5K
C19

C16
220PF

+IN

IN

3V3

POWERDOWN

220PF

69157-102HLF

P5

69157-102HLF

P4

S
+V
S

C30
0.1UF

U9
ADA4841-1YRZ

OUT

VOPF

J2

5-1814832-1

J10

J9

5-1814832-1

5-1814832-1

TP29
WHT
1

SYNC OUTPUT

49.9

R38

49.9

R40

WHT

TP28

49.9

R39

WHT

TP27

SIGNAL OUTPUT

OUTPUT RECONSTRUCTION FILTER

10

R37

TP25

KELVIN
CONNECTION

YEL

VIP

TP24

RESETB

DNI

P3

R32

C14

C33

0.1UF

100PF

0.01UF

WHT

C17

FX8-120S-SV(21)

10K

0.01UF

TP23

0.01UF

2
1
OS102011MS2QN1C

10K

DNI

R2

DNI

R4

R6

DNI

R7

10K

TBD0603

0.1UF

60

C4

C32

DS2

C6

C34

DNI
C22

0.1UF

C21

SML-310LTT86

C7

0.01UF

1UF

0.1UF
C10

R24
C8

0.01UF

SDP INTERFACE

0.1UF

49.9
1UF

100PF

DNI
DNI

3V3

0.1UF

Figure 11. Evaluation Board Schematic

C9

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C29

C35

C20
TBD0805

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TIME-DOMAIN FILTER

ADA2200SDP-EVALZ User Guide

UG-787

UG-787

ADA2200SDP-EVALZ User Guide

NOTES

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the Evaluation Board), you are agreeing to be bound by the terms and conditions
set forth below (Agreement) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (Customer) and Analog Devices, Inc.
(ADI), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
Third Party includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMERS POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADIS TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG12875-0-12/14(0)

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