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PEARS For Advanced Users

and beyond
FPGA Accelerator

PEARS System Overview

PC (GNU RADIO /
MATLAB)

ZYNQ SOC

P.S.

A
X
I

Data ADC
& DAC

P.L

SPI

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Ethernet

RF
FRONTEND

AD9361

Digital Baseband Signal Processor

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Digital Baseband Signal Processor (DBSP)

board

The main component of DBSP board is Xilinx ZYNQ XC7Z030 SOC

ZYNQ XC7Z030 consists of dual-core ARM Cortex-A9 based
processing system and 28 nm Xilinx programmable logic KINTEX-7.
ZYNQ XC7Z030 is directly interfaced to the AD9361 in RF Frontend
The control signals are sent to RF interface through SPI line
(Programming of AD9361 registers)
Audio, HDMI, Ethernet, PCI express, SPI and SD card interfaces are
present in this DBSP board
The data communication between ARM and FPGA is through AXI
Bus.

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An overview of ZYNQ SOC

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The AXI CPU INTERCONNECT enables the interfaces between the

AXI compliant cores in FPGA and the processing system in ZYNQ.
The AD9361 core is used for receiving data from DAC and sending
data to ADC. This data is transferred to the ZYNQ processing system
through AXI interface.
The DDR interface, USB interface, Ethernet interface, SPI interface,
Quad SPI interface, and SD card interface are implemented in PS
using inbuilt peripherals in PS.
The address of AXI compliant blocks inside the FPGA are provided in
the address editor These address block details are used in the transfer
of data and control signals through AXI interface between PS and to
the respective blocks in PL

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Adding Processing Block in DBSP

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For adding Processing Block in receive path of DBSP, open the block
design in Vivado 14.2. The processing block for (channel i0) processing
received data can be added between util_adc_pack core and axi_ad9361
core.

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adc_valid - If set, indicates valid data (effective rate).

adc_data - The DMA adc data
adc_enable - If set, indicates DMA is enabled on this channel.

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Adding Processing Block in DBSP

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For adding Processing Block in transmit path of DBSP, open the block
design in Vivado 14.2. The processing block for (channel i0) processing
received data can be added between util_dac_unpack core and
axi_ad9361 core.

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 The tools required for adding processing blocks inside the

FPGA are Vivado 14.2 and Xilinx SDK14.2
After adding processing blocks generate bit stream file.
First stage boot loader (zynq_fsbl.elf) and Second stage boot
loader will be provided with SDRP (u-boot.elf)
Use the bit stream file, first stage boot loader and Second stage
boot loader to generate boot file (BOOT.bin)
Replace the BOOT.bin file already in the SD card with this
new boot file

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Adding Processing Block in DBSP

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Generating BOOT file

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 Open Xilinx SDK 14.2

Click create zynq boot image tab in xilinx tools
Create zynq boot image window as shown in image
will pop up
Select the files using add button
Provide output .bif file path
Then click create image
The BOOT.bin file get created in the given path
Copy this file to SD card
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Generating BOOT file

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Thank You

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