A 9.

99 mW Low-Noise Amplifier for 60 GHz WPAN System

and 77 GHz Automobile Radar System in 90 nm CMOS
Yo-Sheng Lin, Chien-Yo Lee, and Chih-Chung Chen
Department of Electrical Engineering, National Chi Nan University, Puli, Nantou, 545, Taiwan, ROC

VDD2
= 1.1 V

Abstract A low-power and wideband two-stage

millimeter-wave low-noise amplifier (LNA) for 60 GHz
WPAN (wireless personal area network) system and 77 GHz
automotive radar system using standard 90 nm CMOS
technology is reported. T-match technique is utilized to
achieve simultaneously wideband input and output
impedance matching, wideband power gain (S21) and
wideband NF at both 60-GHz-band and 77-GHz-band. The
LNA consumes only 9.99 mW, achieving S11 better than 10
dB for frequencies of 57.6~81.8 GHz, and S12 better than
29.1 dB for frequencies of 10~110 GHz. Additionally, high
and flat S21 of 11.21.5 dB is achieved for frequencies of
57.9~80.4 GHz, which means the corresponding 3-dB
bandwidth is 22.5 GHz. Furthermore, the LNA achieves
minimum noise figure (NF) of 4.8 dB at 76 GHz and NF of
6.21.4 dB for frequencies of 76~84 GHz, one of the best NF
results ever reported for a W-band CMOS LNA. At 79 GHz,
the measured input 1 dB compression point (P1dB) and input
third-order intercept point (IIP3) are 18.7 dBm and 7.4
dBm, respectively.
Index Terms 60 GHz, 77 GHz, LNA, millimeter-wave
(mm-wave), CMOS, WPAN, automotive radar

Cby5 =
3.699 pF

Output
Matching
Network

RFout

VDD1 = 0.8 V

Input
Matching
Network

TL4

TL1

RFin

C1 =
0.616 pF Cin

TL3

TL12

Cby4 =
4.932 pF

Cby3 =
3.699 pF
TL5

C3 =
TL14 0.616 pF

TL13

VG3
= 0.9V

TL10

C2 =
0.616 pF
TL6

M3
L/W = 0.1 m/3x10 m

TL11
TL9

TL7

M1
L/W =
0.1 m/3x8 m

M2
L/W =
0.1 m/3x10 m

TL8
Cby2 =
1.233 pF

TL2

VG2 = 0.6V
Cby1 =
1.849 pF

VG1 = 0.6V

(a)

I. INTRODUCTION
Recently, several excellent W-band CMOS/BiCMOS
LNAs have been reported [1]-[4]. For example, in [1], a
two-stage (a cacode input stage followed by a CS output
stage) wideband LNA suitable for commercial 71~76 GHz,
76~77 GHz and 77~81 GHz bands in 0.18 Pm SiGe
BiCMOS process with current-gain cut-off frequency
/maximum oscillation frequency (fT/fmax) of 200/200 GHz
was demonstrated. Though high and flat S21 of 13.80.7
dB and low NF of 6.9 dB were achieved, its PDC of 37
mW was not satisfactory. In [2], a single cascode stage
77~81 GHz LNA in 0.13 Pm SiGe HBT process with
fT/fmax of 230/280 GHz was demonstrated. Though low
PDC of 9 mW was achieved, its S21 of 8.51.5 dB and
simulated NF of 7.2 dB (at 82 GHz) were not good
enough. In [3], a five CS stages 76~77 GHz LNA in 90
nm CMOS process was demonstrated. Though high S21 of
110.5 dB was achieved, it NF of 7.8 dB and PDC of 25.8
mW were not satisfactory. In the current work, the
purpose is to demonstrate that low PDC (< 15 mW), high
S21 (> 10 dB), low NF (< 6 dB) and excellent phase
linearity (i.e. group delay variation smaller than 8 ps) can
be achieved simultaneously for a wideband LNA that is

15

-5

10

-10

S21 (dB)

20

-15

-20

Simulation

-5

-25

-10

-30

-15

-35

-20
65

70

75

80

S12 (dB)

978-1-4799-5507-7/15/$31.00 2015 IEEE

(b)
Fig. 1
(a) Schematic diagram, and (b) chip micrograph of the
57-81 GHz CMOS LNA.

-40
85

Frequency (Ghz)

Fig. 2
Simulated S21 and S12 versus frequency characteristics
of the LNA.

65

RWS 2015

14

Measurement

12
10

-10 dB

-10

NF (dB)

S11 (dB)

-5

-15
-20

8
6
4
2

-25
-30
50

55

60

65

70

75

80

0
74

85

(a)

Fig. 4
LNA.

-5

10

-10

14

-15

12

-20
-25

-10

-30

-15

-35
65

70

75

80

S12 (dB)

-5

60

Power Gain (dB)

15

S21 (dB)

-20
55

78

80

82

84

86

Measured NF versus frequency characteristics of the

20

Measurement

76

Frequency (GHz)

Frequency (Ghz)

Measurement

-40
85

10

6
4

0
-40

(b)
Fig. 3
Measured (a) S11, and (b) S21 and S12 versus frequency
characteristics of the LNA.

 dB

Frequency (Ghz)

Frequency : 79 GHz

P1dB =
18.7 dBm

Measurement
-35

-30

-25

-20

-15

Input Power (dBm)

Fig. 5
Measured power gain
characteristics of the LNA at 79 GHz.

suitable for commercial 57~64 GHz and 77~81 GHz

bands by using a cost-effective 90 nm CMOS technology.

versus

input

power

gm1. All transistors (M1~M3) have the same gate length of

100 nm, and gate width per finger of 3 Pm. Finger number
is 8 and 10, respectively, for transistor M1 and transistors
M2~M3. The simulated PDC of the LNA is 9.99 mW in the
bias condition of VDD1 = 0.8 V, VDD2 = 1.1 V, VG1 = VG2 =
0.6 V, VG3 = 0.9 V, Id1 = 5.28 mA and Id2 = 5.24 mA. As a
result, the LNA exhibits high and flat S21, small group
delay variation and excellent NF at the same time.
Fig. 2 shows the simulated S12 and S21 versus
frequency characteristics of the LNA. High and flat S21 of
10.11.5 dB is achieved for frequencies of 64.8~84.6
GHz. That is, the corresponding 3-dB bandwidth of S21 is
19.8 GHz. In addition, the LNA achieves S12 better than
29.1 dB for frequencies of 50~100 GHz.

II. CIRCUIT DESIGN

The CMOS LNA was designed and implemented by a
standard 90 nm CMOS process. The transmission-line (TL)
inductors are implemented with the 3.4-Pm-thick topmost
metal (M9) to minimize the resistive loss.
Fig. 1(a) shows the schematic diagram of the W-band
CMOS LNA with important device parameters and bias
voltages labeled. It constitutes a common-source (CS)
input stage followed by a cascode output stage. Cin is
parasitic capacitance of the input coupling capacitor C1.
That is, the equivalent capacitance between the bottom
metal of C1 and silicon substrate. To maximize the 3 dB
bandwidth of S21, the output of each stage was
equivalently loaded with a low-Q RLC parallel resonant
circuit. Over the 57~81 GHz band of interest, the load
resonant frequency of the input stage and the output stage
are close to the lower corner frequency and the upper
corner frequency, respectively. Based on the methodology
in [5], simultaneous input impedance and noise matching
over the 57~81 GHz band of interest were achieved by
appropriately selecting the values of TL1~ TL14 as well as
the size and bias of the input transistor M1, i.e. Cgs1 and

III. MEASUREMENT RESULTS AND DISCUSSIONS

The chip micrograph of the finished circuit is shown in
Fig. 1(b). The chip area is 724u761 Pm2 excluding the test
pads. On-wafer S-parameters, NF and linearity
measurements were performed by Agilent E7350A
network analyzer (2~110 GHz), Agilent E5052A NF
analyzer (75~110 GHz), and Agilent E4448A spectrum
analyzer (2~110 GHz), respectively. The LNA was biased

66

TABLE I
SUMMARY OF THE IMPLEMENTED 57-81 GHZ LNA, AND RECENTLY REPORTED STATE-OF-THE-ART W-BAND LNAS.
Frequency 3-dB BW
(GHz)
(GHz)

S11
(dB)

S21
(dB)

NF
(dB)

GD
Variation

P1dB
(dBm)

IIP3
(dBm)

PDC
(mW)

FOM
(GHz/mW)

Technology (ft/fmax in GHz)

This Work

58~77

22.5

<10

11.21.5

4.8

18.7

7.4

10

4.04

90 nm CMOS (151/148)

[1] 2010 MWCL

77~81

14.5

<11

13.80.7

6.9

NA

11.4

NA

37

0.49

0.18 Pm SiGe BiCMOS (200/200)

[2] 2011 NEWCAS

77~81

6.5

<10

8.51.5

7.2
(Simulation)

NA

18

NA

0.45

0.13 Pm SiGe BiCMOS

(230/280)

[3] 2012 IEEE RFIT

76~77

10

11

7.8

NA

40

NA

25.8

0.19

65 nm CMOS (NA/NA)

NA

18
(Simulation)

0.73

0.25 Pm SiGe-C BiCMOS

(190/220)

[4] 2012 MWCL

66~78

12

<5

21.3

7.6

in the condition of VDD1 = 0.8 V, VDD2 = 1.1 V, VG1 = VG2

= 0.6 V, VG3 = 0.9 V, Id1 = 5.27 mA and Id2 = 5.25 mA.
That is, the power consumption of the LNA is 9.99 mW.
Fig. 3(a) shows the measured S11 versus frequency
characteristics of the LNA. The LNA achieves S11 better
than 10 dB for frequencies of 57.6~81.8 GHz. Fig. 3(b)
shows the measured S21 and S12 versus frequency
characteristics of the LNA. High and flat S21 of 11.21.5
dB is achieved for frequencies of 57.9~80.4 GHz. This
means the corresponding 3-dB bandwidth is 22.5 GHz. In
addition, S12 is better than 29.1 dB for frequencies of
10~110 GHz.
Fig. 4 shows the measured NF versus frequency
characteristics of the LNA. The LNA achieves minimum
noise figure (NF) of 4.8 dB at 76 GHz and NF of 6.21.4
dB for frequencies of 76~84 GHz, one of the best NF
results ever reported for a W-band CMOS LNA.
Fig. 5 shows the measured power gain versus input
power characteristics of the LNA at 79 GHz. The
corresponding P1dB is 18.7 dBm. In addition, the
measured IIP3 is 7.4 dBm (not shown here).
In most previous work, the cut-off frequency (i.e.
technology cost), fT, of the transistors used is not reported.
Therefore, if fT is neglected, a figure of merit (FOM)
suitable for evaluating the performance of wideband
LNAs can be defined as below [5]:

FOM [GHz/mW]=

S21[1] BW[GHz] ,
(NF 1)[1] PDC[mW]

NA

40

low PDC but one of the lowest NFs and highest FOMs. The
results indicate that the proposed LNA architecture is very
promising for 60 GHz and 77 GHz dual-band
communication system applications.
VI. CONCLUSION
In this work, we demonstrate a low power and low NF
57~81 GHz CMOS LNA. The LNA comprises a commonsource stage, followed by a cascode stage. The LNA
consumes 9.99 mW, achieving high and flat S21 of
11.21.5 dB for frequencies of 57.9~80.4 GHz. The
corresponding 3 dB bandwidth is 22.5 GHz. In addition,
the LNA achieves minimum NF of 4.8 dB at 76 GHz and
NF of 6.21.4 dB for frequencies 76~84 GHz, one of the
best NF results ever reported for a W-band CMOS or
SiGe BiCMOS LNA. The impressive results from this
work signify the high potential of the proposed LNA
architecture in 60 GHz and 77 GHz dual-band transceiver
applications.
REFERENCES
[1] A. Y. K. Chen et. al., "A Low-Power Linear SiGe BiCMOS
Low-Noise Amplifier for Millimeter-Wave Active Imaging,"
IEEE Microwave and Wireless Components Letters, vol. 20,
no. 2, pp. 103-105, Feb. 2010.
[2] D. N. Demirel et. al., "Millimeter-Wave Chip Set for 77-81
GHz Automotve Radar Application," IEEE New Circuits and
Systems Conference, pp. 253-256, 2011.
[3] H. V. Le et. al., " A 77 GHz CMOS Low Noise Amplifier for
Automotive Radar Receiver," IEEE Radio-Frequency
Integration Technology (RFIT), pp.174-176, 2012.
[4] A. C. Ulusoy et. al., "A 60 to 77 GHz Switchable LNA in an
RF-MEMS Embedded BiCMOS Technology, " IEEE
Microwave and Wireless Components Letters, vol.22, no.8,
pp.430-432, Aug. 2012.
[5] H. W. Chiu, S. S. Lu, and Y. S. Lin, "A 2.17 dB NF, 5 GHz
Band Monolithic CMOS LNA with 10 mW DC Power
Consumption on a Thin (20 Pm) Substrate," IEEE Trans. on
Microwave Theory and Techniques, vol. 53, no. 3, pp. 813824, May 2005.

(1)

where S21[1] represents the average power gain in

magnitude; BW[GHz] represents the 3 dB-bandwidth in
GHz; (NF-1)[1] represents the excess NF in magnitude;
and PDC[mW] represents power dissipation in mW. This
FOM includes the most relevant parameters for evaluating
LNAs for low-power, high-gain, low-noise and wideband
applications. Table I is a summary of the implemented
57~81 GHz CMOS LNA, and recently reported state-ofthe-art W-band CMOS or SiGe BiCMOS LNAs in [1]-[4].
Compared with other work, our LNA exhibits not only

67