VLSI Design Lab Manual

VELAMMAL COLLEGE OF ENGG AND
TECHNOLOGY
VELAMMAL NAGAR, VIRAGANOOR
MADURAI-625009
EC67- VLSI Design Lab

LAB Manual
Prepared By:
P.Karthikeyan
Assistant Professor/ECE
&Head/ECE
Approved By:
Dr.S.Vasuki
Professor
Department of Electronics and

Communication Engineering
2013-2014
CONTENTS
1. Study of Simulation using tools.
2. Study of Synthesis tools.
3. Place and Root and Back annotation for FPGAs.
4. Basic logic gates
5. Half adder and full adder
6. Half Subtractor and full Subtractor
7. Encoder and decoder
8. Multiplexer and demultiplexer
9. Flip-Flops
10. Counters
11. Registers
12. Traffic light controller
13. Realtime Clock
14. Serial adder
15. Parallel Pipelined adder/Subtractor
16. Parallel Pipeline adder
VLSI DESIGN FLOW
ASIC DESIGN FLOW
Expt.No:
Date
:
STUDY OF SIMULATION TOOLS
AIM:
To Study the Verilog HDL/VHDL simulation tools for digital logic

verification.
THEORY:
Creating a Test Bench for Simulation:
In this section, you will create a test bench waveform containing input
stimulus you can use to simulate the counter module. This test bench
waveform is a graphical view of a test bench. It is used with a simulator
to verify that the counter design meets both behavioral and timing design
requirements. You will use the Waveform Editor to create a test bench
waveform (TBW) file.
1. Select the counter HDL file in the Sources in Project window.
2. Create a new source by selecting Project _ New Source.
3. In the New Source window, select Test Bench Waveform as the
source type, and type test bench in the File Name field.
4. Click Next.
5. The Source File dialog box shows that you are associating the test
bench with the source file: counter. Click Next.
6. Click Finish. You need to set initial values for your test bench
waveform in the Initialize Timing dialog box before the test bench
waveform editing window opens.
7. Fill in the fields in the Initialize Timing dialog box using the
information below:
Clock Time High: 20 ns.
Clock Time Low: 20 ns.
Input Setup Time: 10 ns.
Output Valid Delay: 10 ns.
Initial Offset: 0 ns
Global Signals: GSR (FPGA)
Leave the remaining fields with their default values.
8. Click OK to open the waveform editor. The blue shaded areas are
associated with each input signal and correspond to the Input Setup Time
in the Initialize Timing dialog box. In this tutorial, the input transitions
occur at the edge of the blue cells located under each rising edge of the
CLOCK input.
Fig 2: Waveform Editor - Test Bench
Fig 1:Waveform Editor - Initialize Timing Dialog Box
Fig 3:Waveform Editor - Expected Results

9. In this design, the only stimulus that you will provide is on the
DIRECTION port. Make the transitions as shown below for the
DIRECTION port:
Click on the blue cell at approximately the 300 ns clock transition.
The signal switches to high at this point.
Click on the blue cell at approximately the 900 ns clock transition.
The signal switches back to low.
Click on the blue cell at approximately the 1400 ns clock
transition. The signal switches to high again.
10. Select File _ Save to save the waveform. In the Sources in Project
window, the TBW file is automatically added to your project.
11. Close the Waveform Editor window.
Adding Expected Results to the Test Bench Waveform:
In this step you will create a self-checking test bench with expected
outputs that correspond to your inputs. The input setup and output delay
numbers that were entered into the Initialize Timing dialog when you
started the waveform editor are evaluated against actual results when the
design is simulated. This can be useful in the Simulate Post- Place &
Route HDL Model process, to verify that the design behaves as expected
in the target device both in terms of functionality and timing.
To create a self-checking test bench, you can edit output transitions
manually, or you can run the Generate Expected Results process:
1. Select the testbench.tbw file in the Sources in Project window.
2. Double-click the Generate Expected Simulation Results process.

This process converts the TBW into HDL and then simulates it in a
background process.
3. The Expected Results dialog box will open. Select Yes to post the
results in the waveform editor.
4. Click the + to expand the COUNT_OUT bus and view the transitions
that correspond to the Output Valid Delay time (yellow cells) in the
Initialize Timing dialog box.
5. Select File _ Save to save the waveform.
6. Close the Waveform Editor.Now that you have a test bench, you are
ready to simulate your design.
Simulating the Behavioral Model (ISE Simulator):
If you are using ISE Base or Foundation, you can simulate your design
with the ISE Simulator. If you wish to simulate your design with a
ModelSim simulator, skip this section and proceed to the Simulating the
Behavioral Model (ModelSim) section.
Fig 4:Simulator Processes for Test Bench
Fig 5:Behavioral Simulation in ISE Simulator
To run the integrated simulation processes in ISE:

1. Select the test bench waveform in the Sources in Project window. You
can see the Xilinx ISE Simulator processes in the Processes for Source
window.
2. Double-click the Simulate Behavioral Model process. The ISE
Simulator opens and runs the simulation to the end of the test bench.
3. To see your simulation results, select the test bench tab and zoom in
on the transitions. You can use the zoom icons in the waveform view, or
right click and select a zoom command.The ISE window, including the
waveform view.
4. Zoom in on the area between 300 ns and 900 ns to verify that the
counter is counting up and down as directed by the stimulus on the
DIRECTION port.
5. Close the waveform view window. You have completed simulation of
your design using the ISE Simulator. Skip past the ModelSim section
below and proceed to the Creating and Editing Timing and Area
Constraintssection.
Simulating the Behavioral Model (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design
using the integrated ModelSim flow. You can run processes from within
ISE which launches the installed ModelSim simulator.
To run the integrated simulation processes in ISE:
1. Select the test bench in the Sources in Project window. You can
see ModelSim Simulator processes in the Processes for Source
window in Fig 6.
Fig 6: Simulator Processes for Test Bench
Fig 7:Behavioral Simulation in ModelSim
2. Double-click the Simulate Behavioral Model process. The ModelSim

simulator opens and runs your simulation to the end of the test bench.
The ModelSim window, including the waveform, should look like Fig 7.
To see your simulation results, view the Wave window.
1. Right-click in the Wave window and select a zoom command.
counter is counting up
and down as directed by the stimulus on the DIRECTION port.
3. Close the ModelSim window.
RESULT:
10
Figure: RTL Viewer - Detailed View
11
Expt.No:
Date
:
STUDY OF SYNTHESIS TOOLS
AIM:
To study the Synthesis tools.
THEORY:
Now that you have created the source files, verified the designs behavior
with simulation,and added constraints, you are ready to synthesize and
implement the design.
Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the + sign next to
Implement Design. The Translate, Map, and Place & Route processes
are displayed. Expand those processes as well by clicking on the +
sign. You can see that there are many sub-processes and options that can
be run during design implementation.
3. Double-click the top level Implement Design process.ISE determines
the current state of your design and runs the processes needed to pull your
design through implementation. In this case, ISE runs the Translate, Map
and PAR processes. Your design is now pulled through to a placed-androuted state. This feature is called the pull through model.
4. After the processes have finished running, notice the status markers in
the Processes for Source window. You should see green checkmarks next
to several of the processes, indicating that they ran successfully. If there
are any yellow exclamation points, check the warnings in the Console tab
or the Warnings tab within the Transcript window. If a red X appears next
to a process, you must locate and fix the error before you can continue.
Verification of Synthesis:
Your synthesized design can be viewed as a schematic in the Register
Transfer Level (RTL) Viewer. The schematic view shows gates and
elements independent of the targeted Xilinx device.
1. In the Processes for Source window, double-click View RTL
Schematic found in the Synthesize - XST process group. The top
level schematic representation of your synthesized design opens in
the workspace.
12
2. Right-click on the symbol and select Push Into the Selected Instance
to view the schematic in detail.
The Design tab appears in the Sources in Project window, enabling you to
view the design hierarchy. In the schematic, you can see the design
components you created in the HDL source, and you can push into
symbols to view increasing levels of detail.
3. Close the schematic window.
Figure 1: Floorplanner View - Detailed View
13
Figure 2: Design Summary View
RESULT:
14
Expt.No:
Date
:
STUDY OF PLACE AND ROOT AND BACK

ANNOTATION FOR FPGAS.
AIM:
To study the Place and Root and Back annotation for FPGAs.
THEORY:
After implementation is complete, you can verify your design before
downloading it to a device.
Viewing Placement:
In this section, you will use the Floor planner to verify your pin outs and
placement. Floor planner is also very useful for creating area groups for
designs.
1. Select the counter source file in the Sources in Project window.
2. Click the + sign to expand the Place & Route group of processes.
3. Double-click the View/Edit Placed Design (Floorplanner) process.
The Floorplanner view opens.
4. Select View _ Zoom _ ToBox and then use the mouse to draw a box
around the counter instance, shown in green on the right side of the chip.
5. This Fig 1 shows where the entire design was placed. Click on any of
the components listed in the Design Hierarchy window to see where each
component is placed.
6. Zoom in to the right side of the chip even more, and place your mouse
over the K13pad. You can see that your pinout constraint was applied the DIRECTION pin is placed at K13.
7. Close the Floorplanner without saving.
Viewing Resource Utilization in Reports:
Many ISE processes produce summary reports which enable you to check
information about your design after each process is run. Detailed reports
are available from the Processes for Source window. You can also view
summary information and access most often-utilized reports in the Design
Summary.
1. Click on the Design Summary tab at the bottom of the window. If you
closed the summary during this tutorial, you can reopen it by doubleclicking the View Design Summary process.
15
Figure 3: Timing Analyzer - Timing Summary
Figure 4: FPGA Editor - Detailed View
16
2. In the Device Utilization Summary section, observe the number of

Slice Flip Flops that were used during implementation. You should see 4
flip flops, since you implemented a 4-bit counter.
3. To see other reports, scroll to the bottom of the Design Summary. You
can click on a report from here to view it in the ISE Text Editor.
Timing Closure:
In this section, you will run timing analysis on your design to verify that
your timing constraints were met. Timing closure is the process of
working on your design to ensure that it meets your necessary timing
requirements. ISE provides several tools to assist with timing closure.
1. In the Processes for Source window, under the Place & Route group of
processes, expand the Generate Post-Place & Route Static Timing
group by clicking the +sign.
2. Double-click the Analyze Post-Place & Route Static Timing process.
The Timing Analyzer opens.
3. To analyze the design, select Analyze Against Timing Constraints.
The Analyze with Timing Constraints dialog box opens.
4. Click OK. When analysis is complete, the timing report opens.
5. Select Timing summary from the Timing Report Description tree in
the left window. This displays the summary section of the timing report,
where you can see that no timing errors were reported.
6. Close the Timing Analyzer without saving.
Viewing the Placed and Routed Design:
In this section, you will use the FPGA Editor to view the design. You can
view your design on the FPGA device, as well as edit the placement and
routing with the FPGA Editor.
1. Double-click the View/Edit Routed Design (FPGA Editor) process
found in the Place & Route group of processes. Your implemented design
opens in the FPGA Editor.
2. Look in the List window to examine your design components.
3. Click on the COUNT_OUT K12 IOB in the List window to select the
row. This is one of the outputs in your design.
4. With the COUNT_OUT K12 row selected, select View _ Zoom
Selection. In the editor window, you can see the COUNT_OUT<0> IOB
highlighted in red.
5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB.
You should see Fig 4.
6. Enlarge the window and zoom in so you can see more detail. This view
shows the inside of an FPGA at the lowest viewable level. The blue line
shows the route that is used through the IOB. The red lines show the
routes that are available.
17
Figure 5: Simulator Processes for Test Bench
Figure 6: Timing Simulation in ISE Simulator
18
7. Verify that the signal goes to the pad as an output.

8. Close the FPGA Editor.
Timing Simulation (ISE Simulator):
You can verify that your design meets your timing requirements by
running a timing simulation. You can use the same test bench waveform
that was used earlier in the design flow for behavioral simulation.
When running timing simulation, the ISE tools create a structural HDL
file which includes timing information available after Place and Route is
run. The simulator will run on a model that is created based on the design
to be downloaded to the FPGA.
If you are using ISE Base or Foundation, you can simulate your design
with the ISE Simulator. To simulate your design with ModelSim, skip to
the Timing Simulation (ModelSim) section.
To run the integrated simulation processes:
1. Select the test bench waveform in the Sources in Project window. You
can see the ISE Simulator processes in the Processes for Source window.
2. Double-click the Simulate Post-Place & Route Model process.
This process generates a timing-annotated netlist from the implemented
design and simulates it. The resulting simulation is displayed in the
Waveform Viewer. These results look different than those you saw in the
behavioral simulation earlier in this tutorial. These results show timing
delays.
3. To see your simulation results, zoom in on the transitions and view the
area between 300 ns and 900 ns to verify that the counter is counting up
4. Zoom in again to see the timing delay between a rising clock edge and
an output transition.
5. Click the Measure Marker button and then click near the 300 ns
mark. Drag the second marker to the point where the output becomes
stable to see the time delay between the clock edge and the transition.
6. Close the waveform view window.You have completed timing
simulation of your design using the ISE Simulator. Skip past the
ModelSim section below, and proceed to the Creating Configuration
Data section.
Timing Simulation (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design
using theintegrated ModelSim flow. You can run processes from within
ISE which launches the installed ModelSim simulator.
1. To run the integrated simulation processes, select the test bench in the
Sources in Project window. You can see the ModelSim Simulator
processes in the Processes for Source window.
19
Figure 7: Simulator Processes for Test Bench
Figure 8: Timing Simulation in ModelSim
20
2. Double-click the Simulate Post-Place & Route VHDL/Verilog

Model process.
counter is counting up
4. Zoom in on the rising clock edges to see that the output transitions
occur slightly later
due to the timing delay.
5. Close the ModelSim window.
RESULT:
21
Expt.No:
Date
:
BASIC LOGIC GATES
AIM:
To write Verilog HDL program for Basic Logic gates and verify the output using
Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
1.Xilinx Spartan-3 Trainer Kit(XC3S400-PQ208)
2.PC with Windows XP OS
3.Xilinx ISE 10.1
PROCEDURE:
1. Start the Xilinx Project Navigator by using the desktop shortcut or by using the
Start
Programs
Xilinx ISE (10.1)
2. Create a new project. In window go to FILE
NEW PROJECT.
Specify the project name and location and say NEXT.
3. Select the family as Spartan 3, the device as XC3S400, package as PQ208 and
speed as -4.
4. Creating a verilog file. Click on the symbol of FPGA device and then right
Click
Click on new source
Verilog module and give the file
name and say next.
5. Define input and output ports.
6. Write the verilog code in verilog editor.
7. Check syntax. Run the Check syntax
Process window
Synthesize
check syntax, and debug errors if present.
8. Creating a test bench file. Click the symbol of FPGA device and then right click
Click on new source
Test Bench Waveform and give the name
Select Entity
Finish.
9. Select the desired parameters for simulating your design.
10. Simulate the code. Click on test bench file. Test bench file will open in main
window. Assign all the signals and save file. From the source of process window.
Click on simulate Behavioral model in process window.
11. Verify your design in wave window by seeing truth table of output signal with
respect to input signal. Close ISE simulator window.
12. Synthesize the design using ISE.For synthesizing your design, from the source
window select, synthesis/Implementation from the drop-down menu. Highlight
file in the sources in Project window. To run synthesis, right-click on synthesize,
and the run option or double-click on synthesize in the processes for current
source window.
13. Check the synthesis report. If there is any error correct it and rerun synthesis.
14. Create constraints file (UCF).Click on the symbol of FPGA device and then right
click
Click on new source
Implementation Constraints file and
give the name
Select entity
Finish. Click on user constraint and in
22
that double click on assign package pins option in process window. Xilinx PACE
window opens. Enter all the pins assignments in PACE, depending upon target
device and number of inputs and outputs used in your design.
15. Implementing a design, once synthesis is complete, use the Xilinx constraints
editor to add timing and location constraints for the implementation of your
design. This procedure runs you through the basic flow for implementation.
16. Generating programming file
Right click on generate programming file, choose the run option, or double left
click on generate programming file. This will generate the bit stream.
17. Downloading in boundary scan mode
Note; Xilinx provides 2-tools for downloading purpose
IMPACT-is a command line and GUI based tool PROM file formatter.
23
AND Gate:
Output:
#
#
#
#
#
#
#
#
#
AND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
0
1
0
0
1
1
1
-------------------------------------------------
PROGRAM:
AND Gate:
// Module Name: Andgate
module Andgate(i1, i2, out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule
// Module Name: Stimulus.v
24
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Andgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tAND Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
OR Gate:
25
Output:
#
#
#
#
#
#
#
#
#
OR Gate
-----------------------------------------------Input1
Input2
-----------------------------------------------0
0
0
0
1
1
1
0
1
1
1
1
------------------------------------------------
Output
OR Gate:
// Module Name: Orgate
module Orgate(i1, i2, out);
input i1;
input i2;
output out;
or(out,i1,i2);
endmodule
// Module Name: Simulus.v
module Simulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
26

Orgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tOR Gate");
$display("\t\t--------------------------------------");
$display("\t\t--------------------------------------");
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
NAND Gate:
Output:
#
#
#
#
#
#
#
#
#
NAND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
1
1
0
1
1
1
0
------------------------------------------------
27
NAND Gate:
// Module Name: Nandgate
module Nandgate(i1, i2, out);
input i1;
input i2;
output out;
nand(out,i1,i2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
Nandgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tNAND Gate");
$display("\t\t--------------------------------------");
$display("\t\t--------------------------------------");
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
28
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
NOR Gate:
Output:
#
#
#
#
#
#
#
#
#
NOR Gate
-----------------------------------------------Input1
Input2
-----------------------------------------------0
0
1
0
1
0
1
0
0
1
1
0
------------------------------------------------
Output
NOR Gate:
// Module Name: Norgate
module Norgate(i1, i2, out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
29
Norgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tNOR Gate");
$display("\t\t--------------------------------------");
$display("\t\t--------------------------------------");
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
XOR Gate:
Output:
#
#
#
#
#
#
#
#
#
XOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
1
1
0
1
1
1
0
-------------------------------------------------
30
XOR Gate:
// Module Name: Xorgate
module Xorgate(i1, i2, out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
Xorgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tXOR Gate");
$display("\t\t--------------------------------------");
$display("\t\t--------------------------------------");
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
31
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
XNOR Gate:
Output:
#
#
#
#
#
#
#
#
#
XNOR Gate
-----------------------------------------------Input1
Input2
-----------------------------------------------0
0
1
0
1
0
1
0
0
1
1
1
------------------------------------------------
Output
XNOR Gate:
// Module Name: Xnorgate
module Xnorgate(i1, i2, out);
32
input i1;
input i2;
output out;
xnor(out,i1,i2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
Xnorgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tXNOR Gate");
$display("\t\t--------------------------------------");
$display("\t\t--------------------------------------");
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
Not Gate:
33
Output:
#
#
#
#
#
#
#
NOT Gate
--------------------------Input
Output
--------------------------0
1
1
0
---------------------------
NOT Gate:
// Module Name: Notgate

module Notgate(in, out);
input in;
output out;
not(out,in);
endmodule
module Stimulus_v;
// Inputs
reg in;
// Outputs
wire out;
Notgate uut (
.in(in),
.out(out)
);
initial
begin
$display("\t\t NOT Gate");
$display("\t\t------------------------");
$display("\t\tInput\t\tOutput");
34
$display("\t\t------------------------");
$monitor("\t\t %b\t\t %b",in,out);
#2 $display("\t\t------------------------");
end
initial
begin
in=0;
#1 in=1;
#1 $stop;
end
endmodule
Buffer:
Output:
#
#
#
#
#
#
#
BUFFER
--------------------------Input
Output
--------------------------0
0
1
1
---------------------------
RESULT:
Expt. No:
Date
:
HALF ADDER AND FULL ADDER
35
AIM:
To write Verilog HDL program for Half Adder and Full Adder and verify the output
using Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
36
Half Adder:
Output:
#
#
#
Sum
#
#
#
#
#
#
Half Adder
-----------------------------------------------------------------Input1
Input2
Carry
-----------------------------------------------------------------0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
------------------------------------------------------------------
PROGRAM:
Half Adder:
// Module Name:
HalfAddr
37
module HalfAddr(sum, c_out, i1, i2);

output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire sum;
wire c_out;
HalfAddr uut (
.sum(sum),
.c_out(c_out),
.i1(i1),
.i2(i2)
);
initial
begin
$display("\t\t\t\t Half Adder");
$display("\t\t----------------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Carry\t\t Sum");
$display("\t\t----------------------------------------------");
$monitor("\t\t %b\t\t %b\t\t %b\t\t
%b",i1,i2,c_out,sum);
#4 $display("\t\t----------------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
Full Adder:
38
Output:
Full Adder
#
----------------------------------------------------------------------------------------------#
i1
i2
C_in
C_out
Sum
#
----------------------------------------------------------------------------------------------#
0
0
0
0
0
#
0
0
1
0
1
#
0
1
0
0
1
#
0
1
1
1
0
#
1
0
0
0
1
#
1
0
1
1
0
#
1
1
0
1
0
#
1
1
1
1
1
#
------------------------------------------------------------------------------------------------
39
Full Adder:
// Module Name: FullAddr
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule
module Stimulus_v;
// Inputs
reg i1;
reg i2;
reg c_in;
// Outputs
wire c_out;
wire sum;
FullAddr uut (
.i1(i1),
.i2(i2),
.c_in(c_in),
.c_out(c_out),
.sum(sum)
);
initial
begin
$display("\t\t\t\t\t\tFull Adder");
40
$display("\t\t----------------------------------------------------------------");
$display("\t\ti1\t\ti2\t\tC_in\t\t\tC_out\t\tSum");
$display("\t\t----------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t%b\t\t
%b",i1,i2,c_in,c_out,sum);
#9
$display("\t\t-------------------------------------------------------------------");
end
initial begin
i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 1;
#1 i1 = 0;i2 = 1;c_in = 0;
#1 i1 = 0;i2 = 1;c_in = 1;
#1 i1 = 1;i2 = 0;c_in = 0;
#1 i1 = 1;i2 = 0;c_in = 1;
#1 i1 = 1;i2 = 1;c_in = 0;
#1 i1 = 1;i2 = 1;c_in = 1;
#2 $stop;
end
endmodule
EXERCISE:
(i) Design a combinational circuit in verilog coding which performs three bits addition in
behavioral model
(ii) Design a combinational circuit in verilog coding which performs three bits addition in
structural model
(iii) Design a combinational circuit in verilog coding which performs two bits addition in
behavioral model and also using this circuit as a component to design the three bit adder in
structural model.
RESULT:
41
Expt. No:
Date
:
HALF SUBTRACTOR & FULL SUBTRACTOR
AIM:
To write Verilog HDL program for Half Subtractor & Full Subtractor and verify the
output using Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and verify the
output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
42
source window.
click
Click on new source
give the name
Select entity
Half Subtractor:
Output:
#
#
#
Difference
#
#
#
#
#
#
Half Subtractor
-----------------------------------------------------------------------Input1
Input2
Borrow
------------------------------------------------------------------------0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
------------------------------------------------------------------------
43
PROGRAM:
Half Subtractor:
// Module Name: HalfSub

module HalfSub(i0, i1, bor, dif);
input i0;
input i1;
output bor;
output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule
module Stimulus_v;
// Inputs
reg i0;
reg i1;
// Outputs
wire bor;
wire dif;
HalfSub uut (
.i0(i0),
.i1(i1),
.bor(bor),
.dif(dif)
);
initial
begin
44
$display("\t\t\t\t\tHalf Subtractor");
$display("\t\t----------------------------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Borrow\t\t Difference");
$display("\t\t----------------------------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b\t\t%b",i0,i1,bor,dif);
#4
$display("\t\t-----------------------------------------------------------");
end
initial
begin
i0=1'b0; i1=1'b0;
#1 i1=1'b1;
#1 i0=1'b1; i1=1'b0;
Full Subtractor:
Output:
#
#
Full Subtractor
----------------------------------------------------------------------------------------------#
B_in
I1
i0
B_out
Difference
#
----------------------------------------------------------------------------------------------#
0
0
0
0
0
#
0
0
1
0
1
#
0
1
0
1
1
#
0
1
1
0
0
#
1
0
0
1
1
#
1
0
1
0
0
#
1
1
0
1
0
#
1
1
1
1
1
45
#
------------------------------------------------------------------------------------------------
#1 i0=1'b1; i1=1'b1;
#1 $stop;
end
endmodule
Full Subtractor:
// Module Name: FullSub

module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule
module Stimulus_v;
// Inputs
reg b_in;
reg i1;
reg i0;
// Outputs
wire b_out;
wire dif;
FullSub uut (
.b_in(b_in),
46
.i1(i1),
.i0(i0),
.b_out(b_out),
.dif(dif)
);
initial
begin
$display("\t\t\t\t\t\tFull Subtractor");
$display("\t\t-------------------------------------------------------------------------");
$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference");
$display("\t\t-------------------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t
%b",b_in,i1,i0,b_out,dif);
#9
$display("\t\t-------------------------------------------------------------------------");
end
initial begin
// Initialize Inputs
b_in = 0;i1 = 0;i0 = 0;
#1 b_in = 0;i1 = 0;i0 =
#1 b_in = 0;i1 = 0;i0 =
#1 b_in = 0;i1 = 1;i0 =
#1 b_in = 0;i1 = 1;i0 =
#1 b_in = 1;i1 = 0;i0 =
#1 b_in = 1;i1 = 0;i0 =
#1 b_in = 1;i1 = 1;i0 =
#1 b_in = 1;i1 = 1;i0 =
#2 $stop;
end
endmodule
0;
1;
0;
1;
0;
1;
0;
1;
EXERCISE:
(i) Design a combinational circuit in verilog coding which performs three bits
Subtraction in behavioral model
(ii) Design a combinational circuit in verilog coding which performs three bits subtraction
in structural model
(iii) Design a combinational circuit in verilog coding which performs two bits
subtraction in behavioral model and also using this circuit as a component to design
the three bit subtractor in structural model
47
RESULT:
Expt No:
Date:
IMPLEMENTATION OF 2 x 4 DECODER AND

4 x 2 ENCODER
AIM:
To write Verilog HDL program for 2x4 Decoder & 4x2 Encoder and verify the
output using Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and verify the
output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
48
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
Encoder:
49
Output:
#
#
#
#
#
#
#
#
#
4to2 Encoder
------------------------------------Input
Output
------------------------------------1000
00
0100
01
0010
10
0001
11
------------------------------------
PROGRAM:
Encoder:
// Module Name: Encd2to4

module Encd2to4(i0, i1, i2, i3, out0, out1);
input i0;
input i1;
input i2;
input i3;
output out0;
output out1;
reg out0,out1;
always@(i0,i1,i2,i3)
case({i0,i1,i2,i3})
4'b1000:{out0,out1}=2'b00;
4'b0100:{out0,out1}=2'b01;
4'b0010:{out0,out1}=2'b10;
4'b0001:{out0,out1}=2'b11;
default: $display("Invalid");
endcase
endmodule
50

module Stimulus_v;
// Inputs
reg i0;
reg i1;
reg i2;
reg i3;
// Outputs
wire out0;
wire out1;
Encd2to4 uut (
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.out0(out0),
.out1(out1)
);
initial
begin
$display("\t\t
4to2 Encoder");
$display("\t\t------------------------------");
Decoder:
$display("\t\tInput\t\t\tOutput");
$display("\t\t------------------------------");
$monitor("\t\t%B%B%B%B\t\t\t %B
%B",i0,i1,i2,i3,out0,out1);
#4 $display("\t\t-------------------------------");
end
initial
begin
i0=1; i1=0; i2=0; i3=0;
51
#1
#1
#1
#1
i0=0; i1=1; i2=0; i3=0;

i0=0; i1=0; i2=1; i3=0;
i0=0; i1=0; i2=0; i3=1;
$stop;
end
endmodule
Decoder:
// Module Name: Decd2to4
module Decd2to4(i0, i1, out0, out1, out2, out3);
input i0;
input i1;
output out0;
output out1;
output out2;
output out3;
reg out0,out1,out2,out3;
always@(i0,i1)
case({i0,i1})
2'b00: {out0,out1,out2,out3}=4'b1000;
2'b01: {out0,out1,out2,out3}=4'b0100;
2'b10: {out0,out1,out2,out3}=4'b0010;
2'b11: {out0,out1,out2,out3}=4'b0001;
default: $display("Invalid");
endcase
endmodule
module Stimulus_v;
// Inputs
reg i0;
reg i1;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;
Output:
#
#
#
#
#
#
#
2to4 Decoder
------------------------------------Input
Output
------------------------------------00
1000
01
0100
10
0010
52
#
#
11
0001
------------------------------------

Decd2to4 uut (
.i0(i0),
.i1(i1),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
);
initial begin
$display("\t\t
2to4 Decoder");
$display("\t\t------------------------------");
$display("\t\tInput\t\t\tOutput");
$display("\t\t------------------------------");
$monitor("\t\t %b%b\t\t\t %b%b%b
%b",i0,i1,out0,out1,out2,out3);
#4 $display("\t\t------------------------------");
end
initial begin
i0=0;i1=0;
#1 i0=0;i1=1;
#1 i0=1;i1=0;
#1 i0=1;i1=1;
#1 $stop;
end
endmodule
53
EXERCISE:
(i)Design a Data flow model combinational circuit (8 inputs 3 outputs) in verilog
coding.
(ii) Design a Data flow model combinational circuit (3 inputs 8 outputs) in verilog
coding.
(iii) Design a Structural model combinational circuit (8 inputs 3 outputs) in verilog
coding.
RESULT:
Expt. No:
Date
:
MULTIPLEXER & DEMULTIPLEXER
AIM:
To write Verilog HDL program for 4 to 1 Multiplexer and 1 to 4 Demultiplexer and

verify the output using Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and
verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
54
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
Multiplexer:
55
Output:
#
#
#
#
#
#
#
#
#
#
#
4to1 Multiplexer
----------------------------------------------Input=1011
----------------------------------------------Selector
Output
----------------------------------------------{0,0}
1
{1,0}
0
{0,1}
1
{1,1}
1
-----------------------------------------------
PROGRAM:
Multiplexer:
// Module Name:
Mux4to1
56
module Mux4to1(i0, i1, i2, i3, s0, s1, out);

input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
module Stimulus_v;
// Inputs
reg i0;
reg i1;
reg i2;
reg i3;
reg s0;
reg s1;
// Outputs
wire out;
Mux4to1 uut (
.i0(i0),
.i1(i1),
.i2(i2),
.i3(i3),
.s0(s0),
.s1(s1),
.out(out)
);
Demultiplexer:
57
initial
begin
$display("\t\t\t 4to1 Multiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3);
$display("\t\t------------------------------------");
$display("\t\tSelector\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out);
#4 $display("\t\t------------------------------------");
end
initial
begin
i0=1; i1=0; i2=1; i3=1;
#1 s0=0; s1=0;
#1 s0=1; s1=0;
#1 s0=0; s1=1;
#1 s0=1; s1=1;
#1 $stop;
end
endmodule
Demultiplexer:
58
// Module Name: Dux1to4

module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;
output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
// Module Name: stimulus.v
module stimulus_v;
// Inputs
Output:
#
#
#
#
#
#
#
#
#
#
1to4 Demultiplexer
----------------------------------------------Input=1
----------------------------------------------Status
Output
----------------------------------------------{0,0}
1000
{0,1}
0100
{1,0}
0010
{1,1}
0001
---------------------------------------------
59
reg in;
reg s0;
reg s1;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;
Dux1to4 uut (
.in(in),
.s0(s0),
.s1(s1),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
);
initial
begin
$display("\t\t 1to4 Demultiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t\tInput=%b",in);
$display("\t\t------------------------------------");
$display("\t\tStatus\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t%b%b%b
%b",s1,s0,out0,out1,out2,out3);
#4 $display("\t\t------------------------------------");
end
initial
begin
in=1;
#1 s1=0;s0=0;
#1 s1=0;s0=1;
#1 s1=1;s0=0;
#1 s1=1;s0=1;
#1 $stop;
end
endmodule
60
EXERCISE:
(i) Design a serial to parallel converter (2 select lines) in verilog coding using case
statement.
(ii)Design a parallel to serial converter (2 select lines) in verilog coding using case
statement.
(iii)Design a serial to parallel converter (2 select lines) in verilog coding using if
statement.
(iv)Design a parallel to serial converter (2 select lines) in verilog coding using if
statement.
(v)Design a 8 to 1 MUX and 1to 8 DEMUX in verilog coding using dataflow model
RESULT:
Expt.No:
Date
:
FLIP-FLOPS
AIM:
To write Verilog HDL program for JK- FilpFlop,D-FlipFlop and T-FlipFlop and
verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
61
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
Flip-Flop:
D Flip-Flop:
62
Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
D FipFlop
-------------------------------------------------------------------------Clock
Reset
Input (d)
Output q(~q)
--------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
--------------------------------------------------------------------------
PROGRAM:
D Flip-Flop:
// Module Name: DFF

module DFF(Clock, Reset, d, q);
input Clock;
input Reset;
63
input d;
output q;
reg q;
always@(posedge Clock or negedge Reset)
if (~Reset) q=1'b0;
else q=d;
endmodule
module Stimulus_v;
// Inputs
reg Reset;
reg Clock;
reg d;
// Outputs
wire q;
DFF uut (
.Clock(Clock),
.Reset(Reset),
.d(d),
.q(q)
);
initial
begin
$display("\t\t\t\t\tD FipFlop");
$display("\t\t------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (d)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d
\t\t
%d(%d)",Clock,Reset,d,q,~q);
#15
$display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;d=0;
#2 Reset=0; d=1;
T Flip-Flop:
64
Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
T FipFlop
--------------------------------------------------------------------------Clock
Reset
Input (t)
Output q(~q)
--------------------------------------------------------------------------0
0
0
0(1)
1
0
0
0(1)
0
0
1
0(1)
1
0
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
1
1
0(1)
1
1
1
1(0)
0
1
0
1(0)
1
1
0
1(0)
0
1
1
1(0)
1
1
1
0(1)
0
0
0
0(1)
1
0
0
0(1)
0
0
0
0(1)
--------------------------------------------------------------------------
#2 d=0;
#2 Reset=1; d=1;
#2
d=0;
65
#2 d=1;
#2 Reset=0; d=0;
#1; // Gap for display.
#2 $stop;
end
endmodule
T Flip-Flop:
// Module Name: TFF
module TFF(Clock, Reset, t, q);
input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset) q=0;
else if (t) q=~q;
else q=q;
endmodule
module Stimulus_v;
// Inputs
reg Clock;
reg Reset;
reg t;
// Outputs
wire q;
TFF uut (
.Clock(Clock),
.Reset(Reset),
.t(t),
.q(q)
);
initial
begin
$display("\t\t\t\t\tT FipFlop");
JK Flip-Flop:
66
$display("\t\t------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (t)\t\tOutput q(~q)");
$display("\t\t------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t %d
\t\t
%d(%d)",Clock,Reset,t,q,~q);
#15
$display("\t\t------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;t=0;
#2 Reset=0; t=1;
#2 t=0;
#2 Reset=1; t=1;
#2
t=0;
#2 t=1;
#2 Reset=0; t=0;
#2 $stop;
end
endmodule
JK Flip-Flop:
Program:
// Module Name: JKFF

module JKFF(Clock, Reset, j, k, q);
input Clock;
input Reset;
input j;
input k;
output q;
reg q;
67
always@(posedge Clock, negedge Reset)

if(~Reset)q=0;
else
begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;
endcase
end
endmodule
Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
JK FipFlop
-------------------------------------------------------------------------Clock
Reset
Input (j,k)
Output q(~q)
-------------------------------------------------------------------------0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,1)
0(1)
1
0
(0,1)
0(1)
0
0
(1,0)
0(1)
1
0
(1,0)
0(1)
0
0
(1,1)
0(1)
1
0
(1,1)
0(1)
0
1
(0,0)
0(1)
1
1
(0,0)
0(1)
0
1
(0,1)
0(1)
1
1
(0,1)
0(1)
0
1
(1,0)
0(1)
1
1
(1,0)
1(0)
0
1
(1,1)
1(0)
1
1
(1,1)
0(1)
0
0
(0,0)
0(1)
1
0
(0,0)
0(1)
0
0
(0,0)
0(1)
-------------------------------------------------------------------------
68

module Stimulus_v;
// Inputs
reg Clock;
reg Reset;
reg j;
reg k;
// Outputs
wire q;
JKFF uut (
.Clock(Clock),
.Reset(Reset),
.j(j),
.k(k),
.q(q)
);
initial
begin
$display("\t\t\t\t\tJK FipFlop");
$display("\t\t--------------------------------------------------------------");
$display("\t\tClock\t\tReset\t\tInput (j,k)\t\tOutput
q(~q)");
$display("\t\t--------------------------------------------------------------");
$monitor("\t\t %d \t\t %d \t\t (%d,%d)
\t\t
%d(%d)",Clock,Reset,j,k,q,~q);
#19
$display("\t\t--------------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0; Reset=0;
j=0; k=0;
69
#2 j=0; k=1;
#2
j=1; k=0;
#2
j=1; k=1;
#2 Reset=1;
j=0; k=0;
#2
j=0; k=1;
#2 j=1; k=0;
#2 j=1; k=1;
#2 Reset=0; j=0; k=0;
#2 $stop;
end
endmodule
EXERCISE:
(i)Design a synchronous reset flip-flop in behavioral model (Realize a flip-flop by
using SR flip-flop as S&R in single input).
(ii) Design a synchronous reset flip-flop which having capability of divide by 2 in
behavioral model.
(iii)Design a synchronous reset flip-flop in behavioral model (Realize a flip-flop by
using JK flip-flop with J=K=1).
RESULT:
Expt No:
Date:
IMPLEMENTATION OF COUNTERS
70
AIM:
To write Verilog HDL program for Counters and verify the output using Xilinx ISE
10.1 version. To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
71
Counter:
PROGRAM:
2- Bit Counter:
// Module Name: Count2Bit
module Count2Bit(Clock, Clear, out);
input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))out=2'b00;
else out=out+1;
endmodule
module Stimulus_v;
// Inputs
reg Clock;
reg Clear;
// Outputs
wire [1:0] out;
Count2Bit uut (
.Clock(Clock),
.Clear(Clear),
.out(out)
72
);
initial
begin
$display("\t\t\t 2 Bit Counter");
$display("\t\t----------------------------------------");
$display("\t\tClock\t\tClear\t\tOutput[2]");
$display("\t\t----------------------------------------");
$monitor("\t\t %b\t\t %b \t\t
%b ",Clock,Clear,out);
#28 $display("\t\t----------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0;Clear=0;
#10 Clear=1;
#16Clear=0;
#2 $stop;
end
endmodule
Output:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2 Bit Counter
--------------------------------------------------Clock
Clear
Output[2]
--------------------------------------------------0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
0
00
1
0
00
0
1
00
1
1
01
0
1
01
1
1
10
0
1
10
1
1
11
0
1
11
1
1
00
0
1
00
1
1
01
0
1
01
1
1
10
73
#
#
#
#
#
#
#
0
1
10
1
1
11
0
1
11
1
1
00
0
0
00
1
0
00
------------------------------------------------
EXCERCISE
(i) Design a frequency divider in verilog coding which having capability of frequency
dividing in both the directions
(ii) Design a counter in Verilog coding for given counting sequence.
0000,0001,0010,0011,0100,0101,0110,0111,0110,0101,0100,0011,0001,0000
RESULT:
Expt No:
Date:
IMPLEMENTATION OF REGISTERS
74
AIM: To write Verilog HDL program for Registers and verify the output using Xilinx
ISE 10.1 version.To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
75

Register:
OutPut:
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2 Bit Register
----------------------------------------------------------------------Clock
Clear
Input[2]
Output[2]
----------------------------------------------------------------------0
0
00
00
1
0
00
00
0
0
01
00
1
0
01
00
0
0
10
00
1
0
10
00
0
0
11
00
1
0
11
00
0
1
00
00
1
1
00
00
0
1
01
00
1
1
01
01
0
1
10
01
1
1
10
10
0
1
11
10
1
1
11
11
0
0
11
00
1
0
11
00
0
0
11
00
--------------------------------------------------------------------
76
PROGRAM:
2 Bit Register:
// Module Name: Reg2Bit
module Reg2Bit(Clock, Clear, in, out);
input Clock;
input Clear;
input [0:1] in;
output [0:1] out;
reg [0:1] out;
always@(posedge Clock, negedge Clear)
if(~Clear) out=2'b00;
else out=in;
endmodule
module Stimulus_v;
// Inputs
reg Clock;
reg Clear;
reg [0:1] in;
// Outputs
wire [0:1] out;
Reg2Bit uut (
.Clock(Clock),
.Clear(Clear),
.in(in),
.out(out)
);
initial
begin
$display("\t\t\t\t 2 Bit Register");
$display("\t\t------------------------------------------------------");
$display("\t\tClock\t\tClear\t\tInput[2]\t\tOutput[2]");
77
$display("\t\t------------------------------------------------------");
$monitor("\t\t %b\t\t %b \t\t %b \t\t
%b
",Clock,Clear,in,out);
#19
$display("\t\t------------------------------------------------------");
end
always
#1 Clock=~Clock;
initial
begin
Clock=0;Clear=0;
in=2'b00;
#2 in=2'b01;
#2 in=2'b10;
#2 in=2'b11;
#2 Clear=1;
in=2'b00;
#2 in=2'b01;
#2 in=2'b10;
#2 in=2'b11;
#2 Clear=0;
#1; //Gap for display.
#2 $stop;
end
endmodule
EXCERCISE
(i)Design a counter in Verilog coding for given counting sequence.
00000001, 00000010, 000000100,00001000,00010000,00100000,01000000,1000000
(ii) Design a counter in Verilog coding for given counting sequence
0000, 1000, 1100,1110,1111,0111,0011,0001,0000.
(iii)Design a ring counter in verilog coding
(iv)Design a twisted ring counter in verilog coding
RESULT:
78
Expt. No:
Date:
DESIGN OF TRAFFIC LIGHT CONTROLLER
AIM:
To write Verilog HDL program for Traffic Light Controller and verify the output
using Xilinx ISE 10.1 version.To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
79
Logic Diagram:
PROGRAM :
80
Traffic Light Controller:

module traffic_light(clk,reset,p1,p2,p3,p4);
input clk;
input reset;
output[2:0]p1;
output[2:0]p2;
output[2:0]p3;
output[2:0]p4;
reg[2:0]p1;
reg[2:0]p2;
reg[2:0]p3;
reg[2:0]p4;
reg[31:0]sig;
always @(posedge clk or negedge reset)
begin
if(reset==1'b0)
begin
p1<=3'b010;
p2<=3'b000;
p3<=3'b000;
p4<=3'b001;
sig<=8'h0;
end
else
begin
sig<=sig+1;
case(sig[29:24])
6'b000000:
begin
p1<=5'b010;//red
p2<=5'b100;//green
p3<=5'b001;//green
p4<=5'b001;//red
end
6'b000100:
begin
p1<=5'b010;//red
p2<=5'b010;//Amber
81
p3<=5'b100;//Amber
p4<=5'b001;//red
end
6'b001000:
begin
p1<=5'b100;//green
p2<=5'b001;//red
p3<=5'b010;//red
p4<=5'b100;//green
end
6'b001100:
begin
p1<=5'b001;//Amber
p2<=5'b001;//red
p3<=5'b010;//red
p4<=5'b010;//Amber
end
6'b010000:
begin
p1<=5'b010;//Red
p2<=5'b100;//Green
p3<=5'b001;//Green
p4<=5'b001;//red
end
6'b010100:
begin
p1<=5'b010;//red
p2<=5'b010;//amber
p3<=5'b100;//amber
p4<=5'b001;//red
end
6'b011000:
begin
p1<=5'b100;//green
p2<=5'b001;//red
p3<=5'b010;//red
p4<=5'b100;//green
end
6'b011100:
begin
p1<=5'b001;//amber
p2<=5'b001;//red
82
p3<=5'b010;//red
p4<=5'b010;//amber
end
6'b100000:
begin
p1<=5'b010;//red
p2<=5'b100;//green
p3<=5'b001;//green
p4<=5'b001;//red
end
6'b100100:sig<=8'h0;
default:begin
end
endcase
end
end
endmodule
RESULT:
Expt. No:
IMPLEMENTATION OF REAL TIME CLOCK
83
Date:
AIM:
To write Verilog HDL program for Real Time Clock and verify the output using
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
84
Block Diagram:
PROGRAM:
Real Time Clock:
module realtimelock(clk,rst,sl,atoh);
input clk; // System Clock
input rst; // Reset(micro switch)
output[5:0] sl; // Segment Selection
output[7:0] atoh; // Segment Display Control Data
reg[5:0] sl;
reg[7:0] atoh;
reg[26:0] sig2;
reg[19:1] sig3;
reg[7:0] ssdigit1;
reg[7:0] ssdigit2;
reg[7:0] ssdigit3;
reg[7:0] ssdigit4;
reg[7:0] ssdigit5;
reg[7:0] ssdigit6;
85
integer
integer
integer
integer
integer
integer
digit1;
digit2;
digit3;
digit4;
digit5;
digit6;
always @ (posedge clk or negedge rst)

begin
if (rst == 1'b0) begin
sig2 = 0;
sig3 = 0;
digit1 = 0;
digit2 = 0;
digit3 = 0;
digit4 = 0;
digit5 = 0;
digit6 = 0;
end
else begin
sig2 = sig2 + 1;
case (sig2[24:23]) //RTC Function
2'b00 : begin
digit6 = digit6 + 1;
if (digit6 > 9) begin
digit6 = 0;
digit5 =0;
if (digit4 >9 ) begin
digit4 = 0;
digit3 = 0;
if (digit2 >9) begin
digit2 = 0;
digit1 = digit1 + 1; if ((digit1 >= 2) & (digit2 >= 4)) begin digit1 = 0;
digit2 = 0;
end
end
end
end
end
end
sig2[24:23] = 2'b01;
end
2'b11 : begin
if (sig2[22:19] == 4'b1001)
sig2 = 0;
end
default : begin
end
endcase
end
// Display Settings
sig3 = sig3 + 1;
case (sig3[17:15])
86
3'b000 : begin
sl = 6'b111110;
case (digit1)
0 : ssdigit1 = 8'b00111111;
1 : ssdigit1 = 8'b00000110;
2 : ssdigit1 = 8'b01011011;
default : ssdigit1 = 8'b00000000;
endcase
atoh = ssdigit1;
end
3'b001 : begin
sl = 6'b111101;
case (digit2)
0 : ssdigit2 = 8'b00111111;
1 : ssdigit2 = 8'b00000110;
2 : ssdigit2 = 8'b01011011;
3 : ssdigit2 = 8'b01001111;
4 : ssdigit2 = 8'b01100110;
5 : ssdigit2 = 8'b01101101;
6 : ssdigit2 = 8'b01111101;
7 : ssdigit2 = 8'b00000111;
8 : ssdigit2 = 8'b01111111;
9 : ssdigit2 = 8'b01101111;
ndcase
atoh = ssdigit2;
end
3'b011 : begin
sl = 6'b111011;
case (digit3)
0 : ssdigit3 = 8'b00111111;
1 : ssdigit3 = 8'b00000110;
2 : ssdigit3 = 8'b01011011;
3 : ssdigit3 = 8'b01001111;
4 : ssdigit3 = 8'b01100110;
5 : ssdigit3 = 8'b01101101;
endcase
atoh = ssdigit3;
end
3'b100 : begin
sl = 6'b110111;
case (digit4)
0 : ssdigit4 = 8'b00111111;
1 : ssdigit4 = 8'b00000110;
2 : ssdigit4 = 8'b01011011;
3 : ssdigit4 = 8'b01001111;
4 : ssdigit4 = 8'b01100110;
5 : ssdigit4 = 8'b01101101;
6 : ssdigit4 = 8'b01111101;
7 : ssdigit4 = 8'b00000111;
8 : ssdigit4 = 8'b01111111;
9 : ssdigit4 = 8'b01101111;
endcase
atoh = ssdigit4;
end
3'b110 : begin
sl = 6'b101111;
case (digit5)
0 : ssdigit5 = 8'b00111111;
87
1 : ssdigit5 = 8'b00000110;
2 : ssdigit5 = 8'b01011011;
3 : ssdigit5 = 8'b01001111;
4 : ssdigit5 = 8'b01100110;
5 : ssdigit5 = 8'b01101101;
endcase
atoh = ssdigit5;
end
3'b111 : begin
sl = 6'b011111;
case (digit6)
0 : ssdigit6 = 8'b00111111;
1 : ssdigit6 = 8'b00000110;
2 : ssdigit6 = 8'b01011011;
3 : ssdigit6 = 8'b01001111;
4 : ssdigit6 = 8'b01100110;
5 : ssdigit6 = 8'b01101101;
6 : ssdigit6 = 8'b01111101;
7 : ssdigit6 = 8'b00000111;
8 : ssdigit6 = 8'b01111111; 9 : ssdigit6 = 8'b01101111;
endcase
atoh = ssdigit6;
end
endcase
end
end
endmodule
Output:
RESULT:
Expt No:
Date
:
IMPLEMENTATION OF SERIAL ADDER
88
AIM:
To write Verilog HDL program for Serial Adder and verify the output using Xilinx
ISE 10.1 version.To download the bit file in FPGA Kit and verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
89
Serial adder
PROGRAM:
Serial Adder:
90
module
SERIALADDER_TOP( RST,LOAD,A3,A2,A0,A1,A5,A4,A6,A7,B7,B6,B4,B
5,B1,B0,
B2,B3,clk1,S3,S4,S0,Cout,S2,S1,S7,S6,S5,Done);
input RST,LOAD,A3,A2,A0,A1,A5,A4;
input A6,A7,B7,B6,B4,B5,B1,B0;
input B2,B3,clk1;
output S3,S4,S0,Cout,S2,S1,S7,S6;
output S5,Done;
wire w50,w51,w52,w53,w54,w55,w56,w57;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112,w113;
wire w114,w115,w116,w117,w118,w119,w120,w121;
wire w122,w123,w124,w125,w126,w127,w128,w129;
wire w130,w131,w132,w133,w134,w135,w136,w137;
dreg #(12) dreg6(w32,w36,w34,w35,clk1);
mux #(10) mux(w34,w32,LOAD,LOAD);
or #(16) or2(w35,RST,Done);
dreg #(12) dreg7(w38,w39,w37,w31,clk1);
dreg #(12) dreg8(Cout,w49,w38,RST,Done);
or #(86) or21(w31,RST,LOAD);
mux #(12) mux_Sh1(w51,w50,A5,LOAD);
dreg #(6) dreg2_Sh3(w54,w55,w51,RST,clk1);
mux #(12) mux_Sh7(w56,RST,A7,LOAD);
mux #(12) mux_Sh17(w74,w73,B5,LOAD);
91

mux #(12) mux_Sh23(w79,RST,B7,LOAD);
not #(23) inv_Di33(w96,w31);
xor #(15) xor2_Di34(w98,w97,w96);
xor #(15) xor2_Di35(w101,w99,w100);
dreg #(2) dreg137_Di36(w103,w104,w102,w31,clk1);
xor #(15) xor2_Di37(w107,w105,w106);
and #(15) and2_Di38(w106,w103,w108);
mux #(12) mux_Di41(w113,w107,w31,Done);
and #(26) and2_Di42(w100,w97,w96);
dreg #(6) dreg140_Di43(Done,w115,w114,w31,clk1);
and #(26) and2_Di44(w108,w99,w100);
xor #(15) xor2_Di48(w117,w103,w108);
and #(15) and3_Di50(w114,w118,w116,w32);
and #(15) and3_Di51(w118,w110,w99,w103);
dreg #(6) dreg108_Se52(w43,w119,w44,RST,clk1);
xor #(26) xor2_fu60(w127,w14,w23);
and #(15) and2_fu61(w128,w14,w23);
xor #(15) xor2_fu62(w40,w127,w38);
and #(15) and2_fu63(w129,w127,w38);
or #(15) or2_fu64(w37,w129,w128);
dreg #(6) dreg116_SH65(S4,w130,w45,RST,Done);
92

endmodule
// Simulation parameters in Verilog Format
always
#1000 RST=~RST;
#2000 LOAD=~LOAD;
#4000 A3=~A3;
#8000 A2=~A2;
#16000 A0=~A0;
#32000 A1=~A1;
#64000 A5=~A5;
#128000 A4=~A4;
#256000 A6=~A6;
#512000 A7=~A7;
#1024000 B7=~B7;
#2048000 B6=~B6;
#4096000 B4=~B4;
#8192000 B5=~B5;
#16384000 B1=~B1;
#32768000 B0=~B0;
#65536000 B2=~B2;
#131072000 B3=~B3;
#1000 clk1=~clk1;
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Simulation parameters
RST CLK 10 10
LOAD CLK 20 20
A3 CLK 40 40
A2 CLK 80 80
A0 CLK 160 160
A1 CLK 320 320
A5 CLK 640 640
A4 CLK 1280 1280
A6 CLK 2560 2560
A7 CLK 5120 5120
B7 CLK 10240 10240
B6 CLK 20480 20480
B4 CLK 40960 40960
B5 CLK 81920 81920
B1 CLK 163840 163840
B0 CLK 327680 327680
B2 CLK 655360 655360
B3 CLK 1310720 1310720
clk1 CLK 10.00 10.00
93
Output:
RESULT:
Expt No:
Date
:
IMPLEMENTATION OF PARALLEL PIPELINE

ADDER & SUBTRACTOR
94
AIM:
To write Verilog HDL program for Parallel Pipeline Adder and Subtractor and
verify the output.
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
95
BLOCK DIAGRAM:
PROGRAM:
module Adder_Subtractor_Top( B5,addbsub,clk1,RST,A7,A6,A5,A4,
A3,A2,A1,B7,B6,B4,B3,B2,
B1,B0,A0,Q7,COUT,Q0,Q1,Q2,
Q3,Q4,Q5,Q6);
input B5,addbsub,clk1,RST,A7,A6,A5,A4;
input A3,A2,A1,B7,B6,B4,B3,B2;
input B1,B0,A0;
output Q7,COUT,Q0,Q1,Q2,Q3,Q4,Q5;
output Q6;
wire w68,w69,w70,w71,w72,w73,w74,w75;
wire w76,w77,w78,w79,w80,w81,w82,w83;
wire w84,w85,w86,w87,w88,w89,w90,w91;
wire w92,w93,w94,w95,w96,w97,w98,w99;
wire w100,w101,w102,w103,w104,w105,w106,w107;
wire w108,w109,w110,w111,w112,w113,w114,w115;
wire w116,w117,w118,w119,w120,w121,w122,w123;
wire w124,w125,w126,w127,w128,w129,w130;
96
not #(17) inv(w21,RST);

dreg #(12) dreg2(w23,w24,w22,RST,clk1);
not #(10) inv(w66,w23);
mux #(10) mux(COUT,w23,w66,addbsub);
not #(10) inv(w67,w21);
mux #(17) mux(w50,w67,w21,addbsub);
dreg #(3) dreg16_re1(w16,w68,B4,RST,clk1);
mux #(19) mux_mu9(w26,w19,w76,addbsub);
not #(12) inv_mu11(w78,w17);
not #(12) inv_mu13(w80,w15);
not #(12) inv_mu14(w81,w14);
not #(12) inv_mu15(w82,w12);
not #(12) inv_mu16(w83,w13);
not #(12) inv_mu17(w76,w19);
not #(12) inv_mu18(w77,w18);
not #(12) inv_mu20(w79,w16);
dreg #(3) dreg16_re25(Q4,w84,w45,RST,clk1);
or #(17) or2_fa1_pa33(w94,w92,w93);
xor #(17) xor2_fa2_pa34(w95,w30,w50);
and #(10) and2_fa3_pa35(w93,w30,w50);
and #(10) and2_fa4_pa36(w92,w95,w49);
xor #(10) xor2_fa5_pa37(w43,w95,w49);
or #(17) or2_fa6_pa38(w98,w96,w97);
xor #(17) xor2_fa7_pa39(w99,w29,w94);
and #(10) and2_fa8_pa40(w97,w29,w94);
and #(10) and2_fa9_pa41(w96,w99,w51);
97
xor #(10) xor2_fa10_pa42(w44,w99,w51);

or #(17) or2_fa11_pa43(w102,w100,w101);
xor #(17) xor2_fa12_pa44(w103,w28,w98);
and #(10) and2_fa13_pa45(w101,w28,w98);
and #(10) and2_fa14_pa46(w100,w103,w52);
xor #(10) xor2_fa15_pa47(w42,w103,w52);
or #(17) or2_fa16_pa48(w106,w104,w105);
xor #(17) xor2_fa17_pa49(w107,w27,w102);
and #(10) and2_fa18_pa50(w105,w27,w102);
and #(10) and2_fa19_pa51(w104,w107,w53);
xor #(10) xor2_fa20_pa52(w41,w107,w53);
or #(17) or2_fa21_pa53(w110,w108,w109);
xor #(17) xor2_fa22_pa54(w111,w31,w106);
and #(10) and2_fa23_pa55(w109,w31,w106);
and #(10) and2_fa24_pa56(w108,w111,w54);
xor #(10) xor2_fa25_pa57(w45,w111,w54);
or #(17) or2_fa26_pa58(w114,w112,w113);
xor #(17) xor2_fa27_pa59(w115,w32,w110);
and #(10) and2_fa28_pa60(w113,w32,w110);
and #(10) and2_fa29_pa61(w112,w115,w55);
xor #(10) xor2_fa30_pa62(w46,w115,w55);
or #(17) or2_fa31_pa63(w118,w116,w117);
xor #(17) xor2_fa32_pa64(w119,w25,w114);
and #(10) and2_fa33_pa65(w117,w25,w114);
and #(10) and2_fa34_pa66(w116,w119,w57);
xor #(10) xor2_fa35_pa67(w47,w119,w57);
or #(10) or2_fa36_pa68(w22,w120,w121);
xor #(17) xor2_fa37_pa69(w122,w26,w118);
and #(10) and2_fa38_pa70(w121,w26,w118);
and #(10) and2_fa39_pa71(w120,w122,w56);
xor #(10) xor2_fa40_pa72(w48,w122,w56);
dreg #(3) dreg16_re73(w54,w123,A4,RST,clk1);
endmodule
// Simulation parameters in Verilog Format
always
#1000 B5=~B5;
#2000 add/sub=~add/sub;
#500 clk1=~clk1;
#4000 RST=~RST;
#8000 A7=~A7;
98
#16000 A6=~A6;
#32000 A5=~A5;
#64000 A4=~A4;
#128000 A3=~A3;
#256000 A2=~A2;
#512000 A1=~A1;
#1024000 B7=~B7;
#2048000 B6=~B6;
#4096000 B4=~B4;
#8192000 B3=~B3;
#16384000 B2=~B2;
#32768000 B1=~B1;
#65536000 B0=~B0;
#131072000 A0=~A0;
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
Simulation parameters
B5 CLK 10 10
add/sub CLK 20 20
clk1 CLK 5.000 5.000
RST CLK 40 40
A7 CLK 80 80
A6 CLK 160 160
A5 CLK 320 320
A4 CLK 640 640
A3 CLK 1280 1280
A2 CLK 2560 2560
A1 CLK 5120 5120
B7 CLK 10240 10240
B6 CLK 20480 20480
B4 CLK 40960 40960
B3 CLK 81920 81920
B2 CLK 163840 163840
Output:
99
// B1 CLK 327680 327680

// B0 CLK 655360 655360
// A0 CLK 1310720 1310720
RESULT:
100
IMPLEMENTATION OF 8-BIT PARALLEL ADDER WITH

CARRY
AIM:
To write Verilog HDL program for 8bit Parallel Adder and verify the output using
APPARATUS REQUIRED:
3.Xilinx ISE 10.1
PROCEDURE:
Start
Programs
Xilinx ISE (10.1)
NEW PROJECT.
speed as -4.
Click
Click on new source
name and say next.
Process window
Synthesize
Click on new source
Select Entity
Finish.
source window.
click
Click on new source
give the name
Select entity
101
BLOCK DIAGRAM:
102
PROGRAM:
module Adder_Par_Top( Cin,RST,B7,clk1,A7,A6,A5,A4,
A3,A2,A1,A0,B6,B5,B4,B3,
B2,B1,B0,R0,R7,R6,R5,R4,
R3,R2,R1,Cout);
input Cin,RST,B7,clk1,A7,A6,A5,A4;
input A3,A2,A1,A0,B6,B5,B4,B3;
input B2,B1,B0;
output R0,R7,R6,R5,R4,R3,R2,R1;
output Cout;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112;
dreg dreg1(w3,w47,Cin,RST,clk1);
dreg dreg2(Cout,w57,w18,w56,clk1);
or or2_fa1_pa1(w60,w58,w59);
xor xor2_fa2_pa2(w61,w1,w3);
and and2_fa3_pa3(w59,w1,w3);
or or2_fa6_pa6(w64,w62,w63);
or or2_fa11_pa11(w68,w66,w67);
or or2_fa16_pa16(w72,w70,w71);
or or2_fa21_pa21(w76,w74,w75);
or or2_fa26_pa26(w80,w78,w79);
103
or or2_fa31_pa31(w84,w82,w83);
or or2_fa36_pa36(w18,w86,w87);
dreg dreg16_re41(w11,w89,A4,RST,clk1);
dreg dreg16_re49(w10,w97,B4,RST,clk1);
dreg dreg16_re57(R4,w105,w23,RST,clk1);
endmodule
104
Output:
RESULT:
105

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VELAMMAL COLLEGE OF ENGG AND

EC67- VLSI Design Lab

Department of Electronics and

VLSI DESIGN FLOW

ASIC DESIGN FLOW

STUDY OF SIMULATION TOOLS

To Study the Verilog HDL/VHDL simulation tools for digital logic

Fig 2: Waveform Editor - Test Bench

Fig 1:Waveform Editor - Initialize Timing Dialog Box

Fig 3:Waveform Editor - Expected Results

2. Double-click the Generate Expected Simulation Results process.

Fig 4:Simulator Processes for Test Bench

Fig 5:Behavioral Simulation in ISE Simulator

To run the integrated simulation processes in ISE:

Fig 6: Simulator Processes for Test Bench

Fig 7:Behavioral Simulation in ModelSim

2. Double-click the Simulate Behavioral Model process. The ModelSim

Figure: RTL Viewer - Detailed View

STUDY OF SYNTHESIS TOOLS

Figure 1: Floorplanner View - Detailed View

Figure 2: Design Summary View

STUDY OF PLACE AND ROOT AND BACK

Figure 3: Timing Analyzer - Timing Summary

Figure 4: FPGA Editor - Detailed View

2. In the Device Utilization Summary section, observe the number of

Figure 5: Simulator Processes for Test Bench

Figure 6: Timing Simulation in ISE Simulator

7. Verify that the signal goes to the pad as an output.

Figure 7: Simulator Processes for Test Bench

Figure 8: Timing Simulation in ModelSim

2. Double-click the Simulate Post-Place & Route VHDL/Verilog

BASIC LOGIC GATES

// Module Name: Stimulus.v

// Instantiate the Unit Under Test (UUT)

// Module Name: Notgate

HALF ADDER AND FULL ADDER

module HalfAddr(sum, c_out, i1, i2);

HALF SUBTRACTOR & FULL SUBTRACTOR

// Module Name: HalfSub

// Module Name: FullSub

IMPLEMENTATION OF 2 x 4 DECODER AND

// Module Name: Encd2to4

// Module Name: Stimulus.v

i0=0; i1=1; i2=0; i3=0;

// Instantiate the Unit Under Test (UUT)

MULTIPLEXER & DEMULTIPLEXER

To write Verilog HDL program for 4 to 1 Multiplexer and 1 to 4 Demultiplexer and

module Mux4to1(i0, i1, i2, i3, s0, s1, out);

// Module Name: Dux1to4

// Module Name: DFF

// Module Name: JKFF

always@(posedge Clock, negedge Reset)

// Module Name: Stimulus.v

16. Generating programming file

DESIGN OF TRAFFIC LIGHT CONTROLLER

Traffic Light Controller:

IMPLEMENTATION OF REAL TIME CLOCK

always @ (posedge clk or negedge rst)

IMPLEMENTATION OF SERIAL ADDER

mux #(12) mux_Sh21(w81,w77,B4,LOAD);

dreg #(6) dreg120_SH69(S1,w134,w42,RST,Done);

IMPLEMENTATION OF PARALLEL PIPELINE

not #(17) inv(w21,RST);

xor #(10) xor2_fa10_pa42(w44,w99,w51);