Multigate Transistors

Tri-Gate transistors
Manjinder Singh
RE2407A12, EC563- Solid State Devices
Department of Electronics & Communication Engineering
Lovely professional University
Jalandhar, India
er.manjinder.minhas@gmail.com
AbstractThe 3D tri-gate transistors are a
remarkable breakthrough in the realm of
CMOS technology. Tri-Gate fully-depleted
CMOS transistors have been fabricated with
various body dimensions. These experimental
results and 3-D simulations are used to explore
the design space for full depletion, as well as
layout issues for the Tri-Gate architecture, down
to 30nm gate lengths. These transistors can be
considered as a reinvention of the transistor, in a
way that they have supplanted the conventional
flat" 2D planar gate with an incredibly thin 3D
silicon fin that rises up vertically from the
silicon
substrate.
This
next-generation
technology,
which
target
ultra-highperformance systems for military, wire line
communications, cloud networking, and
compute and storage applications, will enable
break through levels of performance and power
efficiencies not otherwise possible. These tri-gate
transistors in concern with other key
semiconductor technologies will enable a new
era of energy-efficient performance. This Paper
discusses the 3-D Tri-Gate transistor technology,
its developments and integration with other
silicon processing technologies.
Index TermsMOSFET,
transistors, FinFET.

CMOS,

3D

Tri-Gate

1. INTRODUCTION
Tri-gate transistor is a MOSFET (metaloxide
semiconductor field effect transistor) which
incorporates three gates into a single device. It is a
type of multiple gate field effect transistors
(MuGFET). The three gates may be controlled by a
single gate electrode, where in the three gate
surfaces act electrically as a single gate, or they can
be operated independently. These transistors
employ a single gate stacked on top of two vertical
gates allowing for essentially three times the
surface area for electrons to travel. For over 50

years, integrated circuits were using planar

transistors as its core, during this period the size of
the individual transistors has steadily decreased.
Today, the transistor gate length in production is
approximately 28 nanometers. But there are several
limitations or drawbacks of these miniaturizations,
most significant are: excessive gate leakage
current, exponentially increasing source to drain
sub-threshold leakage current, gate stack reliability
and channel mobility degradation from increasing
electric field. Compared to today's 65nm
transistors, integrated tri-gate transistors can offer a
45 percent increase in drive current (switching
speed) or 50 times reduction in off-current, and 35
percent reduction in transistor switching power.
At present, Intel Corporation is the only company
to have made this design and manufacturing
transition in 22 nm technology, and can provide
data on the overall maturity and manufacturability
of Tri-Gate transistors on a mass production scale.
2. STRUCTURE OF TRI-GATE TRANSISTOR
The structure of 3D Tri-gate transistor represents a
fundamental departure from the 2D planar
transistor structure .Tri-gate transistors form
conducting channels on three sides of a vertical fin
structure, thus they are fully depleted so that the
entire available silicon underneath the gate
electrode is depleted of carriers before the
threshold condition is reached. Since fins are made
vertical in nature, high packing density can be
achieved, by packing transistors closer together.

Tri gate transistor can be fabricated either on the

SOI substrate or standard bulk-silicon substrate.

It has one gate electrode on the top and other two

gate electrodes on the sides of the silicon body.
This additional gate control enables as much
transistor current flowing as possible when the
transistor is in the 'on' state (for performance), and
as close to zero as possible when it is in the 'off'
state (to minimize power), and enables the
transistor to switch very quickly between the two
states (again, for performance). The key
performance advantage of Tri-Gate transistor
geometries over traditional planar geometries can
be found in the effective width of the conducting
channel. Without any impact on the layout area,
designers have a choice of extending the width in
third dimension in tri gate transistor structure; as a
result the effective channel width can be
significantly enhanced relative to a planar
transistor.
Effective channel length and the effective fin width
of the device are used as the key knob for
controlling the short channel effects in 3D
transistors. Device designers design electrostatically well controlled 3D transistors by keeping
the effective channel length to fin width ratio
greater than 0.5. This also allows them to reduce
the channel doping which, in turn, reduces the
impurity scattering the channel, enhances volume
inversion effect and results in higher performance,
particularly at lower bias region.
3. TRI-GATE FABRICATION
Tri-Gate transistors down to 30nm were fabricated
in the following manner. To get body widths of the
same approx. size as the polysilicon gate, the body
was first fabricated by treating it in a similar manner
to polysilicon, using aggressive poly-silicon
lithography and etches techniques to get body
thicknesses equal to gate lengths. The body was
then doped to obtain acceptable threshold voltages
using conventional boron implants. No halo

implants were used for setting Vt, nor were there

any angled implants used anywhere in the process.
This is in contrast to Double-Gate and this is
possible since the Tri-Gate very much resembles
bulk transistor from the processing point-of-view.
However, to get the right Vts, it was found
necessary to protect the Tri-Gate bodies from boron
out diffusion into the surrounding oxide by an N2O
oxidation before gate definition. The gate stack
included polysilicon gates, and a conventional
physical oxide thickness of 15 Angstroms. Raised
source/drains were used to reduce parasitic
resistances and the transistor was silicide using
nickel.
For improving the efficiency, the tri-gate design is
enhanced by using both high-k gate insulators with
metal gates to improve both on and off currents, and
adding strained silicon for enhanced mobility
(speed), further improving device performance.
Non-planar transistor integrated with other silicon
process technologies can provide 30 percent higher
NMOS drive current and 60 percent higher PMOS
drive current than the optimized, state-of-the-art
65nmnode planar transistors at the same off-state
leakage.
4.Conclusion
3D Tri-Gate technology by Intel is an important
innovation needed to continue Moores Law. TriGate CMOS transistors have been fabricated, as
well as simulated down to Lg=22nm to explore the
fabrication and design space at these dimensions.
Full depletion is achieved with relaxed
body dimensions over other fully-depleted
transistor structures. It is found that the corner of
the body plays an dominant role in the sub
threshold behavior. Furthermore, corner rounding is
found to affect greatly the threshold voltage of the
devices, as well as the sub threshold
characteristics. It is also shown that layout play an
important part in the shape of the Tri-Gate body. It
is concluded that in an optimized Tri-Gate device,
particular attention will have
to be paid to the device body edges. Though 3D
Tri-Gate technology will be a foundation to provide
the highest core performance at the lowest power.
5. References
1) Robert Chau, Suman Datta, , Brian Doyle,
Jack Kavalieros, and Matthew Metz,
High-k/Metal-Gate Stack and
Its
MOSFET Characteristics in IEEE
ELECTRON DEVICE LETTERS, VOL.
25, NO. 6, JUNE 2004.

2) Technical report by Intel, Intel Reinvents

Transistors Using New 3-D Structure.
3) D. Hisamoto, W.C. Lee, J. Kedzierski, H.
Takeuchi, K. Asano, C. Kuo, E. Anderson,
T.J. King, J. Bokor, C.M. Hu, FinFETA self-aligned double-gate MOSFET
scalable to 20 nm,IEEE Trans. Electron.
Devices, vol. TED-47, pp. 2320-2325,
2000.
4) Technical report by ALTERA, Arria 10
Device Overview.
http://www.intel.com/technology/silicon/integr
ated_cmos.html
5) R.Chau et al, IEDM 2000, pp. 45-48.
6) H-S. P. Wong et al, IEDM Technical
Digest, pp. 407 -410, 1998
7) R. Chau et al., SSDM, pp. 68-69, 2002

8) "DESSIS", ISE TCAD Release 7.0 Manual,

Volume 4A, Part 12.
ACKNOWLEDGEMENT
I, Manjinder Singh, student, M.Tech (ECE)
express my deep sense of gratitude and sincere
thanks to my teacher Mr. Sandeep Bansal
(Department
of
Electronics
and
Communication) for his directions, suggestions
and information provided related to my topic
that is Multigate Transistors : Trigate
Transistors which were of utmost
importance for the successful completion of
the term paper. Without his guidance and
support it is not possible to complete this term
paper. I shall be very thankful to my teacher
for his proper guidance.