Tutor Marked Assignment #1 2016

THE OPEN UNIVERSITY OF SRI LANKA

Faculty of Engineering Technology
Department of Electrical and Computer Engineering
Bachelors of Technology Level 06

Course Information and Tutor Marked Assignments (2015/2016)

ECX6151 Digital Electronic Systems
Target Group:
Students who are readying for the Degree in Engineering Technology
Aims and Objectives:
This course provides the background knowledge necessary to design, modelling using HDL,
simulation and implementing the digital systems using FPGA/CPLD devices.
After studying this course, you are expected to achieve the following:
Explain and apply fundamental characteristics of relevant electronic technologies, such
as propagation delay, fan-in, fan-out, and power dissipation and noise margin.
Analyze and design combinational logic and sequential logic networks in a hierarchical,
modular approach, using standard and custom logic functions.
Apply the concepts of basic timing issues, including clocking, timing constraints, and
propagation delays during the design process.
Apply digital system design principles and descriptive techniques.
Analyze and design functional building blocks and control and timing concepts of digital
systems.
Develop a complex digital system design in a hierarchical fashion using top-down and
bottom-up design approaches.
Utilize programmable devices such as FPGAs and PLDs to implement digital system
designs.
Model and simulate a digital system using schematic diagrams.
Model and simulate a digital system using a hardware description language, such as
VHDL.
Discuss the timing issues in digital systems and know how to study these via digital circuit
simulation.
Explain the types and characteristics of the most common faults that occur in digital
circuits.
Discuss the role of computer-aided testing tools, including fault simulation and ATPG.
Prerequisites:
The prerequisite for this course is as listed in the Student Guide Book.
Course Components:
This course does not have a predefined set of lessons as such, and you are expected to search and
find the relevant materials in the library and on the internet. Moodle online class is available for this

Tutor Marked Assignment #1 2016

subject. User ID is your NIC number and password is s-user (If you need an enrolment key please
email your request to the course coordinator)
Three home-based Tutor Marked Assignments (TMAs) will direct such reading. You are required to
prepare three home TMAs. These should be prepared individually although you are encouraged to
form discussion groups and discuss the issues among yourselves whenever possible. Plagiarism (that
is, presenting others work as your own) will not be tolerated, and will be reflected in the grade of
all parties involved. For each assignment, a viva voce examination will be held during laboratory
classes.
There will be two CAT (Continuous Assessment Test). The CAT will be OPEN BOOK type, where you
are allowed to refer any materials during the test.
There are six activities in this course. Three TMAs, one Lab (2 sessions) and two CATs
Eligibility:
All six activities will be considered towards the continuous assessment mark as follows.
CA Final = (LAB)0.4 + 1B(CAT)0.3 + 1B(TMA)0.15 + 2B(TMA)0.15 >= 40
Eligibility = CA Final 40% AND Lab 40%
Final Examination:
There will be a three hour CLOSED BOOK type examination at which you are not allowed any
reference materials.
Day Schools:
There will be three day schools for this course. Please attend the first day school without fail. The
first day school will be held on 24th January 2016 from 0900-1130 hours at the Colombo Regional
Centre.
Laboratory:
At the time of registration, you are supposed to assign yourself to a particular lab group. If you are
not assigned to a group yet, feel free to contact the course coordinator and get a group.
Recommended Readings:

Contacts:
S-mail: -

Digital Design - M. Morris Mano

The Course Coordinator, ECX6151 Digital Electronic Systems,

Department of Electrical and Computer Engineering,
The Open University of Sri Lanka
P.O. Box 21, Nawala, Nugegoda, Sri Lanka.

C. J. Basnayakege:

cjbas@ou.ac.lk

Phone: - Direct: +94 11 288 1437 (or Ext: 437)

Tutor Marked Assignment #1 2016

Submit your written assignment on or before 04th April 2016 and late submissions will not be
accepted!
Clearly show your assumptions if any, when you answering the questions.
[01] Optimize the following Boolean function F.
(a)
(b)
(c)
(d)

F (w, x, y, z) = (2, 6, 10, 11, 14, 15)

Draw the K-map for F and find a optimize expression for F.
Find the optimized sum-of-products (SOP) expression for F.
Find the optimized product-of-sums (POS) expression for F.
Implement the F using 2 to 1 Multiplexers.

[Q2] Consider the following Boolean functions F1, F2, F3 and F4.
F1 (w, x, y, z) = (0, 1, 6),

F2 (w, x, y, z) = (a, b, c, d)

F3 (w, x, y, z) = (2, 6, 10, 11, 14, 15),

F4 (w, x, y, z) = (a, b, c, d)

Where a, b, c, and d, are the last four digits of your registration number.
(a) Draw the K-map for F1, F2, F3, F4 and find optimize expressions for F1, F2, F3, F4.
(b) Draw truth tables for the above expressions.
(c) Draw circuit diagrams to realize the same functions by using following PLDs. (Clearly show the
size of the each PLD)
(i) ROM

(ii) PLA

(iii) PAL

(d) Compare and contrast the each implementations above.

[Q3]
(a) Draw a timing diagram and show how the propagation delay affect to the T-Flip Flop using an
example. (Clearly show the propagation delay, setup time, hold time, clock period of your
example).
(b) Hence derive the equations to show the relations between propagation delay, setup time, hold
time, clock period.
(c) Figure 1 depicts a network which has inputs (X, TA) and output (QA, QA) as below. Where; HIGH
to LOW propagation delay (tPHL) = 100 ns, LOW to HIGH propagation delay (tPLH) = 60 ns, set-up
time (tSU) = 20 ns, hold time (tH) = 0 ns, maximum clock frequency (fCLKMAX) = 14 MHz.
Draw a timing diagram for the network showing X, TA, QA. Assume that X is initially 1 and X
becomes 0 for 10 ns, then X becomes 1 for 200 ns. Clearly state other assumptions if any.

Figure 1

Tutor Marked Assignment #1 2016

[Q4]
(a) Use the Quine-McCluskey method to simplify the function f(w,x,y,z) = (a,2,5,7,13,15). List
all the PIs (prime implicant), EPIs (essential prime implicant), cover lists, and solutions.
(Where a is the first digit of your registration number)
(b) Specify the truth table for a ROM which would realize the simplified function above Q4.(a).
Clearly show the size of the ROM.
(c) Implement the ROM circuit of the truth table above Q4.(b) using digital logic devices.

[Q5]
(a) Draw a truth table drive a Boolean function for 4 to 1 Multiplexer.
(b) Draw a circuit diagram using digital logic gates to perform the function of the 4 to 1
multiplexer.
(c) Write a HDL (VHDL) entity declaration for the 4 to 1 Multiplexer.
(d) Write behavioral program for the 4 to 1 Multiplexer using VHDL.
(e) Show the simulation results (waveforms) of the 4 to 1 Multiplexer using XILINX
software.

[Q6]
(a) Draw a truth table drive a Boolean function for 2 to 4 Decoder.
(b) Draw a circuit diagram using digital logic gates to perform the function of the 2 to 4
Decoder.
(c) Write a HDL (VHDL) entity declaration for the 2 to 4 Decoder.
(d) Write structural program for the 2 to 4 Decoder using VHDL.
(e) Show the simulation results (waveforms) of the 2 to 4 Decoder using XILINX software.

Tutor Marked Assignment #2 2016

Submit your written assignment on or before 10th June 2016 and late submissions will not
be accepted!

Clearly show your assumptions if any, when you answering the questions.

Refer the learning resources (VHDL video lectures) given in the Moodle before answer
the questions.
Use Xilinx web pack software to write VHDL program. (You can get a copy of this
software from the laboratory)

[Q1]
(a) Write structural and behavioral VHDL program for T-Flip-Flop.
(b) Compare and contrast the each modelling methods above (a) with simulation
waveforms.
[Q2]
Analyze the FSM shown in the Figure A2.Q3.F1 where C is an inputs, and a and b are outputs.
(a) Derive Boolean functions for T0, T1, a and, b.
(b) Draw a state transition table for the FSM shown in Figure A2.Q3.F1.
(c) Draw a state diagram for the FSM shown in Figure A2.Q3.F1.

Figure A2.Q3.F1
[Q3]
(a) Draw an ASM chart for the digital circuit shown in Figure A2.Q3.F1 use state diagram
drawn in Q3 (c).
(b) Write a structural VHDL program for the FSM shown in the Figure A2.Q3.F1.
(c) Write test bench for the system and show the simulation results.

Tutor Marked Assignment #2 2016

[Q4]
Design a Finite State Machine (FSM) that counts the decimal sequence 2, 1, 0, 3, 2, 1, 0, 3,...
by using T Flip-Flops and the digital logic gates. The counting starts when the control input
C=1 and continues until C=0 and remains in the same state when C=0. Whenever C=1 then
counter will continue its counting from the state where it has stopped.
(a) Draw an ASM chart for the FSM.
(b) Draw a digital circuit diagram for the FSM
(c) Write structural VHDL program for the FSM

[Q5]
Refer the Quadrature Decoder Circuit diagram shown in the Figure A2.Q5.F1 to answer the
questions given in below.
(a) Derive Boolean functions for the Counter up and the Counter Down outputs.
(b) Draw a waveform to show the inputs and outputs of the circuit.
(c) Write a structural VHDL program using A2.Q1.(a). Clearly show the necessary hardware
changes of the given Quadrature Decoder Circuit.

Figure A2.Q5.F1

Tutor Marked Assignment #3 2016

Submit your written assignment on or before 12th August 2016 and late submissions will
not be accepted!

Clearly show your assumptions if any, when you answering the questions.

Refer the learning resources (VHDL video lectures) given in the Moodle before answer
the questions.
Use Xilinx web pack software to write VHDL program. (You can get a copy of this
software from the laboratory)

Digital Electronic Filter Unit (DEFU)

The following scenario is about a Digital Electronic Filter Unit (DEFU) which is used for filtering
unwanted noise in the optical encoders outputs of a motor due to electromagnetic coupling
and vibration in the operating environment. A pair of DEFUs, one for the channel A and the
other one for the channel B, are required to filter out the noise on the incoming signals. Figure
A3Q1 depicts the architecture of the DEFU.

Channels A/B

3 1 or 3 0
Recognizer

Datapath

Dout

(Control Unit)
Clock
Reset
Figure A3Q1: Digital Electronic Filter Unit
The DEFU consists of a Control unit and a Datapath on each channel of the optical encoder.
The Control unit is a recognizer that checks if the input from the optical encoder (Channel
A/B)) has short duration pulses and then controls the input data to flow through the datapath,
which consists of a 2: 1 multiplexer and a D flip-flop. If the input level has the same value (1
or 0) on at least three (3) consecutive clock cycles, then the input is not considered as a noise.
In this case the output of the recognizer (z) is active high, which then allows the input data
(Channels A/B) to flow through the datapath. The data value, thus becomes the new output
of the DEFU. Otherwise the input is considered as a noise and the datapath output (Dout) of
the DEFU remain the same.

Tutor Marked Assignment #3 2016

Clearly stating your assumptions, if any
[Q1]
(a) Draw a circuit diagram for the Datapath of the DEFU.
(b) Draw a waveform of the DEFU. Clearly show the Channel A/B, z, Dout, and the Clock
signals.
(c) Draw a state diagram for the Recognizer of the DEFU.
(d) Draw an ASM chart for the Recognizer of the DEFU.
(e) Draw a state transition table for the Recognizer of the DEFU.
(f) Draw complete circuit diagram of the DEFU using T Flip-Flops and necessary digital logic
gates.
(g) Write structural VHDL code for the DEFU.
(h) Draw a complete circuit diagram to show how to attach the DEFU to the Quadrature
Decoder Circuit shown in the Figure A2.Q5.F1 after replacing the D filip flop to T flip flop.
(i) Write VHDL program for the complete circuit diagram drawn in A3.Q1.(h) using the
programs written in A2.Q5.(c) and A3.Q1.(g)