FM Demodulation Through Use of a Phase Lock Loop

Sean M. Wilson

April 8th 2015

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Contents
1 Abstract 4

2 Analysis of the System 5

2.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Developing a Model of the System . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Obtaining the Transfer Function of the System . . . . . . . . . . . . . . . 8
2.4 Transfer Function From Input to Output of the Phase Detector . . . . . . 9
2.5 Phase Lock Loop as a Simple Feedback Control System . . . . . . . . . . 10

3 Design of The System 11

3.1 Choosing Values for Kd and p . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Converting Model To Continuous Time . . . . . . . . . . . . . . . . . . . 12
3.3 Verilog Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Results 15

5 Conclusions 17
5.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Concluding Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 Acknoledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

List of Figures
1 Simple Block Diagram of FM Demodulator Circuit with a Phase Lock Loop 4
2 Block Diagram of the System Showing Multiplier Phase Detector . . . . . 5
3 Block Diagram of the System Using the Phase Model . . . . . . . . . . . . 6
4 Block Diagram of the System Using a Phase Model . . . . . . . . . . . . . 7
5 Simple Feedback Diagram of the System . . . . . . . . . . . . . . . . . . . 8
6 Simple Feedback Diagram of the System . . . . . . . . . . . . . . . . . . . 9
7 Typical FM signal showing the modulated signal and the modulating signal 10
8 Frequency response of the system . . . . . . . . . . . . . . . . . . . . . . . 11
9 Pole Zero Map of the System . . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Step Response of the System in Continuous Time . . . . . . . . . . . . . . 13
11 Pole Zero Plot of the System in Continuous Time . . . . . . . . . . . . . . 13
12 Block Diagram of Verilog Implementation of the FM Demodulator . . . . 14
13 SignalTap Showing the Signal m[n] Being Recovered . . . . . . . . . . . . 15
14 SignalTap Showing the Signal m[n] Being Recovered . . . . . . . . . . . . 15
15 SignalTap Showing a DC Signal Being Recovered . . . . . . . . . . . . . . 16
16 SignalTap Showing a Zero Frequency Being Recovered . . . . . . . . . . . 16

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List of Tables
1 Step Response Information . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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1 Abstract
FM signals are commonly used in radio and TV applications. A moderatetly popular
way of implementing a FM demodulator is through the use of phase lock loops, which
can essentially be seen as a simple control system. Phase lock loops work through
detecting the phase difference between two signals through the use of a phase detector.
A phase detector can essentially be seen as a multiplier that outputs the phase difference
of two cosine signals by outputting a very small sine wave. In this report I analyze,
design, implement, and intepret the results of a FM demodulator using a phase lock
loop. The system is built entirely on an Altera DE2 - 115 development board. The
parameters chosen were originally ment to be consistent with TV FM values but had to
be changed in order to properly observe the results on the SignalTap Logic Analyzer.
The implementation of this design was presented to Professor Mehr on Wednesday, April
8th 2015.

Figure 1: Simple Block Diagram of FM Demodulator Circuit with a Phase Lock Loop

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2 Analysis of the System
2.1 Phase Detector
The phase detector block shown in figure 1 can be practically implemented as a simple
multiplier. The inputs to this block are two cosine waves which the block multiplies
together and outputs as a sine wave that contains the differences in the cosine waves
frequencies as well as a double frequency noise component sine wave.
1 1
cos(2 ∗ π ∗ Fc + φ1 ) ∗ cos(2 ∗ π ∗ Fc + φ2 ) = ∗ sin(φ1 − φ2 ) + ∗ sin(2 ∗ π ∗ (2 ∗ Fc ) + φ1 + φ2 )
2 2
It can be seen from this equation that if φ1 −φ2 is very small (specifically less than π4 ) the
first sine term becomes its argument and the phase detector can be modeled as taking
the difference between the two phases. The second sine term is a noise component that
will later be mostly filtered out by the low pass filter.

Figure 2: Block Diagram of the System Showing Multiplier Phase Detector

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2.2 Developing a Model of the System
In order to design this system we first need to find the transfer function from the input
to the output of the system. As shown above the phase detector can be modeled as
taking the difference between two phases. If we use this phase model the ROMs from
the NCO block can be removed and just the integrators going into the ROMs can be
considered as show as seen in Figure 3. In Quartus the mega wizard function for creating
ROMs forces the input of the ROM to be clocked. This must be taken into account if
our model is to work as desired. This delay is shown by the z −1 block directly after the
phase detector.

Figure 3: Block Diagram of the System Using the Phase Model

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 From Figure 3 we see a block diagram for the system from input, X[n], to output Y[n].
From this diagram we can see that there is an integrator on both sides of the difference
being used to model the phase detector. These integrators can be combined and moved
to the output of the phase detector in order to simplify analysis. The resulting block
diagram can be seen in Figure 4.

Figure 4: Block Diagram of the System Using a Phase Model

What we have now is essentially a simple feedback system with blocks G1 (z) and
G(z) and a multiplier Kd of which the transfer function can be obtained with relative
ease. From this diagram it can be clearly seen now that the phase lock loop is nothing
but a simple feedback control system and controls the frequency of the second NCO by
attempting to make the difference between the first and second NCOs zero or very close
to zero.

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2.3 Obtaining the Transfer Function of the System
In Figure 5 we see a simplified feedback diagram from the model developed in the
previous section. A closed loop transfer function can be obtained from this diagram of
the form:
G1 (z) ∗ G(z) ∗ Kd
H(z) =
1 + G1 (z) ∗ G(z) ∗ Kd
In order to complete this transfer function we need to know the transfer functions for
G1 (z) and G(z). The block G1 (z) is a simple integrator with a delay in front of it and
has a transfer function:
z −1
G1 (z) =
1 − z −1
Next, the block G(z) is a single pole low pass filter with transfer function:
1
G(z) =
1 − p ∗ z −1

Simplifying H(z) to include the values of G1 (z) and G(z) we get

z −1 1
Kd ∗ 1−z −1
∗ 1−p∗z −1
H(z) = z −1 1
1+ Kd ∗ 1−z −1 ∗ 1−p∗z −1

Which can further simplified to

Kd ∗ z −1
H(z) =
1 − (1 + p − Kd ) ∗ z −1 + p ∗ z −2

This H(z) is the transfer function from input Fc + m[n[ to output m[n]demodulated of the
FM demodulator.

Figure 5: Simple Feedback Diagram of the System

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2.4 Transfer Function From Input to Output of the Phase Detector
For phase detector model to work properly we need the output of the phase detector to
be smaller than π4 so that our model of sin(φ1 − φ2 ) = φ1 − φ2 is reasonably accurate.
In essence we need to compute the transfer function from X[n] to Y1 [n] in Figure 6.

Figure 6: Simple Feedback Diagram of the System

We need to compute this function so that when we later select values for p and Kd
we are sure that we are operating in the linear region of the phase detector. Before we
compute this transfer function we need to add on to our earlier phase detector model.
In the above model I neglected the π term associated with the output of the phase
detector as its effect on the system was minimal. For this transfer function I want to be
as accurate as possible so I will include it in the function. The first step in finding our
limits for our co efficients is to find Y1 (z), Y1 (z) is calculated as
Kd π ∗ z −1
Y1 (z) = (Y1 (z) ∗ ∗ −1 + X(z)) ∗
1 − p ∗ z −1 1 − z −1
from which we can calculate H1 (z) such that
π ∗ z −1 ∗ (1 − p ∗ z −1 )
H1 (z) =
1 − (1 + p − π ∗ Kd ) ∗ z −1 + p ∗ z −2
If we consider the DC gain to be the max gain of this system we find that
1−p
H1 (ej∗0 ) =
Kd
We need to limit this gain to less than π4 radians or 81 cycles. If we begin to operate to
far outside this region our phase detector will begin to be inaccurate and the phase lock
loop will begin to do a very poor job of controlling the frequency of the system. In order
to achieve this goal we find that
Kd 8
> ∗ Xpeak
1−p π
Where Xpeak Is the maximum amplitude of our message signal, m[n].

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2.5 Phase Lock Loop as a Simple Feedback Control System
Now that we have a model for the system more or less completely developed it becomes
apparent that our FM demodulator system is nothing but a simple negative feedback
digital control system. The phase lock loop detects the difference between the input and
output and the transfer function of this system works to force the output of the system
to be such that the frequency of the second NCO is exactly equal to the frequency of the
first one. Since in our system the carrier frequency is present at the input of both the first
and second NCO this means that the output of the system will be the modulating signal
on the first NCO, m[n]. This implies that the FM demodulator takes in a modulated
cosine waves and outputs the modulating signal, or demodulates the sinusoid entering
it.

Figure 7: Typical FM signal showing the modulated signal and the modulating signal

Figure 7 shows a typical modulating signal and the resulting modulated signal. As
mentioned above the FM demodulator built in this report works by forcing the feedback
of the system to the be modulating signal thus locking the phases of the two NCOs. It is
worth mentioning that due to the nature of the phase lock loop the second NCO will be
locked in quadrature with the first NCO meaning that it will always be π2 out of phase
with it.

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3 Design of The System
3.1 Choosing Values for Kd and p
Before we begin designing the system which is largely a DSP task more than a control
systems task we must select appropriate values for Kd and p in order to give us a
reasonable bandwith and to achieve the condition noted above for proper phase detector
operation. If we rewrite the transfer function in terms of r and θ instead of Kd and p
we get
(1 + r2 − 2 ∗ r ∗ cos(θ)) ∗ z −1
H(z) =
1 − 2 ∗ r ∗ cos(θ) ∗ z −1 + r2 ∗ z −1
We desire our system to not attenuate low frequencies such as the modulating signal
and to attenuate high frequencies such as the carrier frequency and the double carrier
frequency associated with the sinusoidal noise component. We also require minimum
gain in the low pass filter G(z) so that we do not have to discard to many bits when
recovering the signal. In order to achieve these goals
p I set theta to be 0 which causes both
of the poles to appear on the real line and r to be (0.9375) which causes the gain of the
low pass filter to be 16, the max gain of the system to be 1 and the 3dB down points to
be at 165 khz resulting in bandwith of 330 khz. These parameters cause the system to
let through much to many high frequency components but makes implementation easy
so I chose to stick with them rather than finding perfect values. If I choose these values
I get Kd = 0.0010 and p = 0.9375 and the frequency response shown in Figure 8 and the
pole zero plot shown in Figure 9. From these figures we see that the system is stable as
both of the poles of the system are within the unit circle. These values also are within
the linear range of our phase detector which as mentioned earlier is essential for the
phase detector to work.

Figure 8: Frequency response of the system

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 Figure 9: Pole Zero Map of the System

3.2 Converting Model To Continuous Time

Using the d2c function in MATLAB with a sampling time of 25−6 (which is the sampling
time used by the FGPA) we get the resulting continuous time transfer function

−21.05 ∗ s + 1.666 ∗ 106

Hc (s) =
s2 + 2582 ∗ s + 1.666 ∗ 106
using the chosen values of p and Kd . This transfer function has a zero at 79144.89
and two poles at -1317 and -1264.9 which shows that the system is stable but has a
unstable zero. The step response information and step response shows that this system
is very fast and despite the unstable zero has little to no measurable overshoot. These
results, while not directly applicable to the design of the system, show that the model I
developed and the parameters I chose result in a favourable response.

Rise Time: 0.0026 seconds

Settling Time: 0.0045 seconds
Settling Min: 0.9007
Settling Max: 0.9998
Overshoot: 0
Undershoot: 0
Peak: 0.9998
Peak Time: 0.0085 seconds

Table 1: Step Response Information

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Figure 10: Step Response of the System in Continuous Time

Figure 11: Pole Zero Plot of the System in Continuous Time

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3.3 Verilog Implementation
Now that we have a model of the system and have chosen appropriate gain parameters we
can begin to build our design in Verilog. In order to see the results in the SignalTap logic
analyzer properly I chose frequency parameters that would be possible to interpet rather
than my original goal of TV FM frequencies. For the carrier frequency ,Fc , a typical TV
FM value is 4.2 Mhz; This value would be nearly impossible to interpret on signal tap
so I scaled it down to 1 Mhz. A typical value for ∆f (Which is the range of deviation
from the carrier frequency) is 25 khz which I kept as is in the hope that it would let
me clearly see the carrier frequency being modulated. Finally for the modulating signal
m[n] I chose to just have a simple sinusoid at 5 khz as it would be simple to see it being
recovered and required less code compared to importing an actual audio signal. Once
all the parameters of the system were chosen I developed a final block diagram of the
implementation which can be seen in Figure 12.

Figure 12: Block Diagram of Verilog Implementation of the FM Demodulator

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 From this block diagram I implemented the system on a Altera DE2 - 115 FPGA,
the verilog code used to create this system can be found attached to the end of this
report along with the MATLAB code used earlier. In order to create the NCOs I used
an accumulator with the frequencies I chose above as inputs placed in front of 14X14
ROMs that contained one cycle of a full scale cosine wave. The phase detector was
just the muiltiplication of the resulting two signals as discussed earlier. From the phase
detector I built a low pass filter the output of which I multiplied by Kd which then
looped around to be added to the input of the accumulator for the second NCO. The
actual demodulated signal is the m[n] demodulated signal that is being added to the
input of the accumulator for the second NCO. The low pass filter at the end which I did
not have time to implement properly would have further smoothed the signal to be a
better recovery of m[n]. Once all the bugs were worked out of my code I loaded it onto
the FPGA and observed the results.

4 Results
Once the system was designed I loaded it onto the FPGA and enabled signal tap so that
I could see what the signals were doing. I created a multiplexer to change the frequency
that the phase lock loop was locking too so that I could confirm it was working. The
multiplexer chose between a simple DC offset frequency, 0 added frequency, and the m[n]
signal generated from the NCO as earlier described. The results from each frequency
can be found below in Figures 13, 14, 15, and 16.

Figure 13: SignalTap Showing the Signal m[n] Being Recovered

Figure 14: SignalTap Showing the Signal m[n] Being Recovered

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 Figure 15: SignalTap Showing a DC Signal Being Recovered

Figure 16: SignalTap Showing a Zero Frequency Being Recovered

It can first be observed that in all cases the signal was successfully recovered. In the
case of m[n] it is slightly harder to see but the frequency of the signal m[n] demodulated
perfectly matched the frequency of m[n] with some phase offset caused by the phase
response of the filter. In the case of the DC signal it is clearly recovered as is the case
with the zero frequency. In all of the recovered signals there is a good deal of noise
present. This noise is the double frequency component from the phase detector that was
not fully attenuated by the low pass filter due to the selection of Kd and p. If another
low pass filter was put on the output of the system I could smooth the recovered signal
out considerably to look more like the originals. Another thing to note is that NCO 1
and NCO 2 are both perfectly locked in quadrature with each other as can be clearly
seen in Figure 13 and Figure 14. The fact that these two signals are locked in quadrature
with each other implies that the FM demodulator was indeed successful and is working
as expected. The output of the phase detector is sinusoidal at double the frequency of
the carrier signal which is once again caused by the double frequency noise component
of its output not being properly attenuated. For the purposes of this report these results
are acceptable as they demonstrate that the phase lock loop is working properly as a
control system and the system is properly recovering input frequencies.

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5 Conclusions
5.1 Future Work
As can be seen in the results section of the report the design was successful but there
was a good deal of room for improvement. Below is a short list of work that could be
done to improve the performance.
• If less noise was required Kd and p could be chosen such that the passband of the
system was narrow and flatter
• The signal m[n] demodulated could be put through further filtering in order to
better recover the input signals
• The system could be modified to demodulate more complicated signals than the
simple 5 khz sinusoid I used to demonstrate its functionallity.
• Other ways of FM demodulation could be examined as a phase lock loop is not
the only nor the more practicaly method.
• The low pass filter could be reworked to recover the carrier frequency as well so
that it did not have to be added to the second NCO. This is because it its not
always feasible to be able to perfectly add the carrier frequency onto your recovered
signal

5.2 Concluding Statements

In this report I analyzed, designed, implemented, and interpreted the results of a phase
lock loop based FM demodulator for the 481 end of term project. The report demon-
strates the potential of phase lock loops as a control system and shows a practical use
of said control system. I began by developing a model for the FM demodulator and
then using that model to develop a transfer function from input to output. After the
transfer function was developed I chose parameters for the system and converted it to
continuous time to show that it had a desirable step response and was stable. After the
perameters were chosen I developed a block diagram of the verilog code that would be
used to build the FM demodulator. The FM demodulator was built using an Altera
DE2 - 115 FPGA and the results were desplayed using the SignalTap Logic Analyzer.
The design was successful but future work could be done to further improve the results.
In conclusion phase lock loops are a clear example of a simple control system and can
be easily implemented to practical applications such as FM demodulation.

5.3 Acknoledgements
I would like to thank the Electrical Engineering Department of the College of Engineering
in Saskatoon for providing the FPGA used to implement the FM demodulator. I would
also like to specially thank Professor Salt for his help in obtaining the transfer function
of the system and the DSP side of implementing the system.

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