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CS222:
Processor Design: MultiCycle
ProcessorDesign:Multi
Cycle
Design
Dr.A.Sahu
Dept of Comp. Sc. & Engg.
DeptofComp.Sc.&Engg.
IndianInstituteofTechnologyGuwahati
1
Outline
MidSemesterExam
MultiCycledesign
Clockperiodsinsinglecycleandmulti
Clock periods in single cycle and multi
cycledesigns
Improvingresourceutilization
Mergingmemory,Removingadders
Addregistersandmultiplexers
ControldesignforMulticycleCPU
C t l d i f M lti
l CPU
2
Courses:ALP,ALUDesign,SC/MCprocessordesign
OnePagedatasheetwillbeprovided,whichwill
g
p
,
contains
MIPSInstructionset,DataPath Both
SingleCycle/MultiCycle,Arithmetic'sunitdesign
3
tI
tR
tA
tR
lw
tI
tR
tA
tM
sw
tI
tR
tA
tM
tI
tR
tA
t+
t+
tI
t+
beq
t+
tI
clock
period
tR
tI
tR
tA
tR
lw
tI
tR
tA
tM
sw
tI
tR
tA
tM
tI
tR
tA
t+
t+
tI
t+
beq
t+
tI
clock
period
tR
s2
ins[250]
ja[310]
0
0
PC+4[3128]
ad
ins
IM
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
sx
ins[25
2521
21]
ins[2016]
0
1
+
ALU
s2
PC
rd
ad
DM
wd
1
0
Merge IM and DM
MergeIMandDM
28
s2
ins[250]
ja[310]
0
0
PC+4[3128]
rd
ins
Mem
IM
wd
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
sx
adad
ins[25
2521
21]
ins[2016]
0
1
+
ALU
s2
PC
rd
ad
DM
wd
1
0
Rearrange diagram
Rearrangediagram
28
s2
ins[250]
ja[310]
0
1
PC+4[3128]
rd
Mem
wd
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
sx
ad
ins[25
2521
21]
ins[2016]
0
1
+
ALU
s2
PC
ja[310]
0
0
PC+4[3128]
rd
Mem
wd
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
s2
+
ad
ins[25
2521
21]
ins[2016]
sx
PC
ALU
s2
ins[250]
ja[310]
0
0
PC+4[3128]
rd
Mem
wd
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
+
0
s2
ad
ins[25
2521
21]
ins[2016]
sx
PC
s2
ALU
s2
ins[250]
Rearrange diagram
Rearrangediagram
28
ja[310]
0
0
rd
Mem
wd
ins[1511]
rad1
rd1
rad2
wad rd2
wd RF
16
ins[150]
s2
ad
ins[25
2521
21]
ins[2016]
sx
PC
PC+4[3128]
ALU
s2
ins[250]
Introduce registers
Introduceregisters
28
ja[310]
0
0
rd
Mem
wd
ins[25
2521
21]
ins[2016]
0
ins[1511]
DR ins[150]
rad1
rd1
rad2
wad rd2
wd RF
16
A
B
s2
ad
IR
sx
PC
PC+4[3128]
ALU
s2
ins[250]
RES
ja[310]
0
0
rd
Mem
wd
ins[1511]
DR ins[150]
rad1
rd1
rad2
wad rd2
wd RF
16
s2
ad
ins[25
2521
21]
IR
ins[2016]
sx
PC
PC+4[3128]
ALU
s2
ins[250]
RES
s2
ins[250]
ja[310]
Mem
wd
ins[1511]
DR ins[150]
16
1
0
ALU
rd
rad1
rd1
rad2
wad rd2
wd RF
s2
ad
ins[25
2521
21]
IR
ins[2016]
sx
PC
PC+4[3128]
RES
ins[250]
s2
wd
ins[1511]
DR ins[150]
rd1
RF
rd2
16
4
4
0
0
1
2
3
ALU
Mem
rad1
rad2
wad
wd
s2
rd
ad
ins[25
2521
21]
IR
ins[2016]
sx
PC
PC+4[3128]
RES
s2
ins[250]
ja[310]
Mem
wd
ins[1511]
DR ins[150]
16
0
1
1
2
3
ALU
rd
rad1
rd1
rad2
wad rd2
wd RF
s2
ad
ins[25
2521
21]
IR
ins[2016]
sx
PC
PC+4[3128]
RES
s2
ins[250]
ja[310]
PC+4[3128]
Mem
wd
ins[1511]
DR ins[150]
16
0
1
1
2
3
ALU
rd
s2
ad
rad1
rd1
rad2
wad rd2
wd RF
sx
PC
ins[25
2521
21]
IR
ins[2016]
RES
Rearrange diagram
Rearrangediagram
s2
ins[250]
28
ja[310]
ins[250]
s2
PC+4[3128]
28
ja[310]
PC[3128]
Mem
Mem
wd
wd
00
ins
ins[[1511
1511]]
11
DR
DR ins
ins[[150
150]]
rd
rd11
RF
RF
rd
rd22
11
22
BB
11
11
00
44
11
22
16
16
00
00
33
ALU
rd
rd
AA
s2
11
ad
ad
rad
rad11
rad
rad22
wad
wad
wd
d
wd
sx
PC
00
ins
ins[[2521
2521
25
21]]
IR
IR
ins
ins[[2016
2016]]
00
RES
RES
ins[250]
s2
Final: MultiCycle
Final:Multi
CycleDataPath
Data Path
28
ja[310]
PC[3128]
wd
ins[1511]
DR ins[150]
RF
rd2
1
2
16
1
ALU
Mem
rd1
s2
rd
ad
rad1
rad2
wad
wd
sx
PC
ins[2521]
IR
ins[2016]
Res
22
Multicycle
Multi
cycledatapath
data path
Single
Singlecycleapproachtomulti
cycle approach to multicycle
cycleapproach:
approach:
improveperformanceandresourcesharing
Delaysindifferentcyclesshouldbebalanced
Delays in different cycles should be balanced
SingleALUandsinglememoryused
Additionalregistersandmultiplexersrequired
24
Multicycle
Multi
cycleControlDesign
Control Design
Breakinstructionsintocycles
Break
instructions into cycles
Putcyclesequencestogether
C
Controlsignalgroupsandmicrooperations
l i l
d i
i
Controlstatesandsignalvalues
Controlstatetransitions
ins[250]
s2
MultiCycle
Multi
CycleDataPath
Data Path
28
ja[310]
PC[3128]
wd
ins[1511]
DR ins[150]
RF
rd2
1
2
16
1
ALU
Mem
rd1
s2
rd
ad
rad1
rad2
wad
wd
sx
PC
ins[2521]
IR
ins[2016]
Res
26
BreakInstructionExecution
i
intoCycles:Rclassinstructions
l
l
i
i
cycle1
IR=Mem[PC]
PC=PC+4
cycle2
A=RF[IR[2521]]
B=RF[IR[2016]]
RF[IR[ 0 6]]
cycle3
Res=AopB
cycle4
RF[IR[1511]]=Res
opdepends
upon IR[50]
uponIR[50]
BreakInstructionExecution
i
intoCycles:sw
l
i
instruction
i
cycle1
IR=Mem[PC]
PC=PC+4
cycle2
A=RF[IR[2521]]
B=RF[IR[2016]]
RF[IR[ 0 6]]
cycle3
Res=A+sx(IR[150])
cycle4
Mem[Res]=B
BreakInstructionExecution
i
intoCycles:lw
l l instruction
i
i
cycle1
IR=Mem[PC]
PC=PC+4
cycle2
A=RF[IR[2521]]
cycle3
Res=A+sx(IR[150])
cycle4
DR=Mem[Res]
cycle5
l 5
RF[IR[2016]]=DR
BreakInstructionExecution
i
intoCycles:beq
l b instruction
i
i
cycle1
IR=Mem[PC]
PC=PC+4
cycle 2
cycle2
A=RF[IR[2521]]
B=RF[IR[2016]]
RF[IR[ 0 6]]
Res=PC+s2(sx(IR[1511]))
cycle3
if(A==B)PC=Res
BreakInstructionExecution
i
intoCycles:jinstruction
l ji
i
cycle1
IR=Mem[PC]
PC=PC+4
cycle2
PC=PC[3128]|| s2(IR[250])
Whyhavewedivided
executionofthisinstruction
i t t
intotwocycles?
l ?
Recall....Delayfor{j}
y
{ j}
28
s2
ins[250]
ja[310]
PC+4[3128]
PC
ad
ins
IM
t +
max
tI
tI
tR
tA
tR
lw
tI
tR
tA
tM
sw
tI
tR
tA
tM
tI
tR
tA
t+
t+
tI
t+
beq
t+
tI
clock
period
tR
sw
beq
IR=Mem[]
PC=..+..
IR=Mem[]
PC=..+..
IR=Mem[]
PC=..+..
IR=Mem[]
PC=..+..
IR=Mem[]
PC=..+..
A=RF[..]
B=RF[..]
A=RF[..]
B=RF[..]
A=RF[..]
A=RF[..]
B=RF[..]
Res=..+..
PC=..
Res=..op..
Res=..+..
Res=..+..
if(..==..)
PC=..
RF[..]=..
Mem[]=..
DR=Mem[]
lw
RF[..]=DR
thesecanbemerged
Rclass
sw
beq
A=RF[..]
B=RF[..]
A=RF[..]
B=RF[..]
A=RF[..]
A=RF[..]
B=RF[..]
Res=..+..
PC=..
Res=..op..
Res=..+..
Res=..+..
if(..==..)
PC=..
RF[..]=..
Mem[]=..
DR=Mem[]
lw
RF[..]=DR
Opcode isavailableonly
secondcycleonwards.
Splitfrom3rdd cycleonwards
afterdecodingopcode.
Rclass
sw
lw
Res=..op..
Res=..+..
Res=..+..
RF[..]=..
Mem[]=..
DR=Mem[]
RF[ ] DR
RF[..]=DR
beq
if(..==..)
PC=..
j
PC=..
lw, sw cansplitafterthirdcycle
lw,sw
can split after third cycle
IR=Mem[]
PC=..+..
A=RF[..]
[ ]
B=RF[..]
Res=..+..
Rclass
Res=..op..
RF[..]=..
sw/lw
sw
beq
Res=..+..
Mem[]=..
lw
DR=Mem[]
RF[ ] DR
RF[..]=DR
if(..==..)
PC=..
j
PC=..
ins[250]
PC
0
1
rd
ad
Mem
wd
IW
AW
ins[2521]
IR
ins[2016]
0
ins[1511]
Rdst
DR ins[150]
rad1
rad2
wad
wd
rd1
RF
rd2
M2R
PC[3128]
BW
16
1
DW
Asrc1
sx
IorD
RW
ja[310]
28
ALU
MR MW
1
2
s2
PW
s2
Asrc2
op
R W
ReW
1
0
Res Psrc
Microoperationsand
controlsignals
l i
l PCgroup
Microoperation
PWuPWcPsrc
PC PC 4
PC=PC+4
1
1X1
X 1
PCinc
i
if(A==B)PC=Res
branch 010
PC=PC[3128]|| s2(IR[250]) jump 1X2
default
00X
nop
PW=PWu +Z.PWc
Microoperationsand
controlsignals
l i
l Mem group
Microoperation
IR=Mem[PC]
MWMRIorD IWDW
fetch
01010
DR=Mem[Res] m_rd
01101
Mem[Res] =B
Mem[Res]
B
m wr
m_wr
1 0 1 0 0
10100
default
nop
00X00
Microoperationsand
controlsignals
l i
l RFgroup
Microoperation
i
i
A=RF[IR[2521]]
[ [
]]
RWRdst
d M2RAWBW
rs2A
0XX10
rt2B
0XX01
RF[IR[1511]]=Res
res2rd
11000
RF[IR[2016]]=DR
mem2rt
10100
default
nop
0XX00
B=RF[IR[2016]]
Microoperationsand
controlsignals
l i
l ALUgroup
Microoperation
opc Asrc1Asrc2ReW
PC=PC+4
PCinc
0010
Res=AopB
arith
2101
M dd
Maddr
0 1
0121
2
1
Res=PC+s2(sx(IR[1511]))
Paddr 0031
if(A==B)PC=Res
branch
1100
default
nop
X X
XXX0
X
0
cs0 PCinc
cs1
Rclass
cs2 arith
sw/lw
cs4
sw
res2rd
cs3
rs2A
rt2B
Paddr
m_wr
cs5
Maddr
beq
lw
cs6 m_rd
2t
cs7
7 mem2rt
cs8 branch
j
jump
cs9
PCincfetchnopPCinc
nopnoprs2A,rt2BPaddr
nopnopnoparith
ith
nopnopres2rdnop
nop
nopnopnopMaddr
nop
nop
Maddr
nopm_wrnopnop
nop
nopm_rdnopnop
m rd
nop
nop
nopnopmem2rtnop
branch
branchnopnopbranch
nop
nop
branch
jumpnopnopnop
sw
lw
beq
cs1cs1cs1cs1cs1
cs2cs4cs4cs8cs9
cs3XXXX
cs0XXXX
Xcs5cs6XX
Xcs0XXX
XXcs7XX
XXcs0XX
X
XXXcs0X
X
X
cs0
X
XXXXcs0
Summary
Instructions
Instructionsexpressedassequencesofmicro
expressed as sequences of micro
operations
Controlsignalaregrouped
Control signal are grouped
Microoperationsdefinevaluesofcontrol
signals of a group
signalsofagroup
Controlstatesassociatedwithmicro
operations
Controlstatetransitionsdependuponopcode
47