tsmc

Taiwan Semiconductor Manufacturing Co., LTD

SECURITY

TSMC-SECRET

Ver.
1

Eff_Date
06-29-05

ECN No.
E070200524020

Author
Bennett Hsu

Change Description

08-09-06

E070200631005

J. J. Wu

Modify document title to specify the test flow

for 1K ENDR

01-11-08

E070200801008

J. J. Wu

Change the document title to distinguish

L+11& L+8

4.

03-11-08

E030200810011

T. H. Wang

Add
(1)note9:To avoid Bin34/35 test-overkill
(2)note10:Recommend FT to check G.D.R.

03-27-08

E030200812001

J. C. LeeH

Add
(1)Bin5 as option.
(2)Note 11:Inform IP designer, if apply bin5

07-16-08

E030200828005

J. C. LeeH

Add
(1)Note 12:Include IFR in Flash testing for
specific application.

12-23-08

E070200852001

H. P. Yangc

(1) Modify title from TSMC 0.18UM PURE

1.8V EMBFLASH WAFER LEVEL CP
TEST FLOW FOR 1K ENDR (L+11) to
TSMC 0.18UM 1.8V EMBFLASH WAFER
LEVEL TEST FLOW FOR 1K ENDR
(Non-BLB, L+11, HE CELL)
(2) Create NOTE for L+11 vs L+8, test Mode
Gude DC No, test methodology DC No,
and Test Vehicle information.

Original

Revising Line Manager : L. T. Ho

Approvals :
Please refer EDW workflow to see detail approval
records.

Title

TSMC 0.18UM 1.8V EMBFLASH

WAFER LEVEL TEST FLOW FOR 1K
ENDR (NON-BLB, L+11, HE CELL)
Document No. : S-TFL-02-02-039
Contents
Attach.
Total

:6
:0
:6

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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TSMC Confidential Information E220081200367001 Joe C. Mackey/SILAB 2009/1/13

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Reviser : H. P. Yangc (NVMD)

tsmc

Confidential Do Not Copy

Document No. : S-TFL-02-02-039

Version
:7

NOTE
1. This document is for L+11 1K BLB EmbFlash. The major difference with L+8 1K BLB EmbFlash (Doc. No.:
S-TFL-02-02-097) is that L+11 1K BLB EmbFlash needs not to do reference cell erase at the beginning of CP
test.
2. Please refer to the two documents below for testing program development:
Test mode guide DC No.: D-018-FH-02-001
Test methodology DC No.: S-TFL-02-03-068

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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3. ( For tsmc internal use only): Qual vehicle - TMC875 512kx16 EmbFlash.
Sort program: (CP1) C875_512k16_s1.rar
(CP2) C875_512k16_s2.rar

tsmc

Confidential Do Not Copy

Document No. : S-TFL-02-02-039

Version
:7

TSMC 0.18UM 1.8V EMBFLASH WAFER LEVEL TEST FLOW FOR 1K ENDR (NON-BLB, L+11, HE CELL)

(for 1.8V 512k*16 FlashIP sort 1 @25C, last update: Aug.02,2006) 02,2004)
Created By H.Hsuo
Purpose

Test Order

Bin Out#

Test Condition

Failure Criteria

Start
Bin 6
Bin 7

Fail

Open
Short

Check continuity

Force -100uA and measure voltage

Check standby current

1. Force Vcc=2.0V, all input=0 except TMR=2.0V

2. Set CE, OE and TMR high
3. Measure standby current

Open if voltage < -1V

Short if voltage > -0.2V

Pass
Fail

Isb
(<= 80uA)
Pass

Fail if current > 80 uA

1.Set TM register (code=0x2b)

REF CELL ERASE

Bin 5 Fail

Verify Iref>60uA
Pass

Partial Logic Test

for critical test patterns
Pass
DC Stress

Optional

2.Ref Cell Erase Time=20ms

Note 11.

3.Set TM register (code=0xb)

Fail if any current > 60 uA

4.Measure even/odd Ref Cell, force TM[0] 1V and measure current

Optional

Customer specifies the test conditions

Weed out weak

interpoly dielectric

1. Mass Erase with Tme = 1sec

Fail if any bit

Fail if any bad bit

Bin 20
Fail

Mass Program
Pass

Bin 23

Fail

Mass Erase with IFR

Verify "FF"
Pass

Bin 13/36
Fail

Program First 6 Rows

Verify "00"
Pass
Mass Program

Bin 17
Fail

Mass Erase
Verify MRG1

Set background as
"0000"

1. Set TM register (code=0x1d)

*3
2. Mass program @Vpp=11.5V, Tmprog=4ms,Vccnom
3. Read "00" @Vccnom

Check erase issue

1. IFREN=1, mass erase @Vccmin, Tme=Tpe

2. Verify 0xffff @Vccmin/Vccmax, include information page

Catch bit line failure

1. Write 0x0000 on first 6 rows and information page@Vccmin

2. Verify 0x0000 @Vccmax (Bin 13), include information page
3. Verify 0x0000 @Vccmin (Bin 36), include information page

Set background as
"0000"

Check erase efficiency

1. Set TM register (code=0x1d)

*3
2. Mass program @Vpp=11.5V, Tmprog=4ms,Vccnom

Fail if any bad bit

Fail if any bad bit

Fail if any bad bit

1. Mass erase @Vccmin, Tme=Tpe

2. Set TM register (code=0x0a)
3. Margin "1" read @Vccnom

Pass
Bin 28

Fail

Write Disturb
Verify MRG1

Check reverse tunneling

disturb
WL=Vss, BL=Vdd

1. Set TM register (code=0x1e)

*4
2. Do stress test @Vpp, Tmprog=(#columns/#IOs)*7*2*(MaxTpg) us
3. Set TM register (code=0x0a)
4. Margin "1" read @Vccnom

Weed out infant mortality

1. Mass erase @Vccnom, Tme=Tpe

2. Set TM register (code=0x1d)
*3
3. Mass program @Vpp=11.5V, Tmprog=4ms, Vccnom
4. Repeat step 1-3 9 times.

Pass

Cycling
10X

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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Bin 9

tsmc
Bin 27

Fail

Confidential Do Not Copy

Weak Erase
Verify MRG1

Document No. : S-TFL-02-02-039

Version
:7

Fail if any bad bit

Check erase at lower

Vpp

1. Mass erase @Vccnom, Tme=16ms

2. Set TM register (code=0x0a)
3. Margin "1" read @Vccnom

Check thin oxdie

1. Do stress test @Vpp=8V, Vcc=1.8V, Terase=200ms

2. Set TM register (code=0x0a)
3. Margin "1" read @Vccnom

Fail if any bad bit

Set background as "FF"

1. Mass erase @Vccnom, Tme=Tpe

2. Write 0x0000 on "full" diagonal @Vccmax
3. Verify 0x0000 @Vccnom

Fail if any bad bit

Check x & y decoders

1. Set TM register (code=0x1d)

*3
2. Mass program @Vpp=11.5V, Tmprog=4ms, Vccnom
3. Page erase entire array, @Vccmin, Tpe=20ms
4. Margin "1" read @Vccnom

Fail if any bad bit

Check page erase

Optional

Pass

Bin 30

Fail

Fail

Pass
Mass Erase
Program Full Diagonal
Verify Diagonal

Bin 16
Fail

Mass Program
Page Erase
Verify MRG1

Pass
Bin 34/35
Fail

Punch-Through
(PT_E & PT_O)

Pass

Bin21
Fail

Program 0xFF
Check Program Disturb
Pass

Bin14
Fail

Mass Erase
Program CKBD
Verify MRG0

Pass
Bin18
Fail

Program CKBD
Verify MRG1

Check punch-through
disturb

Check PGM 0xFF disturb

Fail if any bad bit

1. Set TM register (code=0x1d)
*5
2. Mass program even rows @Vpp=11.5V , Tmprog=6ms, Vccnom
3. Set TM register (code=0x0a)
4. Margin "1" read odd rows @Vccnom (Bin 34)
5. Repeat step 1-4 for odd rows
6. Repeat step 5 for even rows (Bin 35)

Fail if any bad bit

1. Mass erase @ Vccnom, Tme=Tpe
*4
2. MEO_FF with Vpp = 10.5V*, Vcc=1.6V, Tmprog = 2*(MaxTpg) us
3. MRG1 verify @ Vcc norm

Set background as "ffff"

Check program issue
with CKBD pattern

1. Mass erase @Vccnom, Tme=Tpe

*6
2. Byte Prog CKBD pattern (0x0000/0xffff ) for data 0 only @Vccnom,T=Tpg
3. Set TM register (code=0x09)
Fail if any bad bit
4. Margin "0" read @Vccmax (Bin14)

Check disturb issue

1. Byte Prog CKBD pattern (0x0000/0xffff ) for data 0 only @Vccnom, T=3*Tpg
2. Set TM register (code=0x0a)
3. Margin "1" read @Vccmin (Bin18)
Fail if any bad bit

Set background as "ffff"

Check program issue
with CKBD# pattern

1. Mass erase @Vccnom, Tme=Tpe

2. Byte Prog CKBD# pattern (0xffff/0x0000 ) for data 0 only @Vccnom,T=Tpg
3. Set TM register (code=0x09)
4. Margin "0" read @Vccmax (Bin44)
Fail if any bad bit

Pass
Bin44
Fail

Mass Erase
Program CKBD#
Verify MRG0

Pass

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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Bin 26

Tox Stress
Verify MRG1

tsmc

Confidential Do Not Copy

Program CKBD#

Bin48

Document No. : S-TFL-02-02-039

Version
:7

Check disturb issue

1. Byte Prog CKBD# pattern (0xffff/0x0000 ) for data 0 only @Vccnom, T=3*Tpg
2. Set TM register (code=0x0a)
3. Margin "1" read @Vccmin (Bin48)
4 Byte Prog CKBD pattern (0x0000/0xffff) for data 0 only @Vccnom, T=Tpg

Check thin oxide

1. Set TM register (code=0x1e)

2. Do stress test @Vpp=10.5V, Vcc=1.8V, Tmprog=120ms
3. Set TM register (code=0x09)
4. Margin "0" read @Vccnom

Fail
Verify MRG1
Pass
Bin25
Fail

Thin Oxide Leak

Verify MRG0
Pass

Fail

Read Disturb
Verify MRG0

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Bin19

Bin39

Fail

Mass Erase
Verify MRG1
Pass

Bin40

Bin1

Fail

Pass

Good Die Record

write x, y address

Check read disturb

1. Set TM register (code=0x1c)

2. Do stress test @Vpp=4.9V, Tstress=100ms
3. Set TM register (code=0x09)
4. Margin "0" read @Vccnom

Optional

Customer specifies the test conditions

For data retention bake

1. IFREN=1, Mass erase @Vccnom, Tme=Tpe

2. Margin "1" read @Vccmin

Fail if any bad bit

For wafer sort 2

1. IFREN=1, write 0x55aa for x16 to X=0,Y=0 @Vccnom

2. IFREN=1, X=0,Y=0, verify 0x55aa @Vccnom

Fail if any bad bit

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

Fail if any bad bit

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TSMC Confidential Information E220081200367001 Joe C. Mackey/SILAB 2009/1/13

Pass
Partial Logic Test
for critical test patterns
Pass

Fail if any bad bit

tsmc

Confidential Do Not Copy

Document No. : S-TFL-02-02-039

Version
:7

TSMC 0.18um EmbFlash Wafer Level Test Flow

(for 1.8VV 512k*16 sort 2 @25C, last update: Aug.2,2006)
Created By H.Hsuo
Purpose

Test Order

Bin Out#

Test Condition

Failure Criteria

High Temp. Bake

(@250C for 72 hrs)
Start
Fail

Open
Short

Bin 37

Fail

Check Good Die

Record
Pass

Bin 31

Verify MRG1
Fail
Pass
Verify MRG1

Bin 38
Fail

Pass

Partial Logic Test

for critical test patterns
Pass
Bin 39

Fail

Mass Erase
Verify MRG1
Pass

Bin 40

Bin 1

Good Die Record

Fail

Pass

Check continuity

Force -100uA and measure voltage

Short if voltage > -0.2V

Open if voltage < -1V

Look for good die at

sort-1

1. IFREN=1, X=0,Y=0, verify 0x55aa @Vccnom

Fail if any bad bit

Check data retention

1.Set TM register (code=0x0a)

2. Margin "1" read @Vccnom

Fail if any bad bit

Check RPO_contact

1. Byte program 0x0000 248 cols/IO, Tpg

2. Margin "1" read @Vccnom for 8 cols/IO

Fail if any bad bit

Optional

Customer specifies the test conditions

For future use

(such as FT)

1. Mass erase @Vccnom, Tme=Tpe

2. Margin "1" read @Vccnom

Fail if any bad bit

1. IFREN=1, write 0x55aa for x16 to X=0,Y=1 @Vccnom

2. IFREN=1, X=0,Y=1, verify 0x55aa @Vccnom

Fail if any bad bit

Note: 1. Vccnom=1.8V, Vccmin=1.6V and Vccmax=2.0V. Vcc=Vccnom if not specified in the test condition.
2. The waveforms for user mode and test mode should follow FlashIP Specification and Test Mode Guide respectively.
3.The Mass Program voltage/time=11.5V/4ms is for 8M/16IO IP. For different memory size and IO, need characterization to set the voltage and
time which can fully set background as 00.
4. The MaxTpg need refer to Datasheet. For example, in 8M IP, the MaxTpg=40us
5. Due to weak mass program efficiency, the Tmprog and Vpp must be characterized. For example, in 8M IP, Tmprog=560us with Vpp=10.5v is
replaced by Tmprog=6ms with Vpp=11.5v for Bin34/Bin35(PT).
6. Tpg need refer to Datasheep. For example, in 8M IP, the Tpg=20us.
7. Use byte program for sort2/Bin38(RPO) test to prevent PGMFF disturb failure.
8. Customer's logic test can be inserted in "Partical Logic Test".
9. To avoid test overkill, CP1 Bin34/35(punch through disturb), test condition should be re-characterized between mass/word program stress on
customized IP.Current test condition(11.5V, 6ms) is based on TSMC IP Vehicle(8M bits, 2048 WLs).For small flash IP(small WL#, BL#), suggest to
use word program(40~ 80us) for bin34/35 test to avoid overkill.
10. Recommend FT to check good die record of CP1 & CP2 to double screen CP test bad dice.
11. This option should depend on IP catagory, please contact with TSMC IP designer if need to test this item.
12. If IFR will be used in application, all flash testing items shall include IFR

The information contained herein is the exclusive property of TSMC and shall not be distributed, copied, reproduced, or disclosed in
whole or in part without prior written permission of TSMC.

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Bin 6
Bin 7