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1. D.A.Pucknell, K.Eshraghian, Basic VLSI Design, 3rd Edition, Prentice Hall of India, New
Delhi, 2003.
2. Rabey, J.M., Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1955.
3. Bhasker, J., VHDL Primer, Prentice Hall 1995.
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1.2.
1.3.
Draw the symbols for P-channel and N-channel DE-MOSFET and E-only
MOSFET.
1.4.
1.5.
1.6.
Draw the model transfer characteristics for DE-MOS and E-only MOSFET
1.7.
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1.1.
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1.9.
What are the different regions of operation for MOS transistors and the
conditions foreach?
Cutoff or threshold region; Ids = 0; Vgs< Vt ;
Non-saturation or linear region; Ids
-Vt)Vds-Vds2/2)] ; 0<Vds<Vgs-Vt
2
Saturation region; Ids
-Vt) /2)] ; 0< Vgs-Vt<Vds
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1.16. Draw the VTC for CMOS inverter and mark the different regions of operation.
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1.22. What is the advantage of CMOS over PMOS and NMOS technology? (Nov/Dec
2011)
reduce the complexity of the circuit
low static power consumption
high noise immunity
high density of logic function on a chip
1.23. Write the reasons for the limited load driving capabilities of MOS transistors.
(Nov/Dec 2011)
The MOS technology lies in the limited load driving capabilities of MOS
transistors. This is due to the limited current sourcing and current sinking abilities
associated with both p- and n- transistors. Bipolar transistors provide higher gain and
have generally better noise and high frequency characteristics than MOS transistors
and have effective way of speeding up VLSI circuits.
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2.2.
2.3.
2.4.
What are the four basic layers on which MOS circuits are formed?
1. n diffusion,
2. p diffusion,
3. polysilicon,
4. metal
Define stick diagram? Show the monochrome stick encoding for implant and
polysilicon.
Stick diagrams are used to convey layer information through the use of a colour code or
monochrome shading.
Implant
Polysilicon
2.7.
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2.6.
2.5.
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2.9.
2.10. What are the disadvantages of CMOS transmission gates? Draw the symbol for
transmission gate.
Disadvantages of CMOS transmission gate are
1. Require more area than NMOS pass circuits
2. Require complemented control signals
3. T.G symbol
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I0
I1
I2
I3
2.14. What are the different fatal errors possible in layout design and illustrate them
pictorially. ?
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2.17. How latch up problems can be rectified in CMOS fabrication process? (Nov 04)
CMOS/bulk devices have parasitic bipolar transistors can cause latch up,a
condition in which high currents exist between VDD & Gnd.One method of
preventing Latch up consists of decreasing the current gains of the parasitic
transistors. If the product of the two current gains of both transistors is less than
unity, f/b is not self sustaining & the device cannot latch. The current gain of the
vertical pnp tr is determined by the process design & can be reduced by using buried
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2.21. Why BiCMOS technology does not offer speed advantage in applications like
ALU and ROM subsystems? (Nov/Dec 2011)
Main disadvantage : greater process complexity compared to CMOSResults in a
1.25 -> 1.4 times increase in die costs over conventional CMOS.Taking into account
packaging costs, the total manufacturing costs of supplying a BiCMOS chip ranges
from 1.1-> 1.3 times that of CMOS.
2.22. Define body effect. (Nov/Dec 2012)
The threshold voltage Vt is not constant with respect to the voltage difference
between the substrate and the source of the MOS transistor. This is known as the
substrate-bias effect or body effect
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2.23. What are the three approaches used in making contacts between polysilicon and
diffusion in nMOS circuits. (Nov/Dec 2012)
1. Polysilicon to metal then metal to diffusion
2. Buried contact polysilicon to diffusion
3. Butting contact (polysilicon to diffusion using metal)
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2.25. Draw the circuit schematic of a non-inverting type nMOS type buffer. (Nov/Dec
2012)
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3.2.
3.4.
3.5.
3.6.
3.7.
3.8.
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3.3.
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3.17. Draw the circuit of a two phase clock generator using D-FF.
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3.21. What are the advantages of AOI implementation of two level logic functions?
(Nov/Dec 2011)
Construction of AOI cells is particularly efficient using CMOS technology where
the total number of transistor gates can be reduced compared to the same construction
using NAND logic or NOR logic.
3.22. Name the two phases of operation in a dynamic CMOS logic.(Nov/Dec 2012)
1. Precharge and
2. Evaluate
3.23. What is two phase clocking? (Nov/Dec 2012)
Inverting a single clock can lead to skew problems. Employ two non-overlapping
clocks for master and slave sections of a flip-flop. Thus we can have between one and
four clock lines to route around the chip
3.24. What are the two phases of operation of a dynamic CMOS logic? (Nov/Dec 2012)
Refer Q.No.23
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3.25. Draw the circuit schematic of a two input CMOS NAND gate. (Nov/Dec 2012)
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4.2.
4.3.
4.4.
4.5.
What is a LUT?
Look up Table is a memory organization through which a cells combinational
logic may be physically implemented. LUT devices are more flexible and provide
more inputs per cell but at the expense of propagation delay.
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4.1.
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4.7.
4.8.
4.9.
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4.6.
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4.20. List two advantages & two disadvantages of FPGA based design.
Advantages:
1. Supports implementation of relatively large logic circuits
2. It can be configured in many different ways.
Disadvantages:
1. Storage cells in FPGA are volatile.
2. Limited utilization of cells based on application.
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ROM problems
1. Size doubles for each additional input
2. Can't exploit don't cares
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4.21. What are the benefits of implementing combinational logic functions using PLAs
when compared with ROMs? (Nov/Dec 2011)
PLA approach advantageous when
1. Design tools are available for multi-output minimization
2. There are relatively few unique minterm combinations
3. Many minterms are shared among the output functions
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5.2.
5.3.
5.4.
5.7.
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5.6.
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5.5.
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5.9.
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entity and_nand is
port (A,B : in bit; Y: out bit);
end and_nand;
architecture concur of and_nand is
Y<= (A and B) nand C;
end concur;
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