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Cypress Product

Roadmap

Q3 2016

Document No. 001-89435 Rev. *L

Roadmap Slide Index


Page

Topic

PSoC and MCU Portfolio

30

CapSense Controllers

41

USB Controllers

53

Wireless Solutions for The IoT

101

Modules

115

Asynchronous SRAM

120

Synchronous SRAM

123

Nonvolatile RAM

129

Timing Solutions

132

Specialty Memory

134

Flash Memory

156

Military Memory

167

Aerospace Memory

171

Energy Harvesting PMIC

178

Automotive Products

Document No. 001-89435 Rev. *L

PSoC and MCU Portfolio

Document No. 001-89435 Rev. *L

PSoC and MCU Portfolio


8-Bit

32-Bit ARM
Cortex-M0/M0+

32-Bit ARM
Cortex-M3

32-Bit ARM
Cortex-M4

32-Bit ARM
Cortex-M7

High Analog Integration

Ultra-Low-Power
8-/16-Bit Replacement

Mid-Range
Performance

High Performance

Next Generation

Analog and Digital Integration

Programmable System-on-Chip (PSoC) is the worlds only programmable embedded


system-on-chip integrating an MCU core, PABs1, PDBs2, programmable interconnect
and routing, and CapSense capacitive sensing
Flexible MCU (FM) is a portfolio of high-performance ARM Cortex-M-based
MCUs for industrial and consumer applications

PSoC 5LP
Cortex-M3
80 MHz, 256KB Flash
20 PAB1, 30 PDB2, 72 I/Os

PSoC 3
8051 CPU
67 MHz, 64KB Flash
Up to 19 PAB1, 30 PDB2, 72 I/Os
PSoC 1
M8C CPU
24 MHz, 32KB Flash
16 PAB1, 16 PDB2, 64 I/Os
8FX
8-bit RISC MCU
16 MHz, 32-50KB Flash

PSoC 4
Cortex-M0
48 MHz, 256KB Flash
Up to 13 PAB1, 20 PDB2, 98 I/Os

PSoC 7
Cortex-M7
NDA Required, Contact Sales
PSoC 6
Cortex-M4 and Cortex-M0+
NDA Required, Contact Sales
FM4-LP MCUs
Cortex-M4 and Cortex-M0+
NDA Required, Contact Sales

FM4 MCUs
Cortex-M4
200 MHz, 2MB Flash, 190 I/Os

FM3 MCUs
Cortex-M3
144 MHz, 1.5MB Flash, 154 I/Os

PSoC Analog Coprocessor


CY8C4Axx
48 MHz, 32KB Flash
Up to 12 PAB1, 11 PDB2, 38 I/Os
FM0+ MCUs
Cortex-M0+
40 MHz, 512KB Flash, 102 I/Os

Production Sampling Development Concept

A programmable analog block that is configured using PSoC software to create analog front ends, signal conditioning circuits
with opamps and filters
2 A programmable digital block that is configured using PSoC software to implement custom digital peripherals and glue logic

Document No. 001-89435 Rev. *L

FM7 MCUs
Cortex-M7
NDA Required, Contact Sales

Status
Availability

QQYY

QQYY

FM4 MCU Portfolio


ARM Cortex-M4
High Performance
S6E2D-Series
160 MHz, 540 CoreMark, 2.7-3.6 V,
2M/36K1, 512KB Video RAM,
120/176 Pins

NEW

S6E2G-Series
180 MHz, 608 CoreMark, 2.7-5.5 V,
1M/192K1, 144/176 Pins

Flash

MB9BFx6xM/N/R-Series
160 MHz, 540 CoreMark, 2.7-5.5 V,
1M/128K1, 32KB Work Flash2,
80/100/120 Pins

S6E2C-Series
200 MHz, 675 CoreMark, 2.7-5.5 V,
2M/256K1, 144/176/216 Pins

NEW

S6E2H-Series
160 MHz, 540 CoreMark, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins

MB9BFx6xK/L-Series
160 MHz, 540 CoreMark, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
48/64 Pins

CPU Speed

Production Sampling Development Concept


1

Flash KB/SRAM KB

Document No. 001-89435 Rev. *L

Independent flash memory available to store data or additional firmware

Status
Availability

QQYY

QQYY

PSoC 5LP Portfolio

CPU Speed and Flash

ARM Cortex-M3 | CapSense | DMA | LCD | RTC | Timer/Counter/PWM


Programmable Digital
PSoC 5200

Intelligent Analog
PSoC 5400

Performance Analog
PSoC 5600

Precision Analog
PSoC 5800

Analog: 1x ADC1, 1x DAC2, 2x CMP3,


0.9% Vref
Interfaces: USB, FF4 I2C

Analog: 1x ADC1, 2x DAC2, 4x CMP3,


2x Opamps, 2x SC/CT PAB5,
0.9% Vref
Interfaces: USB, FF4 I2C

Analog: 2x ADC1, 4x DAC2, 4x CMP3,


4x Opamps, DFB6, 4x SC/CT PAB5,
0.9% Vref
Interfaces: USB, FF4 I2C, CAN7

Analog: 2x/3x ADC1, 4x DAC2,


4x CMP3, 4x Opamps, DFB6,
4x SC/CT PAB5, 0.1% Vref
Interfaces: USB, FF4 I2C, CAN7

CY8C5288
80 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9, 99-CSP10

CY8C5488
80 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9, 99-CSP10

CY8C5688
80 MHz, 256K/64K/2K8
2x 12b SAR ADC1
24x UDB9, 99-CSP10

CY8C5888
80 MHz, 256K/64K/2K8
20b ADC11, 2x 12b SAR ADC1
24x UDB9, 99-CSP10

CY8C5268
67 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9

CY8C5468
67 MHz, 256K/64K/2K8
12b SAR ADC1
24x UDB9

CY8C5668
67 MHz, 256K/64K/2K8
12b ADC11, 12b SAR/2x 12b SAR ADC1
24x UDB9

CY8C5868
67 MHz, 256K/64K/2K8
20b ADC10, 2x 12b SAR ADC1
24x UDB9

CY8C5267
67 MHz, 128K/32K/2K8
12b SAR ADC1
24x UDB9

CY8C5467
67 MHz, 128K/32K/2K8
12b SAR ADC1
24x UDB9

CY8C5667
67 MHz, 128K/32K/2K8
12b ADC11, 12b SAR/2x 12b SAR ADC1
24x UDB9

CY8C5867
67 MHz, 128K/32K/2K8
20b ADC11, 12b SAR ADC1
24x UDB9

CY8C5266
67 MHz, 64K/16K/2K9
12b SAR ADC1
20x UDB10

CY8C5466
67 MHz, 64K/16K/2K8
12b SAR ADC1
20x UDB9

CY8C5666
67 MHz, 64K/16K/2K8
12b ADC11, 12b SAR ADC1
20x UDB9

CY8C5866
67 MHz, 64K/16K/2K8
20b ADC11, 12b SAR ADC1
20x UDB9

CY8C5265
67 MHz, 32K/8K/2K8
12b SAR ADC1
20x UDB9

CY8C5465
67 MHz, 32K/8K/2K8
12b SAR ADC1
20x UDB9

Analog-to-digital converter
Digital-to-analog converter
3 Comparator

Fixed function
Switched capacitor/continuous time
programmable analog block

Document No. 001-89435 Rev. *L

10

Digital filter block


Controller area network
8 Flash KB/SRAM KB/EEPROM KB

Universal digital block


Chip-scale package
11 Delta-Sigma ADC

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

FM3 MCU Portfolio


ARM Cortex-M3

Midrange Performance
MB9BFx2xS/T-Series
60 MHz, 2.7-5.5 V,
1.5M/192K1, 64KB Work Flash2,
144/176 Pins

MB9BFx1xS/T-Series
144 MHz, 2.7-5.5 V,
1M/128K1, 144/176 Pins
MB9BFx1xN/R-Series
144 MHz, 2.7-5.5 V,
512K/64K1, 32KB Work Flash2,
100/120 Pins

MB9AFx2xK/L-Series
40 MHz, 2.7-5.5 V,
512K/32K1, 80/100 Pins
MB9AFx5xM/N/R-Series
40 MHz, 1.7-3.6 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins

Flash

MB9AFx4xL/M/N-Series
40 MHz, 1.7-3.6 V,
256K/32K1, 32KB Work Flash2,
64/80/100 Pins
MB9AFx3xK/L-Series
20 MHz, 1.8-5.5 V,
128K/8K1, 48/64 Pins

MB9AFx1xL/M/N-Series
40 MHz, 2.7-5.5 V,
256K/32K1, 64/80/100 Pins

MB9AFxAxL/M/N-Series
20 MHz, 1.8-5.5 V,
128K/16K1, 64/80/100 Pins

MB9AFx1xK-Series
40 MHz, 2.7-5.5 V,
128K/16K1, 32KB Work Flash2,
48 Pins

MB9BFx2xK/L/M-Series
72 MHz, 2.7-5.5 V,
256K/32K1, 32KB Work Flash2,
48/64/80 Pins

MB9AFx2xK/L-Series
40 MHz, 2.7-5.5 V,
64K/4K1, 48/64 Pins

MB9BF121J-Series
72 MHz, 2.7-5.5 V,
64K/8K1, 32 Pins

CPU Speed
Production Sampling Development Concept
1

Flash KB/SRAM KB

Document No. 001-89435 Rev. *L

Independent flash memory available to store data or additional firmware

Status
Availability

QQYY

QQYY

PSoC 4 Portfolio
ARM Cortex-M0/M0+ | CapSense | Timer/Counter/PWM
PSoC MCU
PSoC 4000

Intelligent Analog
PSoC 4100
BL = BLE-Series

Programmable Digital
PSoC 4200
S = S-Series

M = M-Series

NEW

NEW

NEW

CY8C4128-BL
24-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6

CY8C4248-L
48-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB

CY8C4248-BL
48-MHz M0, 256K/32K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6, UDB7

NEW

NEW

CY8C4247-L
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB

CY8C4247-BL
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6, UDB7

NEW

CY8C4127-M
24-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5

CY8C4127-BL
24-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, BLE6
NEW

Flash

CY8C4126-M
24-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5
NEW

CY8C4125
24-MHz M0, 32K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5

NEW

CY8C4124
24-MHz M0, 16K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5

NEW

CY8C4246-M
48-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, UDB7

CY8C4246-L
48-MHz M0, 64K/8K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8, USB

Q316

CY8C4125-S
24-MHz M0+, 32K/4K1,
2
CMP , Opamp, ADC3, SCB4,
IDAC5, Smart I/O9
NEW

CY8C4024-S
24-MHz M0+, 16K/2K1,
CMP2, ADC3, SCB4,
IDAC5, Smart I/O9

CY8C4247-M
48-MHz M0, 128K/16K1,
CMP2, Opamp, ADC3, SCB4,
IDAC5, UDB7, CAN8

Q316

CY8C4146-S
48-MHz M0+, 64K/8K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, Smart I/O9
NEW

CY8C4045-S
48-MHz M0+, 32K/4K1,
CMP2, ADC3, SCB4,
IDAC5, Smart I/O9

L = L-Series

CY8C4245
48-MHz M0, 32K/4K1,
2
CMP , Opamp, ADC3,
SCB4, IDAC5, UDB7

Q316

CY8C4124-S
24-MHz M0+, 16K/4K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, Smart I/O9

CY8C4244
48-MHz M0, 16K/4K1,
CMP2, Opamp, ADC3,
SCB4, IDAC5, UDB7

CY8C4014
16-MHz M0, 16K/2K1,
CMP2, I2C, IDAC5

1 Flash

KB/SRAM KB

2 Comparator
3 Analog-to-digital

converter

4 Serial

7 Universal

5 Current-output

8 Controller

communication block
DAC
6 Bluetooth Low Energy

Document No. 001-89435 Rev. *L

digital block
area network
9 Embedded programmable digital logic in the I/O subsystem

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

FM0+ MCU Portfolio


ARM Cortex-M0+
Ultra-Low-Power 8-Bit/16-Bit Replacement
NEW

Q416

S6E1B-Series
40 MHz, 1.7-3.6 V,
512K/64K1, 32KB Work Flash2,
80/100/120 Pins, 65 A/MHz3

Flash

S6E1x-Series
48 MHz, 2.2-5.5 V,
Concept Only, Contact Sales

NEW

S6E1C-Series
40 MHz, 1.7-3.6 V,
128K/16K1, 26/32/48/64 Pins , 40 A/MHz3

S6E1A-Series
40 MHz, 2.7-5.5 V,
88K/6K1, 32/48 Pins, 70 A/MHz3

CPU Speed

Flash KB/SRAM KB
Independent flash memory available to store data or additional firmware
3 Active power consumption
2

Document No. 001-89435 Rev. *L

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

PSoC 3 Portfolio
8051 CPU | CapSense | DMA | LCD | RTC | Timer/Counter/PWM
Programmable Digital
PSoC 3200

Intelligent Analog
PSoC 3400

Performance Analog
PSoC 3600

Precision Analog
PSoC 3800

Analog: ADC1, 1x DAC2, 2x CMP3,


0.9% Vref

Analog: ADC1, 2x DAC2, 4x CMP3,


2x Opamps, 2x SC/CT PAB5,
0.9% Vref
Interfaces: FF4 I2C

Analog: ADC1, 2x/4x DAC2,


0x/2x/4x CMP3, 0x/2x/4x Opamps,
0x/2x/4x SC/CT PAB5, 0.1% Vref
Interfaces: USB, FF4 I2C

Analog: ADC1, 2x/4x DAC2,


0x/2x/4x CMP3, 0x/2x/4x Opamps,
0x/2x/4x SC/CT PAB5, 0.1% Vref
Interfaces: USB, FF4 I2C

CY8C3666
67 MHz, 64K/8K/2K6
0x/1x DFB7, 12b ADC1
20x/24x UDB8, CAN9

CY8C3866
67 MHz, 64K/8K/2K6
DFB7, 20b ADC1
20x/24x UDB8, CAN9, 72-CSP10

CY8C3665
67 MHz, 32K/4-8K/1K6
0x/1x DFB7, 12b ADC1
16x/20x UDB8, 72-CSP10

CY8C3865
67 MHz, 32K/4-8K/1K6
0x/1x DFB7, 20b ADC1
16x/20x UDB8

CPU Speed and Flash

Interfaces: FF4 I2C

CY8C3246
50 MHz, 64K/8K/2K6
12b ADC1
24x UDB8, USB, 72-CSP10

CY8C3446
50 MHz, 64K/8K/2K6
12b ADC1
24x UDB8, USB, CAN9

CY8C3245
50 MHz, 32K/4K/1K6
12b ADC1
20x UDB8, USB, 72-CSP10

CY8C3445
50 MHz, 32K/4K/1K10
12b ADC1
20x UDB8, USB

CY8C3244
50 MHz, 16K/2K/0.5K6
12b ADC1
16x UDB8

CY8C3444
50 MHz, 16K/2K/0.5K6
12b ADC1
16x UDB8

Delta-Sigma analog-to-digital converter


Digital-to-analog converter
3 Comparator

Document No. 001-89435 Rev. *L

Fixed function
Switched capacitor/continuous
time programmable analog block

10

Flash KB/SRAM KB/EEPROM KB


Digital filter block
8 Universal digital block

Controller area network


Production Sampling Development Concept
Chip-scale package
Status
10
QQYY
QQYY
Availability

10

PSoC 1 Portfolio
M8C CPU | 24 MHz
PSoC MCU

Programmable Digital

Intelligent Analog

Performance Analog
CY8C29xxx
32K/2K1, 64 GPIOs2
CapSense, 16x PDB3, 4x CMP4,
1x14-bit 5 ADC, 12x SC/CT PAB6
CY8C27xxx
32K/2K1, 44 GPIOs2
CapSense, 8x PDB3, 4x CMP4,
1x14-bit 5 ADC, 12x SC/CT PAB6

CY8C24x93
32K/2K1, 36 GPIOs2
2x CMP4, 1x10-bit Incremental ADC

CY8C24x94
16K/1K1, 56 GPIOs2
CapSense, 4x PDB3, 2x CMP4,
2x14-bit SAR7 ADC, 6x SC/CT PAB6

CY8C28xxx
16K/1K1, 44 GPIOs2
CapSense, 12x PDB3, 4x CMP4,
4x14-bit 5 ADC, 16x SC/CT PAB6

Flash

CY8C2xx45
16K/1K1, 38 GPIOs2
CapSense, 8x PDB3, 4x CMP4,
1x10-bit SAR7 ADC, 6x SC/CT PAB6
CY8C21x34
8K/0.5K1 , 28 GPIOs2
CapSense, 4x PDB3 , 2x CMP4,
1x10-bit Single-Slope ADC, 4x SC/CT PAB6
CY8C23x33
8K/0.25K1, 26 GPIOs2
CapSense, 4x PDB3, 1x CMP4,
1x 8-bit SAR7 ADC, 4x SC/CT PAB6
CY8C21x23
4K/0.25K1, 16 GPIOs2
4x PDB3, 2x CMP4,
1x10-bit Single-Slope ADC, 4x SC/CT PAB6

2 General-purpose

Flash KB/SRAM KB
input/output pins
3 Programmable digital block

Document No. 001-89435 Rev. *L

CY8C24x23
4K/0.25K1, 24 GPIOs2
CapSense, 4x PDB3, 2x CMP4,
1x14-bit 5 ADC, 6x SC/CT PAB6

7 Successive approximation register ADC


Comparator
Delta-Sigma ADC
6 Switched capacitor/continuous time programmable analog block

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

11

8FX MCU Portfolio


8-Bit RISC CPU

CPU Speed and Flash

8-/16-Pin

20-Pin

24-Pin

32-Pin

48-/52-Pin

MB95690K
16 MHz, 2.8-5.5 V
56/2/41
MB95650L
16 MHz, 1.8-5.5 V,
32/1/41
MB95580H
16 MHz, 2.4-5.5 V,
16/0.5/41

64-Pin

80-Pin

MB95810K
16 MHz, 2.8-5.5 V
56/2/41

MB95710M
16 MHz, 1.8-5.5 V
56/2/41

MB95770M
16 MHz, 1.8-5.5 V
56/2/41

MB95630H
16 MHz, 2.4-5.5 V
32/1/41

MB95610H
16 MHz, 2.4-5.5 V
32/1/41

MB95560H
16 MHz, 2.4-5.5 V,
16/0.5/41

MB95570H
16 MHz, 2.4-5.5 V,
16/0.5/41

Production Sampling Development Concept


1

Flash KB/SRAM KB/work flash KB; work flash is independent flash memory available to store data or additional firmware

Document No. 001-89435 Rev. *L

Status
Availability

QQYY

QQYY

12

PSoC 4000 S-Series


PSoC MCU Family
Applications
Consumer devices (wearable, mobile, personal care)
Small home appliances (coffee machine, juicer)

Block Diagram
PSoC 4 One-Chip Solution
MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8
Smart
I/O4

Features
32-Bit MCU Subsystem
48-MHz ARM Cortex-M0+ CPU
Up to 32KB flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 10-bit, 46.8-ksps single-slope ADC2
Two low-power comparators (CMP)
One CapSense block that supports low-power operation and
mutual-capacitance sensing
Two 7-bit IDACs3 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Two serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
25-ball WLCSP, 24-pin QFN, 32-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os4

Collateral
Datasheet:

Flash
(16KB to 32KB)

SRAM
(2KB to 4KB)

CMP
x2

7-bit IDAC3
x2

Single-Slope
ADC2

CapSense

Programmable Digital
Blocks

WCO1

TCPWM x5

Serial Wire Debug

SCB x2

Programmable Interconnect and Routing

48 MHz

Advanced High-Performance Bus (AHB)

Cortex-M0+
GPIO x8
Smart
I/O4

GPIOx8

GPIO x8

GPIO x4

Availability
PSoC 4000S

Production:

1 Watch

3 Current

4 Embedded

crystal oscillator
A simple ADC used to measure slow-moving signals

Document No. 001-89435 Rev. *L

Now

output digital-to-analog converter


programmable digital logic in the I/O subsystem

13

PSoC 4100 S-Series


Intelligent Analog Family
Applications

Block Diagram

Home appliances (washing machine, dishwasher)


Industrial applications

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8

Features

Collateral

48 MHz

Flash
(16KB to 64KB)

SRAM
(4KB to 8KB)

CMP
x2

7-bit IDAC5
x2

Single-Slope
ADC3

CapSense

Programmable Digital
Blocks

WCO1

TCPWM x5

Serial Wire Debug

SCB x3

Programmable Interconnect and Routing

Cortex-M0+
GPIO x8
Smart
I/O6

GPIOx8

GPIO x8

GPIO x4

Sampling:
Production:

1 Watch

3A

4 Programmable

Document No. 001-89435 Rev. *L

Smart
I/O6

SAR2 ADC

Availability

Datasheet: PSoC 4100S


crystal oscillator
Successive approximation register

Opamp
x2

Advanced High-Performance Bus (AHB)

32-Bit MCU Subsystem


48-MHz ARM Cortex-M0+ CPU
Up to 64KB flash, 8KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 46.8-ksps single-slope ADC3
Two opamps configurable as PGAs4, comparators, etc.
Two low-power comparators (CMP)
One CapSense block that supports low-power operation with
self- and mutual-capacitance sensing
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
35-ball WLCSP, 32-pin QFN, 40-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os6

simple ADC used to measure slow-moving signals


gain amplifier

Now
September 2016
5 Current
6

output digital-to-analog converter


Embedded programmable digital logic in the I/O subsystem

14

PSoC 4100 BLE-Series


Intelligent Analog Family with Bluetooth Low Energy
Applications

Block Diagram

Sports and fitness monitors, wearable electronics, medical


devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)

PSoC 4 BLE One-Chip Solution

Features

Collateral

Analog front end(s)


Successive approximation register

Document No. 001-89435 Rev. *L

BLE System

Flash
(128KB to 256KB)

SRAM
(16KB to 32KB)

Advanced High-Performance Bus (AHB)

24 MHz

Serial Wire Debug

CMP
x2

I/O Subsystem
GPIO x8

SAR2
ADC

CSD

Programmable Digital
Blocks

TCPWM3 x4

SCB4 x2

GPIO x8

GPIO x8

GPIO x8

Segment LCD Drive


GPIO x4

Availability

Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)


2

Opamp
x4

Cortex-M0

32-bit MCU subsystem


24-MHz ARM Cortex-M0 CPU
Up to 256KB Flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
Industrys No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta (CSD) controller with touchpad capability
Programmable digital logic
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs4):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.25
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun

Programmable Analog
Blocks

Programmable Interconnect and Routing

MCU Subsystem

3 Timer,
4 Serial

Production:

counter, PWM block


communication block programmable as I2C/SPI/UART

Now
5 Bluetooth

4.2 is only available in the 256KB flash option device

15

PSoC 4200 BLE-Series


Programmable Digital Family with Bluetooth Low Energy
Applications

Block Diagram

Features

Collateral

Analog front end(s)


Successive approximation register

Document No. 001-89435 Rev. *L

Programmable Analog
Blocks
Opamp
x4

BLE System

Flash
(128KB to 256KB)

SRAM
(16KB to 32KB)

Advanced High-Performance Bus (AHB)

48 MHz

CMP
x2

I/O Subsystem
GPIO x8

SAR2
ADC

CSD

Programmable Digital
Blocks

UDB3 x4

TCPWM4 x4

SCB5 x2

GPIO x8

GPIO x8

GPIO x8

Segment LCD Drive


Serial Wire Debug
GPIO x4

Availability

Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)


2

MCU Subsystem

Cortex-M0

32-bit MCU subsystem


48-MHz Cortex-M0 with up to 256KB flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
Industrys No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta (CSD) controller with touchpad capability
Programmable digital logic
Four universal digital blocks (UDBs3): custom digital peripherals
Four configurable TCPWM4 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs5):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.26
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun

PSoC 4 BLE One-Chip Solution

Programmable Interconnect and Routing

Sports and fitness monitors, wearable electronics, medical


devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)

3
4

Universal digital block


Timer/counter/PWM block

Production:
5
6

Now

Serial communication block programmable as I2C/SPI/UART


Bluetooth 4.2 is only available in the 256KB flash option device

16

PSoC 4100 M-Series


Intelligent Analog Family
Applications

Block Diagram

User interface and host processor for home appliances


Digital and analog sensor hub
MCU and discrete analog replacement

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

GPIO x8
SAR1
ADC

Opamp
x4

Features
32-bit MCU subsystem
24-MHz ARM Cortex-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense with SmartSense Auto-tuning
Cypress Capacitive Sigma-Delta (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight programmable 16-bit TCPWM3 blocks
Four SCBs4: I2C master or slave, SPI master or slave, or UART
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN

GPIO x8

Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug

CMP
x2

CSD

8-bit
IDAC2
x2

7-bit
IDAC2
x2

Programmable Digital
Blocks

TCPWM3 x8

Programmable Interconnect and Routing

24 MHz

Advanced High-Performance Bus (AHB)

Cortex-M0

GPIO x8

GPIO x8

GPIO x8

SCB4 x4

GPIO x8

Segment LCD Drive

GPIO x7

RTC

DMA

Collateral
Datasheet:

I/O Subsystem

Availability
Production:

PSoC 4 M-Series (CY8C4100)

1 Successive

approximation register
Current-output digital-to-analog converter

Document No. 001-89435 Rev. *L

Now

Timer/counter/PWM block
Serial communication block programmable as I2C/SPI/UART

17

PSoC 4200 M-Series


Programmable Digital Family
Applications

Block Diagram

User interface and host processor for home appliances


Digital and analog sensor hub
LED control and communication for lighting systems

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8

Features

Collateral

GPIO x8

48 MHz

Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug

CAN x2

CMP
x2

CSD

8-bit
IDAC2
x2

7-bit
IDAC2
x2

Programmable Digital
Blocks
UDB3 x4

TCPWM4 x8

Programmable Interconnect and Routing

Cortex-M0

Advanced High-Performance Bus (AHB)

32-bit MCU subsystem


48-MHz ARM Cortex-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense with SmartSense Auto-tuning
Cypress Capacitive Sigma-Delta (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Four universal digital blocks (UDBs3): custom digital peripherals
Eight programmable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Two controller area network (CAN) controllers
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN

Datasheet:

SAR1
ADC

Opamp
x4

GPIO x8

GPIO x8

GPIO x8

GPIO x8
RTC

SCB5 x4

DMA

Segment LCD Drive

GPIO x7

Availability
Production:

PSoC 4 M-Series (CY8C4200)

1 Successive

approximation register
Current-output digital-to-analog converter

Document No. 001-89435 Rev. *L

Universal digital block


Timer/counter/PWM

Now
5 Serial

communication block programmable as I2C/SPI/UART

18

PSoC 4200 L-Series


Programmable Digital Family
Block Diagram

Applications
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
LED control and communication for lighting systems

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks
Opamp
x4

SAR2

CMP
x6

CSD
x2

8-bit
IDAC3
x2

7-bit
IDAC3
x2

I/O Subsystem
GPIO x8
GPIO x8

ADC

Features
Cortex-M0

Flash
(64KB to 256KB)
SRAM
(8KB to 32KB)
Serial Wire Debug
CAN x2
Full-Speed
USB 2.0
RTC1
DMA

Collateral
Datasheet:
1 Real-time

Programmable Digital
Blocks
UDB x8

TCPWM4 x8

Programmable Interconnect and Routing

48 MHz

GPIO x8

Advanced High-Performance Bus (AHB)

32-bit MCU Subsystem


48-MHz ARM Cortex-M0 CPU with a DMA controller and RTC1
Up to 256KB flash and 32KB SRAM
Up to 98 GPIOs supporting analog and digital interfaces
CapSense With SmartSense Auto-tuning
Two Cypress Capacitive Sigma-Delta (CSD) controllers
Programmable Analog Blocks
Two comparators (CMPs)
Four opamps, configurable as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
Four IDACs3 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight universal digital blocks (UDBs): custom digital peripherals
Eight configurable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Full-Speed USB 2.0 Controller and Transceiver
Two Controller Area Network (CAN) Controllers
Packages: 48-pin TQFP,64-pin TQFP,68-pin QFN,124-pin
VFBGA

GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8

GPIO x8
SCB5

x4
GPIO x8

Segment LCD Drive

GPIO x4

Availability
Production:

PSoC 4 L-Series

clock
approximation register

2 Successive

Document No. 001-89435 Rev. *L

3
4

Current-output digital-to-analog converter


Timer, counter, PWM

Now

Serial communication block programmable as I2C/SPI/UART

19

PSoC Analog Coprocessor


Block Diagram

Applications
Industrial sensors (photoelectric sensors, displacement sensors)
Instrumentation and measurement (photometers, pH meters)
Consumer products (wearables, grooming products)

PSoC Analog Coprocessor


Programmable Analog Blocks

Programmable Analog Blocks


One universal analog block (UAB) configurable as a:
Programmable analog filter or
14-bit Delta-Sigma ADC or
12-bit VDAC1
Four opamps, configurable as PGAs, comparators, TIAs, etc.
One 12-bit, 1-Msps SAR2 ADC
One 10-bit single-slope3 ADC
38-channel analog multiplexer (AMUX)
One CapSense block configurable as a:
Capacitive-sensing controller or
IDACs4 (2x 7-bit) or
Two low-power comparators (CMP)
38 GPIOs

Opamp
x4

10-bit
Single-slope3
ADC

CMP
x2

Universal Analog Block


14-bit
DeltaSigma

AMUX
x38

12-bit
VDAC1

CapSense
7-bit
IDAC4

Analog
Filter

7-bit
IDAC4

Signal Processing Engine


Flash
(16KB to 32KB)

Cortex-M0+
48 MHz

SRAM
(2KB to 4KB)

DMA

TCPWM6 x8

WCO5

SCB7 x3

Signal Processing Engine


48-MHz ARM Cortex -M0+ with a DMA controller and WCO5
Eight 16-bit TCPWM6 blocks
Three SCBs7: configurable as I2C, SPI or UART

GPIO
x8

Programmable Interconnect and Routing

12-bit
SAR2

Features

I/O Subsystem

GPIO
x8

GPIO
x8

GPIO
x8

GPIO
x6

Packages: 28-pin SSOP, 45-pin CSP, 48-pin QFN, 48-pin TQFP

Availability

Collateral
Preliminary Datasheet:

Sampling:
Production:

Contact Sales

4 Current-output

5 Watch

Voltage-output DAC
Successive approximation register
3 A simple ADC used to measure slow-moving signals

Document No. 001-89435 Rev. *L

Now
Q4 2016

DAC
crystal oscillator
6 Configurable as various timers, counters, PWMs or quadrature decoders

7 Serial

communication block

20

S6E1B-Series
FM0+ MCU Portfolio
Block Diagram

Industrial, M2M connectivity, healthcare, consumer electronics,


sensor hubs, metering and point-of-sale equipment

MCU Subsystem

Features

Cortex-M0+
40 MHz

Ultra-Low Power MCU Subsystem


Up to 40-MHz ARM Cortex-M0+ CPU
65-A/MHz active current with 1.65-V to 3.6-V operating voltage
Ultra-low-power 0.6-A real-time clock (RTC) operating current
Up to 512KB flash and 64KB SRAM with 32KB work Flash1
Near-zero wait-state flash access at up to 40 MHz
Fast 540-s startup from power-on reset and 40 s from standby

MFT

MFS x8

PPG x3

USB
(Host + Device)

GPIO x16

GPIO x15

SRAM
(32KB to 64KB)

LVD4

DSTC5
Internal Main
Oscillator
Clock Supervisor

GPIO x9

Dual Timer

GPIO x16
RTC

I2S

Watch Counter

HDMI3 x2
Smart Card x2

WDT6
CRC2

Pin Relocation

Flash
(304KB to 512KB)

GPIO x14

GPIO x12

GPIO x9
Crypto Assist
GPIO x5

Analog Subsystem
12-bit ADC

LCD Drive

Serial Wire
Debug

Packages: 80-pin LQFP, 100-pin LQFP, 120-pin LQFP,


96-pin BGA, 80-pin CSP (4.35 mm x 6.5 mm)

Datasheet:

I/O Subsystem

Base Timer x8

Analog and Digital Subsystems


Multi-function timer (MFT), 3 programmable pulse generators
(PPG), 8 base timers, dual timer, CRC2 and watch counter
8 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
USB, Inter-IC sound (I2S), 2 HDMI-CEC3 channels, 2 Smart Card
interface channels
12-bit, 1-Msps ADC with a 24-channel multiplexer input
LCD drive with support for up to 44 segments or 8 common outputs
Built-in cryptographic assist hardware coprocessor for encryption

Collateral

Digital Subsystem

Advanced High-Performance Bus (AHB)

Applications

GPIO x3

GPIO x3

Availability
S6E1B3-Series, S6E1B8-Series

Sampling: Now

Independent Flash memory available to store data or additional firmware


Cyclical redundancy check
3 HDMI consumer electronics control signal

Document No. 001-89435 Rev. *L

Production: Q4 2016

Low-voltage detect
Descriptor system transfer controller
6 Watchdog timer

21

S6E1C-Series
FM0+ MCU Portfolio
Applications

Block Diagram

Industrial, healthcare, sensor hubs, wearable electronics and


mobile, battery-powered devices

MCU Subsystem

Digital Subsystem

I/O Subsystem
MFS x6

Features

LVD3

DSTC4
Internal Main
Oscillator
Clock Supervisor

Dual Timer

GPIO x3

GPIO x12
RTC

I2S

Watch Counter

HDMI2 x2
Smart Card

WDT5

Pin Relocation

SRAM
(12KB to 16KB)

Advanced High-Performance Bus (AHB)

Flash
(64KB to 128KB)

Packages: 32-pin LQFP, 48-pin LQFP, 64-pin LQFP, 32-pin QFN,


48-pin QFN, 26-pin CSP (2.35mm x 2.72mm)

Datasheet:

GPIO x12

Base Timer x8

Analog and Digital Subsystems


8 base timers, dual timer, CRC1 and watch counter
6 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
USB, Inter-IC sound (I2S), 2 HDMI-CEC2 channels, 2 Smart Card
interface channels
12-bit, 1-Msps ADC with a 24-channel multiplexer input

Collateral

USB
(Host + Device)

Cortex-M0+
40 MHz

Ultra-Low-Power MCU Subsystem


Up to 40-MHz ARM Cortex-M0+ CPU
40-A/MHz active current with 1.65-V to 3.6-V operating voltage
Low-power 1.2-A real-time clock (RTC) operating current
Up to 128KB Flash and 16KB SRAM
Near-zero wait-state flash access at up to 40 MHz
Fast 540-s startup from power-on reset and 40 s from standby

GPIO x8

GPIO x9

GPIO x4
CRC1
GPIO x2

Analog Subsystem
12-bit ADC

Serial Wire
Debug

GPIO x2

GPIO x2

Availability
S6E1C1-Series, S6E1C3-Series

Production: Now

Cyclical redundancy check


HDMI consumer electronics control signal
3 Low-voltage detect

Document No. 001-89435 Rev. *L

Descriptor system transfer controller


Watchdog timer

22

S6E2C-Series
FM4 MCU Portfolio
Block Diagram

Features
High-Performance MCU Subsystem
675 CoreMark, 200-MHz ARM Cortex-M4 CPU
365-A/MHz active current with 2.7-V to 5.5-V operating voltage
Ultra-low-power 1.0-A real-time clock (RTC) operating current
Up to 2MB Flash and 256KB SRAM with 16KB flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
3 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 16 base timers, 4 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
16 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two USB, two CAN3, CAN-FD4, IEEE 1588 Ethernet5, HighSpeed Quad-SPI (HS-QSPI), I2S6 and external bus interfaces
Three 12-bit, 2-Msps ADCs with a 32-channel multiplexer input
Two 12-bit digital-to-analog converters (DACs)
Built-in Cryptographic Assist hardware coprocessor for encryption
Packages: 144-pin LQFP, 176-pin LQFP, 216-pin LQFP,
192-pin BGA

Collateral
Datasheet:

MCU Subsystem

Digital Subsystem

Cortex-M4
200 MHz
Flash
(1MB to 2MB)
SRAM
(128KB to 256KB)
MPU7
LVD
DMA8
DSTC9
Internal Main
Oscillator
Clock Supervisor

I/O Subsystem

MFT x3

MFS x16

GPIO x8

PPG x9

USB x2
(Host + Device)

GPIO x16

Base Timer x16

CAN3 x2

Dual Timer

CAN-FD4

QPRC x4

IEEE 1588
Ethernet5

RTC

SD Card

Watch Counter

HS-QSPI

GPIO x11

I2S6
WDT1
CRC2

GPIO x15
GPIO x16
GPIO x15
GPIO x15
GPIO x4
GPIO x8

External Bus
Interface

GPIO x16

Crypto Assist

GPIO x16

Analog Subsystem
12-bit ADC x3

GPIO x15

Pin Relocation

Motor control, factory automation, industrial, IoT


Building management systems and automation

Advanced High-Performance Bus (AHB)

Applications

GPIO x16
12-bit DAC x2

GPIO x3
GPIO x3

Serial Wire/
JTAG Debug

GPIO x13

Availability
S6E2CC-Series

Production: Now

Watchdog timer
Cyclical redundancy check
3 Controller area network

Document No. 001-89435 Rev. *L

Controller area network with flexible data-rate


Ethernet communications solution that supports the Precision Time Protocol (PTP) standard
6 Inter-IC sound

Memory protection unit


Direct memory access
9 Descriptor System Transfer Controller

23

S6E2G-Series
FM4 MCU Portfolio
Block Diagram

Features
High-Performance MCU Subsystem
608 CoreMark, 180-MHz ARM Cortex-M4 CPU
244-A/MHz active current with 2.7-V to 5.5-V operating voltage
Up to 1MB Flash and 192KB SRAM with 16KB flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
2 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 16 base timers, 2 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
10 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two USB, CAN3, IEEE 1588 Ethernet4, I2S5, 2 Smart Card
interfaces and an external bus interfaces
Three 12-bit, 2-Msps ADCs with a 32-channel multiplexer input
Built-in Cryptographic Assist hardware coprocessor for encryption

MCU Subsystem

Digital Subsystem

Cortex-M4
180 MHz
Flash
(512KB to 1MB)
SRAM
(128KB to 192KB)
MPU6
LVD
DMA7
DSTC8
Internal Main
Oscillator
Clock Supervisor

I/O Subsystem

MFT x2

MFS x10

GPIO x8

PPG x9

USB x2
(Host + Device)

GPIO x16

Base Timer x16

CAN3

GPIO x11
GPIO x15

Dual Timer

GPIO x15

QPRC x2

IEEE 1588
Ethernet4

RTC

SD Card

Watch Counter

Smart Card x2
I2S5

WDT1
CRC2

Analog Subsystem
12-bit ADC x3

GPIO x6

Pin Relocation

Motor control, factory automation, industrial, IoT


Building management systems and automation

Advanced High-Performance Bus (AHB)

Applications

GPIO x7
GPIO x11
GPIO x4
GPIO x6

External Bus
Interface

GPIO x16

Crypto Assist

GPIO x8
GPIO x16
GPIO x3
GPIO x3

Packages: 144-pin LQFP, 176-pin LQFP

Collateral
Datasheet:

Serial Wire/
JTAG Debug

GPIO x8

Availability
S6E2G-Series

Production: Now

Watchdog timer
Cyclical redundancy check
3 Controller area network

Document No. 001-89435 Rev. *L

Ethernet communications solution that supports the Precision Time Protocol (PTP) standard
Inter-IC sound
6 Memory protection unit

Direct memory access


Descriptor system transfer controller

24

S6E2H-Series
FM4 MCU Portfolio
Block Diagram

Motor control, factory automation, industrial, IoT


DSLR lens MCU and home appliance

MCU Subsystem

Digital Subsystem
MFT x3

High-Performance MCU Subsystem


540 CoreMark, 160-MHz ARM Cortex-M4 CPU
188-A/MHz active current with 2.7-V to 5.5-V operating voltage
Ultra-low power 1.3-A real-time clock (RTC) operating current
Up to 512KB Flash and 64KB SRAM with 16KB flash accelerator
Error-correcting code (ECC) support, hardware WDT1, low-voltage
detect and clock supervisor blocks for safety-critical applications
Analog and Digital Subsystems
3 multi-function timers (MFT), 9 programmable pulse generators
(PPG), 8 base timers, 3 quadrature position/revolution
counters (QPRC), a dual timer, CRC2 and watch counter
8 channels of multi-function serial (MFS) interfaces configurable
as SPI, UART, I2C or LIN
Two CAN3, SD Card and External Bus Interfaces
Three 12-bit, 2-Msps ADCs with a 24-channel multiplexer input
Two 12-bit digital-to-analog converters (DACs)
Packages: 80-pin LQFP, 100-pin LQFP, 120-pin LQFP,
121-pin BGA

Collateral
Datasheet:

SRAM
(32KB to 64KB)
MPU4
LVD
DMA5
DSTC6
Internal Main
Oscillator
Clock Supervisor
Serial Wire/
JTAG Debug

GPIO x15

GPIO x16
Base Timer x8

Flash
(256KB to 512KB)

MFS x8

PPG x9

Cortex-M4
160 MHz

Advanced High-Performance Bus (AHB)

Features

I/O Subsystem

CAN3 x2
GPIO x8

Dual Timer
QPRC x3
RTC

GPIO x16
SD Card

Watch Counter
WDT1
CRC2

External Bus
Interface

Pin Relocation

Applications

GPIO x14

GPIO x12

GPIO x9

GPIO x5

Analog Subsystem
12-bit ADC x3

12-bit DAC x2

GPIO x2

GPIO x3

Availability
S6E2H-Series

Production: Now

Watchdog timer
Cyclical redundancy check
3 Controller area network

Document No. 001-89435 Rev. *L

Memory protection unit


Direct memory access
6 Descriptor System Transfer Controller

25

Low-Cost PSoC Development Kits


PSoC Prototyping Kits

Bluetooth Low Energy (BLE)


Pioneer Development Kit

PSoC 5LP Development Kit


by SparkFun1

Kit Number

CY8CKIT-049 or CY8CKIT-059

CY8CKIT-042-BLE

DEV-13229

Key Features

Ultra-low-cost prototyping
Breadboard-compatible
Serial wire debug (SWD) or
bootload for program/debug

Arduino form factor-compatible


Access to all PSoC 4 BLE I/Os
Full SWD program and debug

Arduino form factor-compatible


Access to all PSoC 5LP I/Os
Full SWD program and debug

Price

$4-$10

$49

$50

Learn more or buy a kit today at www.cypress.com/kits


1 SparkFun

is an online retail store that specializes in supporting the hobbyist market with kits and tools to develop small electronics products

Document No. 001-89435 Rev. *L

26

Low-Cost FM Development Kits


FM0+ S6E1B-Series Pioneer Kit FM4 S6E2C-Series Pioneer Kit

FM4 S6E2H-Series Pioneer Kit

Kit Number

FM0-100L-S6E1B8

FM4-176L-S6E2CC-ETH

FM4-176L-S6E2H

Key Features

Arduino form factor-compatible


Full SWD program and debug

Arduino form factor-compatible


Full SWD program and debug

Arduino form factor-compatible


Full SWD program and debug

Price

$49

$49

$25

Learn more or buy a kit today at www.cypress.com/kits


Document No. 001-89435 Rev. *L

27

PSoC Packages
Package
Pins

LQFP
48

PSoC 1

PDIP

QFN

20

28

16

24

32

40

48

56

68

16

20

28

68

72

PSoC 3
PSoC 4

SOIC

PSoC 5LP

CapSense
Package

SSOP

TQFP

Pins

16

20

24

28

32

48

44

PSoC 1

48

WLCSP
64

PSoC 4

100

30

32

PSoC 3

PSoC 5LP

CapSense
Package

WLCSP

BGA

Pins

99

124

PSoC 1

PSoC 3
PSoC 4

PSoC 5LP
CapSense

Document No. 001-89435 Rev. *L

28

MCU Packages
Package

SSOP

TSSOP

SDIP

QFN

Pins

16

20

24

16

20

24

32

32

8FX

FM0+
FM3

48

Pins

80

8FX

FM0+

100

120

FM3

FM4

Document No. 001-89435 Rev. *L

144

176

216

QFP

TEQFP

100

120

32

48

52

64

LQFP

64

FM4
Package

LQFP

BGA
96

112

121

WLCSP
161

192

26

80

29

CapSense Controllers

Document No. 001-89435 Rev. *L

30

CapSense Express

CapSense Plus

PSoC

Configurable Controllers1

Programmable Controllers2

Programmable System-on-Chip2

CY8CMBR3106S
11 Buttons, 2 Sliders
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8CMBR3116
16 Buttons, 8 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8CMBR3108
8 Buttons, 4 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8CMBR3110
10 Buttons, 5 LEDs
Proximity, Liquid Tolerance
SmartSense_EMCplus3

Performance

CY8CMBR2044
4 Buttons, 4 LEDs
SmartSense Auto-tuning

CY8CMBR3002
2 Buttons, 2 LEDs
SmartSense_EMCplus3

1 Standard

CY8C56xx/58xx
62 Buttons, 12 Sliders
64, 128, 256KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8C20xx7
31 Buttons, 6 Sliders
16, 32KB Flash
Proximity, Liquid Tolerance
SmartSense Auto-tuning

CY8C52xx/54xx
62 Buttons, 12 Sliders
32, 64, 128, 256KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8C36xx/38xx
62 Buttons, 12 Sliders
32, 64KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8C20xx6A/S
33 Buttons, 6 Sliders
16, 32KB Flash, 2KB SRAM
SmartSense Auto-tuning

NEW

NEW

Portfolio

CY8C32xx/34xx
62 Buttons, 12 Sliders
16, 32, 64KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8CMBR2016
16 Buttons
SmartSense Auto-tuning

CY8C20xx6H
25 Buttons, 5 Sliders
8, 16KB Flash
SmartSense Auto-tuning
Haptics

CY8C21x34/B
24 Buttons, 4 Sliders
8KB Flash
Proximity, Liquid Tolerance
SmartSense Auto-tuning

CY8C41xx/42xx
36 Buttons, 7 Sliders
16, 32KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8C20x36A
33 Buttons, 6 Sliders
8KB Flash
SmartSense Auto-tuning

CY8C28xx
44 Buttons, 8 Sliders
16KB Flash
Proximity, Liquid Tolerance
SmartSense Auto-tuning

CY8CMBR2010
10 Buttons, 10 LEDs
SmartSense Auto-tuning

CY8C201xx
10 Buttons, 5 LEDs
2 Sliders

CY8C40xx
16 Buttons, 3 Sliders
8, 16KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8C20x34
25 Buttons, 6 Sliders
8KB Flash

Integration

products that are configured for target applications with a graphical user interface
2 Microcontroller-based products that can be freely programmed to implement additional functions
3 SmartSense Electromagnetic Compatible = SmartSense Auto-tuning + high noise immunity

Document No. 001-89435 Rev. *L

CY8C4246/7
96 Buttons, 19 Sliders
64, 128KB Flash
Proximity, Liquid Tolerance
SmartSense_EMCplus3

CY8CMBR2110
10 Buttons, 10 LEDs
SmartSense Auto-tuning

CapSense

CY8CMBR3102
2 Buttons, Proximity
SmartSense_EMCplus3

NEW

CY8C4xx8-BL
36 Buttons, 7 Sliders
256KB Flash, BLE4
Proximity, Liquid Tolerance
SmartSense_EMCplus3
Q316
CY8C41xxS
36 Buttons, 7 Sliders
32KB Flash, 4th Gen
Proximity, Liquid Tolerance
SmartSense_EMCplus3

NEW

CY8C40xxS
36 Buttons, 7 Sliders
64KB Flash, 4th Gen
Proximity, Liquid Tolerance
SmartSense_EMCplus3

Production Sampling Development Concept

Bluetooth Low Energy


Status
Availability

QQYY

QQYY

31

PSoC 4000 S-Series


PSoC MCU Family
Applications
Consumer devices (wearable, mobile, personal care)
Small home appliances (coffee machine, juicer)

Block Diagram
PSoC 4 One-Chip Solution
MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8
Smart
I/O4

Features
32-Bit MCU Subsystem
48-MHz ARM Cortex-M0+ CPU
Up to 32KB Flash, 4KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 10-bit, 46.8-ksps Single-Slope ADC2
Two low-power comparators (CMP)
One CapSense block that supports low-power operation and
mutual-capacitance sensing
Two 7-bit IDACs3 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Two serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
25-ball WLCSP, 24-pin QFN, 32-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os4

Collateral
Datasheet:

Flash
(16KB to 32KB)

SRAM
(2KB to 4KB)

CMP
x2

7-bit IDAC3
x2

Single-Slope
ADC2

CapSense

Programmable Digital
Blocks

WCO1

TCPWM x5

Serial Wire Debug

SCB x2

Programmable Interconnect and Routing

48 MHz

Advanced High-Performance Bus (AHB)

Cortex-M0+
GPIO x8
Smart
I/O4

GPIOx8

GPIO x8

GPIO x4

Availability
PSoC 4000S

Production:

1 Watch

3 Current

4 Embedded

crystal oscillator
A simple ADC used to measure slow-moving signals

Document No. 001-89435 Rev. *L

Now

output digital-to-analog converter


programmable digital logic in the I/O subsystem

32

PSoC 4100 S-Series


Intelligent Analog Family
Applications

Block Diagram

Home appliances (washing machine, dishwasher)


Industrial applications

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8

Features

Collateral

48 MHz

Flash
(16KB to 64KB)

SRAM
(4KB to 8KB)

CMP
x2

7-bit IDAC5
x2

Single-Slope
ADC3

CapSense

Programmable Digital
Blocks

WCO1

TCPWM x5

Serial Wire Debug

SCB x3

Programmable Interconnect and Routing

Cortex-M0+
GPIO x8
Smart
I/O6

GPIOx8

GPIO x8

GPIO x4

Sampling:
Production:

1 Watch

3A

4 Programmable

Document No. 001-89435 Rev. *L

Smart
I/O6

SAR2 ADC

Availability

Datasheet: PSoC 4100S


crystal oscillator
Successive approximation register

Opamp
x2

Advanced High-Performance Bus (AHB)

32-Bit MCU Subsystem


48-MHz ARM Cortex-M0+ CPU
Up to 64KB Flash, 8KB SRAM
Real-time clock capability with a WCO1
Programmable Analog Blocks
One 12-bit, 1-Msps SAR2 ADC
One 10-bit, 46.8-ksps Single-Slope ADC3
Two opamps configurable as PGAs4, comparators, etc.
Two low-power comparators (CMP)
One CapSense block that supports low-power operation with
self- and mutual-capacitance sensing
Two 7-bit IDACs5 configurable as a single 8-bit IDAC
Programmable Digital Blocks
Five 16-bit timer, counter, PWM (TCPWM) blocks
Three serial communication blocks (SCBs) that are configurable
as I2C, SPI or UART
Packages
35-ball WLCSP, 32-pin QFN, 40-pin QFN, 48-pin TQFP
Up to 36 GPIOs, including 16 Smart I/Os6

simple ADC used to measure slow-moving signals


gain amplifier

Now
September 2016
5 Current
6

output digital-to-analog converter


Embedded programmable digital logic in the I/O subsystem

33

PSoC 4100 BLE-Series


Intelligent Analog Family with Bluetooth Low Energy
Applications

Block Diagram

Sports and fitness monitors, wearable electronics, medical


devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)

PSoC 4 BLE One-Chip Solution

Features

Collateral

Analog front end(s)


Successive approximation register

Document No. 001-89435 Rev. *L

BLE System

Flash
(128KB to 256KB)

SRAM
(16KB to 32KB)

Advanced High-Performance Bus (AHB)

24 MHz

Serial Wire Debug

CMP
x2

I/O Subsystem
GPIO x8

SAR2
ADC

CSD

Programmable Digital
Blocks

TCPWM3 x4

SCB4 x2

GPIO x8

GPIO x8

GPIO x8

Segment LCD Drive


GPIO x4

Availability

Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)


2

Opamp
x4

Cortex-M0

32-bit MCU subsystem


24-MHz ARM Cortex-M0 CPU
Up to 256KB Flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
Industrys No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta (CSD) controller with touchpad capability
Programmable digital logic
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs4):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.25
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun

Programmable Analog
Blocks

Programmable Interconnect and Routing

MCU Subsystem

3 Timer,
4 Serial

Production:

counter, PWM block


communication block programmable as I2C/SPI/UART

Now
5 Bluetooth

4.2 is only available in the 256KB flash option device

34

PSoC 4200 BLE-Series


Programmable Digital Family with Bluetooth Low Energy
Applications

Block Diagram

Features

Collateral

Analog front end(s)


Successive approximation register

Document No. 001-89435 Rev. *L

Programmable Analog
Blocks
Opamp
x4

BLE System

Flash
(128KB to 256KB)

SRAM
(16KB to 32KB)

Advanced High-Performance Bus (AHB)

48 MHz

CMP
x2

I/O Subsystem
GPIO x8

SAR2
ADC

CSD

Programmable Digital
Blocks

UDB3 x4

TCPWM4 x4

SCB5 x2

GPIO x8

GPIO x8

GPIO x8

Segment LCD Drive


Serial Wire Debug
GPIO x4

Availability

Datasheet: PSoC 4 BLE (CY8C4XX7 BLE)


2

MCU Subsystem

Cortex-M0

32-bit MCU subsystem


48-MHz Cortex-M0 with up to 256KB flash and 32KB SRAM
Programmable AFE1
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
Industrys No. 1 capacitive-sensing solution with one Capacitive
Sigma-Delta (CSD) controller with touchpad capability
Programmable digital logic
Four universal digital blocks (UDBs3): custom digital peripherals
Four configurable TCPWM4 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs5):
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68-pin CSP
Bluetooth connectivity with Bluetooth 4.1 or Bluetooth 4.26
Royalty-free stack and GUI-based Component to configure profiles
2.4-GHz BLE radio with integrated balun

PSoC 4 BLE One-Chip Solution

Programmable Interconnect and Routing

Sports and fitness monitors, wearable electronics, medical


devices, home automation solutions, game controllers, sensorbased low-power systems for the Internet of Things (IoT)

3
4

Universal digital block


Timer/counter/PWM

Production:
5
6

Now

Serial communication block programmable as I2C/SPI/UART


Bluetooth 4.2 is only available in the 256KB flash option device

35

PSoC 4100 M-Series


Intelligent Analog Family
Applications

Block Diagram

User interface and host processor for home appliances


Digital and analog sensor hub
MCU and discrete analog replacement

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

GPIO x8
SAR1
ADC

Opamp
x4

Features
32-bit MCU subsystem
24-MHz ARM Cortex-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense with SmartSense Auto-tuning
Cypress Capacitive Sigma-Delta (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight programmable 16-bit TCPWM3 blocks
Four SCBs4: I2C master or slave, SPI master or slave, or UART
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN

GPIO x8

Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug

CMP
x2

CSD

8-bit
IDAC2
x2

7-bit
IDAC2
x2

Programmable Digital
Blocks

TCPWM3 x8

Programmable Interconnect and Routing

24 MHz

Advanced High-Performance Bus (AHB)

Cortex-M0

GPIO x8

GPIO x8

GPIO x8

SCB4 x4

GPIO x8

Segment LCD Drive

GPIO x7

RTC

DMA

Collateral
Datasheet:

I/O Subsystem

Availability
Production:

PSoC 4 M-Series (CY8C4100)

1 Successive

approximation register
Current-output digital-to-analog converter

Document No. 001-89435 Rev. *L

Now

Timer/counter/PWM
Serial communication block programmable as I2C/SPI/UART

36

PSoC 4200 M-Series


Programmable Digital Family
Applications

Block Diagram

User interface and host processor for home appliances


Digital and analog sensor hub
LED control and communication for lighting systems

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks

I/O Subsystem
GPIO x8

Features

Collateral

GPIO x8

48 MHz

Flash
(64KB to 128KB)
SRAM
(8KB to 16KB)
Serial Wire Debug

CAN x2

CMP
x2

CSD

8-bit
IDAC2
x2

7-bit
IDAC2
x2

Programmable Digital
Blocks
UDB3 x4

TCPWM4 x8

Programmable Interconnect and Routing

Cortex-M0

Advanced High-Performance Bus (AHB)

32-bit MCU subsystem


48-MHz ARM Cortex-M0 CPU with a DMA controller and RTC
Up to 128KB Flash and 16KB SRAM
CapSense with SmartSense Auto-tuning
Cypress Capacitive Sigma-Delta (CSD) controller
CapSense supported on up to 55 pins
Programmable Analog Blocks
Two comparators (CMP)
Four opamps, programmed as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR1 ADC
Four IDACs2 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Four universal digital blocks (UDBs3): custom digital peripherals
Eight programmable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Two controller area network (CAN) controllers
Packages: 48-pin LQFP, 64-pin TQFP (0.8-mm pitch),
64-pin TQFP (0.5-mm pitch), 68-pin QFN

Datasheet:

SAR1
ADC

Opamp
x4

GPIO x8

GPIO x8

GPIO x8

GPIO x8
RTC

SCB5 x4

DMA

Segment LCD Drive

GPIO x7

Availability
Production:

PSoC 4 M-Series (CY8C4200)

1 Successive

approximation register
Current-output digital-to-analog converter

Document No. 001-89435 Rev. *L

Universal digital block


Timer/counter/PWM

Now
5 Serial

communication block programmable as I2C/SPI/UART

37

PSoC 4200 L-Series


Programmable Digital Family
Block Diagram

Applications
User interface and host processor for home appliances
Digital and analog sensor hub
MCU and discrete analog replacement
LED control and communication for lighting systems

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks
Opamp
x4

SAR2

CMP
x6

CSD
x2

8-bit
IDAC3
x2

7-bit
IDAC3
x2

I/O Subsystem
GPIO x8
GPIO x8

ADC

Features
Cortex-M0

Flash
(64KB to 256KB)
SRAM
(8KB to 32KB)
Serial Wire Debug
CAN x2
Full-Speed
USB 2.0
RTC1
DMA

Collateral
Datasheet:
1 Real-time

Programmable Digital
Blocks
UDB x8

TCPWM4 x8

Programmable Interconnect and Routing

48 MHz

GPIO x8

Advanced High-Performance Bus (AHB)

32-bit MCU Subsystem


48-MHz ARM Cortex-M0 CPU with a DMA controller and RTC1
Up to 256KB flash and 32KB SRAM
Up to 98 GPIOs supporting analog and digital interfaces
CapSense With SmartSense Auto-tuning
Two Cypress Capacitive Sigma-Delta (CSD) controllers
Programmable Analog Blocks
Two comparators (CMPs)
Four opamps, configurable as PGAs, CMPs, filters, etc.
One 12-bit, 1-Msps SAR2 ADC
Four IDACs3 (2x 8-bit, 2x 7-bit)
Programmable Digital Blocks
Eight universal digital blocks (UDBs): custom digital peripherals
Eight configurable 16-bit TCPWM4 blocks
Four SCBs5: I2C master or slave, SPI master or slave, or UART
Full-Speed USB 2.0 Controller and Transceiver
Two Controller Area Network (CAN) Controllers
Packages: 48-pin TQFP,64-pin TQFP,68-pin QFN,124-pin
VFBGA

GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8
GPIO x8

GPIO x8
SCB5

x4
GPIO x8

Segment LCD Drive

GPIO x4

Availability
Production:

PSoC 4 L-Series

clock
approximation register

2 Successive

Document No. 001-89435 Rev. *L

3
4

Current-output digital-to-analog converter


Timer/counter/PWM

Now

Serial communication block programmable as I2C/SPI/UART

38

Low-Cost PSoC Development Kits


PSoC Prototyping Kits

Bluetooth Low Energy (BLE)


Pioneer Development Kit

PSoC 5LP Development Kit


by SparkFun1

Kit Number

CY8CKIT-049 or CY8CKIT-059

CY8CKIT-042-BLE

DEV-13229

Key Features

Ultra-low-cost prototyping
Breadboard-compatible
Serial wire debug (SWD) or
bootload for program/debug

Arduino form factor-compatible


Access to all PSoC 4 BLE I/Os
Full SWD program and debug

Arduino form factor-compatible


Access to all PSoC 5LP I/Os
Full SWD program and debug

Price

$4-$10

$49

$50

Learn more or buy a kit today at www.cypress.com/kits


1 SparkFun

is an online retail store that specializes in supporting the hobbyist market with kits and tools to develop small electronics products

Document No. 001-89435 Rev. *L

39

PSoC Packages
Package
Pins

LQFP
48

PSoC 1

PDIP

QFN

20

28

16

24

32

40

48

56

68

16

20

28

68

72

PSoC 3
PSoC 4

SOIC

PSoC 5LP

CapSense
Package

SSOP

TQFP

Pins

16

20

24

28

32

48

44

PSoC 1

48

WLCSP
64

PSoC 4

100

30

32

PSoC 3

PSoC 5LP

CapSense
Package

WLCSP

BGA

Pins

99

124

PSoC 1

PSoC 3
PSoC 4

PSoC 5LP
CapSense

Document No. 001-89435 Rev. *L

40

USB Controllers

Document No. 001-89435 Rev. *L

41

USB 3.1

USB Portfolio
Device

Hub

Bridge

CYUSB301x
FX3

CYUSB33xx
HX3

32-Bit Bus to USB 3.1 Gen 1


ARM9, 512KB RAM

USB 3.1 Gen 1, Shared Link1


BC 1.22, Ghost Charge3

FX3PD

NEW

USB 3.1 Gen 2 Type-C


Peripheral Controller with PD
Contact Sales

CYUSB333x
HX3C

Storage

Type-C

CYUSB306x
CX3

CYUSB303x
FX3S

CYPD1xxx
CCG1

CSI-24 to USB 3.1 Gen 1


4 CSI-24 Lanes, 1 Gbps/Lane

16-Bit Bus to USB 3.1 Gen 1


RAID5, Dual SDXC6/eMMC7

USB Type-C Port Controller


1 PD Port, 5 Profiles, 100 W

CYUSB361x
GX3

CYUSB302x
SD3

CYPD2xxx
CCG2

USB 3.1 Gen 1 to GigE


Energy Efficient Ethernet

USB 3.1 Gen 1 SD Reader


SDXC6/eMMC7, RAID5

USB Type-C Cable Controller


1 PD Port, Termination, ESD

Q316

4 Ports: 1 Type-C, 3 Type-A


USB PD, Billboard, BC1.22

HX3PD

USB 1.1

USB 2.0

USB 3.1 Gen 2 Type-C


Hub with PD
Contact Sales

Host

NEW

DX3
DSI8

USB 3.1 Gen 1 to


Contact Sales

TX

Q316

CYPD3xxx
CCG3

USB Type-C Port Controller


20-V, Crypto, Billboard

CY7C6801x/53
FX2LP

CY7C656x4
HX2VL

CYWB016xBB
Bay

CYWB0x2xABS
Arroyo, Astoria

NEW

16-Bit Bus to USB 2.0


8051, 16KB RAM

4 Ports
4 Transaction Translators

HS USB OTG
Dual SDXC6/eMMC7

16-Bit Bus to USB 2.0


8051, Dual SD/eMMC7

USB Type-C Port Controller


2 PD Ports,128KB Flash, Mux

CY7C68003
TX2UL

CY7C656x1
HX2LP

CY7C6803x
NX2LP

4 Ports, Industrial Grade


1 Transaction Translator

NAND Flash to USB 2.0


8051, 15KB RAM

ULPI9

PHY
13, 19.2, 24, 26 MHz

CY7C683xx
AT2LP

32-Bit Bus to USB 2.0


ARM9 512KB RAM

Parallel ATA to USB 2.0


8051

CY7C6521x
USB-Serial

M8C MCU, 20 GPIOs


SPI, 8KB Flash

UART/SPI/I2C to USB
2 Channels, CapSense

CY7C64215
enCoRe III

CY7C65213
USB-to-UART (Gen 2)

M8C MCU, 50 GPIOs, ADC


I2C/SPI, 16KB Flash

SL811HS
FS USB Host/Device
256Byte RAM

4 Ports, FS USB OTG


32 GPIOs

CY7C643xx
enCoRe V

CY7C65210/7
USB Billboard

CY7C67200
EZ-OTG

M8C MCU, 36 GPIOs, ADC


I2C/SPI, 32KB Flash

ARM Cortex M0
1 or 2 UART/SPI/I2C channels

2 Ports, FS USB OTG


25 GPIOs

USB 2.0 and


SuperSpeed traffic on the same port
2 Battery Charging specification v1.2

Document No. 001-89435 Rev. *L

3 Enables

USB charging without


host connection
4 Camera Serial Interface v2.0

5 Redundant

array of
independent disks
6 SD extended capacity

USB Type-C AFE


Contact Sales

Type-C products
apply to any
USB speed

CY7C67300
EZ-Host

3 Mbps, 8 GPIOs

1 Simultaneous

Q316

CCG5

CYUSB201x
FX2G2

CY7C638xx
enCoRe II

CYPD4xxx
CCG4/CCG4M

Concept

7 Embedded

Multimedia Card
Serial Interface
9 UTMI low-pin interface
8 Display

Development

Sampling

Production

QQYY

QQYY

Status
Availability

42

CCG1

USB Type-C and PD Port Controller


Block Diagram

Notebooks, tablets, monitors, docking stations, power adapters,


Type-C EMCAs1 and dongles

CCG1: USB Type-C Port Controller with PD


MCU Subsystem

Programmable Analog
Blocks

Features

IDAC

32-bit MCU Subsystem


48-MHz ARM Cortex-M0 CPU with 32KB flash and 4KB SRAM
Integrated Analog Blocks
12-bit, 1-Msps ADC for VBUS voltage and current monitoring
Dynamic overcurrent and overvoltage protection
Integrated Digital Blocks
Two configurable 16-bit TCPWM2 blocks
One SCB3: I2C master or slave, SPI master or slave, or UART
Up to eight GPIOs
Type-C Support
Integrated Type-C transceiver, supporting two Type-C ports
Controls routing of all protocols to an external MUX
PD Support
Supports provider4 and consumer5 roles and all power profiles
Low-Power Operation
1.71-5.5 V operation
Sleep: 1.3 mA, Deep Sleep: 1.3 A
Packages
40-pin QFN (36 mm x 36 mm), 35-ball CSP (6.8 mm x 6.8 mm),
16-pin SOIC (60 mm x 60 mm)

Collateral

Electronically Marked Cable Assembly


Timer/Counter/Pulse-Width Modulation

Document No. 001-89435 Rev. *L

ADC

CORTEX-M0
48 MHZ

Flash
(32KB)

SRAM
(4KB)

Advanced High-Performance Bus (AHB)

Type-C
Port 1
Comparators

Programmable Digital
Blocks
TCPWM
SCB
(I2C, SPI, UART)
Profiles and
Configurations
Baseband MAC

Type-C
Port 2

GPIO
Port
Serial Wire Debug

Baseband PHY

Availability

Datasheet:
CCG1 Datasheet
Reference Design Kit: CCG1 RDK
1

I/O Subsystem

Programmable Interconnect and Routing

Applications

Serial communication block


Type-C port that sources power over VBUS

Production:
5A

Now

Type-C port that sinks power from VBUS

4A

43

CCG2

USB Type-C and PD Port Controller


Applications

Block Diagram

USB Type-C Electronically Marked Cabled Assembly (EMCA) and


powered accessories

CCG2: USB Type-C Port Controller With PD


MCU Subsystem

Integrated Digital Blocks

I/O Subsystem

Features

CC7

Flash
(32KB)

SRAM
(4KB)

VCONN2

SCB1
(I2C, SPI, UART)

Profiles and
Configurations
Baseband MAC
Baseband PHY

Programmable I/O Matrix

48 MHz

VDDIO
GPIO5
Port

Integrated RP, RD, RA

Serial Wire Debug

Production:

CCG2 Datasheet
CCG2 RDK

1 Serial

communication block configurable as UART, SPI or I 2C


Termination resistor read as a Down Facing Port (DFP)

4 Termination

Document No. 001-89435 Rev. *L

CORTEX-M0

VCONN1

SCB1
SPI, UART)

Availability

Collateral
Datasheet:
Reference Design Kit:

(I2C,

Advanced High-Performance Bus (AHB)

32-bit MCU Subsystem


48-MHz ARM Cortex -M0 CPU with 32KB flash and 4KB SRAM
Integrated Digital Blocks
Integrated timer/counter/pulse-width modulators (TCPWMs)
Two SCBs1 configurable to I2C, SPI or UART modes
Type-C Support
Integrated transceiver, supporting one Type-C port
Integrated DFP (RP2), UFP (RD3), EMCA (RA4) termination resistors
Power Delivery (PD) Support
Standard power profiles
Low-Power Operation
Two independent VCONN rails with integrated isolation
Independent supply voltage pin for GPIO5
2.7-5.5-V operation
Sleep: 2.0 mA; Deep Sleep: 2.5 A
System-Level ESD on CC6 and VDD Pins
8-kV contact, 15-kV Air Gap IEC61000-4-2 level 4C
Packages
20-ball CSP (3.3 mm x 3.3 mm) with 0.4-mm ball pitch,
14-pin DFN (2.5 mm x 3.5 mm)with 0.6-mm pin pitch,
24-pin QFN (4 mm x 4 mm) with 0.55-mm pin pitch

TCPWM6

Now

Termination resistor read as a Up Facing Port (UFP)


resistor read as an EMCA

5 General-purpose
6

input/output
Configuration Channel

44

CCG3

USB Type-C and PD Port Controller


Block Diagram

Applications
Accessories and power adapters

CCG3: USB Type-C Cable Controller

Collateral
Datasheet:

Cortex-M0
48 MHz

Flash
(64KB)

Flash
(64KB)

4x TCPWM9
4x SCB4
(I2C, SPI, UART)
Crypto Engine

I/O Subsystem

Programmable
I/O Matrix

Type-C Support
Integrated transceiver, supporting one Type-C port
Alternate modes1, Crypto Engine2 for USB authentication3
Power Delivery (PD) Support for Standard Power Profiles
Integrated Digital Blocks for VBUS Power and MUX Interface
Four TCPWMs, 24x GPIOs
Four SCBs4 for configurable master/slave I2C, SPI or UART
USB Billboard Controller5 with Billboard Device Class6 support
Integrated Analog Blocks for OVP/OCP7
20-V OVP/OCP; 4:2 cross-bar switch
32-bit ARM Cortex-M0 CPU with MCU Subsystem
2x64KB Flash for fail-safe updates over CC, I2C or USB interfaces
Low-Power Operation
2x VBUS Gate Drivers8, for consumer and provider power paths
2x high-voltage (5-20 V, 25 V maximum) VBUS voltage inputs
Sleep: 2.0 mA; Deep Sleep: 2.5 A with wake-on-I2C or wake-on-CC
System-Level ESD on CC/VCONN, VBUS, and SBU Pins
8-kV contact, 15-kV Air Gap IEC61000-4-2 Level 4C
Packages
42-ball (8.5 mm2) CSP and 40-pin (36 mm2) QFN

Integrated Digital Blocks

Advanced High-Performance Bus (AHB)

MCU Subsystem

Features

CC

24x GPIO
Ports

USB PD Subsystem
Baseband MAC

Baseband PHY

20-V Regulator

2x VCONN FETs

Overcurrent
Protection

2x 20V VBUS FET


Gate Drivers8

System Resources

Overvoltage
Protection

Integrated Resistors
(RP, RD, RA)10

Full-Speed USB
Billboard Controller

4:2 Analog
Cross-Bar Switch

8-bit SAR ADC

SRAM
(8KB)

Availability
Samples:

CCG3 Datasheet

Mode of operation in which the data lines are repurposed to transmit non-USB data
The encryption hardware and software required to implement USB Authentication
3 A USB-IF specification that defines the authentication protocol for Type-C accessories
4 Serial communication block configurable as UART, SPI or I 2C
5 A USB Device controller that informs the USB Host of the supported Alternate Modes

Document No. 001-89435 Rev. *L

Now

Production:

Q3 2016

A specification that defines the method for a USB Device to communicate the supported Alternate Modes
Overvoltage protection, overcurrent protection
8 Circuits to control the gates of external power Field-Effect Transistors (FETs) on V
BUS (5-20 V)
9 Timer/counter/pulse-width modulator block
10 Termination resistors: R read as a DFP, R as a UFP, R as an EMCA
P
D
P

45

CCG4/4M

USB Type-C and PD Port Controller


Applications

Block Diagram

Notebooks, tablets, monitors, docking stations, power adapters

CCG4/4M: Two-Port Type-C Controller with Power Delivery

Features
ARM
Cortex-M0
48 MHz

Flash
(128KB)

SRAM
(8KB)

16

4x SCB1
32

32

Type-C
Baseband
Transceiver

Type-C
Baseband
Transceiver

CC

CC
2x VCONN
FETs

4x
TCPWM

24
GPIOs

2x VCONN
FETs

4x 8-bit
SAR ADC

Programmable I/O Matrix

Integrated USB Type-C Transceivers Support Two Type-C Ports


Integrated 2x 1-W VCONN FETs and 2x FET control signals, per
port programmable RP1 and removable RP, and RD2 terminations
Supports dead battery mode operation
Integrated SuperSpeed USB/DisplayPort (DP) Mux (CCG4M)
Increased Flash Enables Fail-Safe Bootup
Integrates 128KB flash to store dual FW images for Fail-Safe Boot
Integrated Digital Blocks for Inter-Chip Communications
Four SCBs3 master or slave configurable to I2C, SPI or UART
SCBs interconnect CCG4 with embedded controller,
two alternate muxes and Thunderbolt4 controller (optional)
Integrated Blocks for OVP5 and OCP6
Four 8-bit SAR ADCs configurable for OVP and OCP
Low-Power Operation
2.7-V to 5.5-V operation and independent supply voltage for general
purpose input/output (GPIO) Sleep: 2.0 mA; Deep Sleep: 2.5 A
with wake-on-I2C or wake-on-configuration channel (CC)
System-Level ESD on CC Pins
8-kV contact, 15-kV Air Gap IEC61000-4-2 level 4C
32-bit ARM Cortex -M0 CPU with MCU Subsystem
128KB Flash, upgradable over CC lines or I2C interface
Packages
40-pin QFN, 96-ball BGA (CCG4M)

To
EC7
24

SS_
USB
+
DP

USB/DP
Mux
(CCG4M)

2
12

Type-C
Port 1

Type-C
Port 2

SS_USB
+ DP

AUX

SBU

Availability
Samples: Now

Production: Q3 2016

Collateral
Datasheet: CCG4 Datasheet
1 Termination

4 An

resistor read as a DFP


Termination resistor read as a UFP

Document No. 001-89435 Rev. *L

Serial communication block configurable as UART, SPI or I2C


interface jointly defined by intel and Apple that connects peripherals to a computer

5
6

Overvoltage protection
Overcurrent protection

Embedded controller in a PC

46

HX3C

USB 3.0 Type-C PD Hub1


Block Diagram

Applications
USB Type-C charging hubs1, adapters and accessories
Docking stations for notebook PCs and tablets
Televisions and monitors
PC motherboards and servers
Set-top boxes, home gateways and routers

EEPROM

USB Type-C (US Port)


2

HX3C Hub

SS6 PHY

MCU

Features

USB 2.0 PHY CC5

16

32

Directs data traffic between a USB Host and multiple USB Devices
A USB Device controller that is used to implement the USB Billboard Device Class
Informs the USB Host of the supported Alternate Modes as well as any failures

Document No. 001-89435 Rev. *L

USB 2.0 Hub1 Controller

SS6 Hub1 Controller

16

32
Buffers

4x TT7

Repeater

16

32
Routing Logic

USB
Billboard
Controller2

Routing Logic
16

32

USB 3.1 Gen 1 PHY


SS6 PHY

USB Type-A (DS Port)

USB 3.1 Gen 1 PHY

USB 2.0 PHY SS6 PHY

Collateral

PD
Controller

32

USB 3.1 Gen 1-compliant Hub1 controller


Upstream (US): Type-C
Downstream (DS): 1 Type-C and 2 Type-A ports
Integrated Type-C transceivers, supporting two ports
Integrated DFP (RP) and UFP (RD) termination resistors
Integrated USB Billboard Controller2
Charging Support: USB PD, BC v1.23, Apple Charging
Standard4
PD policy engine configures power profiles dynamically
Ghost Charge: Charging DS without US connection
Firmware upgradable over USB
System-Level ESD on CC5 Pins: 8 kV contact, 15 kV airconfigurable USB SS6 and USB 2.0 PHY (drives 11 trace)
121-ball BGA (10 mm x 100 mm, 0.8 mm ball-pitch)

Datasheet:
CYUSB3333/CYUSB3343
Product Overview: EZ-USB HX3C: USB 3.0 Type-C Hub
with Power Delivery

USB 3.1 Gen 1 PHY

USB Type-A (DS Port)

USB 3.1 Gen 1 PHY

USB 2.0 PHY SS6 PHY

USB 2.0 PHY CC5

PD
Controller

USB Type-C (DS Port)

Availability
Samples:
Production:
3A

Now
Q3 2016

specification published by the USB Implementers Forum


(USB-IF) for charging portable USB Devices
4 An Apple-specified battery charging standard for the iPhone,
iPod and iPad

Configuration Channel
USB SuperSpeed
7 Transaction Translator
6

47

GX3

USB 3.1 Gen 1 to GigE1 Bridge


Block Diagram

USB dongles, docking stations and port replicators


Network printers and security cameras
Ultrabooks and home gateways
Game consoles and portable media players
DVRs, IP set-top boxes and IP TVs
Other embedded systems

GX3 Bridge
Data SRAM

Program
ROM

DMA
Engine

RISC SOC

GigE MAC
Controller

USB
Controller

One-chip USB 3.1 Gen 1 to 10/100/1000M GigE bridge


Integrates USB 3.1 Gen 1 PHY and GigE PHY
Integrates USB 3.1 Gen 1 Controller and GigE MAC2
Needs only a 25-MHz crystal to drive both USB & GigE1 PHY
IEEE 802.3az3 support for low-power idle state
Supports dynamic cable length and power adjustment
Offers multiple power management wake-on-LAN4 features
Supports optional EEPROM to store USB descriptors
Integrates on-chip POR5 circuitry
68-QFN (8 x 8 x 0.85 mm)

GigE1 PHY

Features

I2C

GPIO

Clock

USB 3.1 Gen 1 PHY

Applications

USB 3.1
Gen 1
Host

Reset

Collateral
Datasheet:
GX3 Datasheet
Reference Design Kit: GX3 RDK
Software Drivers:
GX3 Drivers

Availability
Production:

Now

1 Gigabit

Ethernet
Media access controller that provides the address to an Ethernet node
3 A new-energy efficient Ethernet standard
4 An Ethernet standard that allows a computer to be turned on by a network message
5 Power-on-reset
2

Document No. 001-89435 Rev. *L

48

HX3

USB 3.1 Gen 1 Hub


Applications

Block Diagram

Docking stations for notebook PCs and tablets,


PC motherboards, servers, digital TV, monitors, retail hub
boxes, printers, scanners, set-top boxes, home
gateways, routers and game consoles

Upstream Port

EEPROM
2

4
HX3 Hub
SS3 PHY

USB 2.0 PHY

MCU

USB 3.1 Gen 1 PHY

I2C

32

Features

16

32

USB 3.1 Gen 1-compliant four-port Hub Controller


USB-IF certified (Test ID: 330000047)
WHQL certified for Windows 7, Window 8, Windows 8.1
Shared Link supports simultaneous USB 2.0 and
USB SuperSpeed (SS) devices on the same port
Ghost Charge enables USB charging while the hub is
disconnected from a USB Host
Charging Standard support:
USB-IF Battery Charging v1.2
Apple Charging Standard
Charging an OTG Host in an ACA-Dock
Programming of external EEPROM via USB
Configurable USB SS and USB 2.0 PHY that drives 11 trace
68-QFN (8 x 8 x 1.0 mm), 88-QFN (10 x 10 x 1.0 mm),
100-BGA (6 x 6 x 1.0 mm)

SuperSpeed Hub
Controller

USB 2.0 Hub Controller


16

32
Buffers

4x TT1

Repeater

16

32
Routing Logic

Routing Logic
32
16
USB 3.1 Gen 1 PHY

USB 3.1 Gen 1 PHY


SS3

PHY

USB 2.0 PHY

USB 3.1 Gen 1 PHY


SS3

PHY

SS3 PHY

USB 2.0 PHY

USB 3.1 Gen 1 PHY


SS3 PHY

USB 2.0 PHY

USB 2.0 PHY

2
4

Downstream Port 1

Downstream Port 2

Downstream Port 3

Downstream Port 4

Collateral
Datasheet:
Application Note:
Kits:
Configuration Utility:
1

HX3 Datasheet
HX3 Hardware Design Guide
CY4609, CY4603, CY4613
Blaster Plus2

Transaction translator

Document No. 001-89435 Rev. *L

Availability
Production:

Now

A Cypress GUI-based PC application for setting HX3 configuration parameters

SuperSpeed

49

FX3

USB 3.1 Gen 1 Peripheral Controller


Block Diagram

Industrial
Medical and machine vision cameras
3-D and 1080p full HD and 4K Ultra HD (UHD) cameras
Document and fingerprint scanners
Videoconferencing and data acquisition systems
Video capture cards and HDMI converters
Protocol and logic analyzers
USB test tools and software-designed radios (SDRs)

5
FX3 Controller
JTAG
512KB
RAM

Image
Sensor,
FPGA or
ASIC

Features
USB 3.1 Gen 1-compliant peripheral controller
USB-IF certified (TID:340800007)
Fully accessible 32-bit, 200-MHz ARM926EJ core
512KB of embedded SRAM for code space and buffers
Up to 32-bit, 100-MHz, flexible GPIF II interface
Other peripheral interfaces such as I2C, I2S, UART, SPI and
12 GPIOs
Unused I/O pins can be used as GPIOs
Up to 32 USB endpoints
Flexible clock options:
19.2-MHz crystal
19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input
121-ball BGA (10 x 10 mm), 131-ball WLCSP (4.7 x 5.1 mm)

32

32

32

USB 3.1 Gen 1

ARM9

GPIF-II

Applications

32

32
32

UART

I2C

I2S

SPI

USB 3.1
Gen1
Host

GPIO

12

Availability
Production:

Now

Collateral
Datasheet:
Development Kit:
Software Development Kit:

Document No. 001-89435 Rev. *L

CYUSB301X/CYUSB201X
FX3 SuperSpeed Explorer Kit
EZ-USB FX3 SDK

50

FX3S

USB 3.1 Gen 1 RAID1-on-Chip


Applications

Block Diagram

Servers
Routers
Mobile storage
USB flash drives
POS terminals
Automatic teller machines (ATM)
SDIO expanders and data logging devices

16

GPIF II

ASIC,
FPGA,
SoC

USB 3.1 Gen 1-compliant Peripheral Controller


USB-IF certified (TID:340800007)
Fully accessible 32-bit, 200-MHz ARM926EJ core
512KB of embedded SRAM for code space and buffers
Up to 16-bit, 100-MHz, flexible GPIF II interface
Peripheral interfaces such as I2C, UART, SPI and GPIOs
Supports two SDXC2, eMMC3 4.4, or SDIO 3.0 interfaces
Support RAID0 or RAID1 configurations
Flexible clock options:
19.2-MHz crystal
19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input
121-ball BGA (10 x 10 mm)
131-ball WLCSP (4.7 x 5.1 mm)

32

32

32
32

SDXC2/eMMC3S
DIO

4
SD Card,
eMMC3 NAND,
SDIO Device

USB 3.1
Gen 1
Host

SDXC2/eMMC3S
DIO

4
SD Card,
eMMC3 NAND,
SDIO Device

Availability

Collateral

1 Redundant

512KB
RAM
(RAID1
Firmware)

ARM9

Features

Datasheet:
Kit:
Software:
App Notes:

JTAG

USB 3.1 Gen 1

FX3S
RAID1-on-Chip

EZ-USB FX3S
FX3S RAID1-on-Chip Boot Disk Kit
FX3 Software Development Kit (SDK)
FX3S Hardware Design Guidelines (AN70707)
USB RAID 1 Disk Design Using FX3S (AN89661)

array of independent disks

Document No. 001-89435 Rev. *L

2 SD

extended capacity

3 Embedded

Production:

Now

Multimedia Card

51

CX3

MIPI1 CSI-2 to USB 3.1 Gen 1 Bridge


Block Diagram

Features
USB 3.1 Gen 1-compliant video-class controller
Four-lane MIPI1 Camera Serial Interface v2.0 (CSI-2) input
Camera Control Interface (CCI) for image sensor configuration
Supports industry-standard video data formats:
RAW8/10/12/142, YUV422/4443, RGB888/666/5654
Supports uncompressed streaming video:
4K UHD at 15 fps, 1080p at 30 fps, 720p at 60 fps
On-chip ARM9 with 512KB RAM for data processing
Supports I2C, I2S, SPI, UART and 12 GPIOs
121-BGA (10 x 10 x 1.7 mm)

Collateral
Datasheet:
Reference Design Kit:
Software Development Kit:

5
CX3 Bridge
JTAG
512KB
RAM
ARM9
Image
Sensor or
Image
Signal
Processor

32

32

32

32

UART

I2C

SPI

USB 3.1 Gen 1

Industrial
Medical and machine vision cameras
1080p full HD and 4K Ultra HD (UHD) cameras
Document scanners
Fingerprint scanners
Game consoles
Videoconferencing systems
Notebook PCs
Tablets and image acquisition systems

MIPI1 CSI-2

Applications

USB 3.1
Gen 1
Host

GPIO

12

Availability
Production:

Now

CYUSB306X
CX3 Reference Design
EZ-USB SDK

Mobile Industry Processor Interface


format for raw video data
3 Video format for luminance and chrominance components
4 Video format for red, green and blue pixel components
2 Video

Document No. 001-89435 Rev. *L

52

Wireless Solutions for the IoT

Document No. 001-89435 Rev. *L

53

Bluetooth

Wi-Fi

Wi-Fi + Bluetooth Combo

Automotive

NEW

NEW

IEEE 802.11a/b/g/n/ac WLAN1 + Bluetooth


Up to 867 Mbps Wi-Fi, 1-3 Mbps Bluetooth
Dual Band (2.4/5 GHz), 2x2 MIMO2

IEEE 802.11a/b/g/n/ac WLAN + Bluetooth


Up to 867 Mbps
Dual Band (2.4/5 GHz), 2x2 MIMO, RSDB3

NEW

Integration and Performance

NEW

IEEE 802.11a/b/g/n WLAN + MCU


Up to 150 Mbps
ARM Cortex-R4/-M3 MCU

IEEE 802.11a/b/g/n WLAN + Bluetooth


Up to 300 Mbps Wi-Fi, 1-3 Mbps Bluetooth
Dual Band (2.4/5 GHz), 2x2 MIMO

NEW
NEW

IEEE 802.11a/b/g/n WLAN


Up to 300 Mbps
2x2 MIMO

Wireless Portfolio

Bluetooth (BR4 + EDR5 + BLE6) + MCU


1-3 Mbps,
Class 1/2/37, ARM Cortex-M4/-M3 MCU

NEW

Bluetooth (BR + EDR)


1-3 Mbps
Class 1/2/3

PSoC 4 BLE
1 Mbps, CapSense
ARM Cortex-M0 MCU, AFE8, Opamp, TIA9

PRoC BLE
1 Mbps, CapSense
ARM Cortex-M0 MCU

NEW

Bluetooth Low Energy (BLE) + MCU


1-2 Mbps,
ARM Cortex-M3 MCU

2 Multiple-input

5 Enhanced

Wireless Local Area Network


multiple-output
3 Read simultaneous dual band

Document No. 001-89435 Rev. *L

Basic Rate
Data Rate
6 Bluetooth Low Energy

Concept

Class 1 (100 m)/2 (10 m)/3 (1 m)


Analog front end
9 Transimpedance amplifier
8

Development

Sampling

Production

QQYY

QQYY

Status
Availability

54

Wireless Solutions for The Internet of Things (IoT)


Roadmap

BLE PORTFOLIO

Document No. 001-89435 Rev. *L

55

Bluetooth Low Energy (BLE) Portfolio


WICED

PSoC Creator
PRoC BLE (MCU + Touch1)

BLE + MCU

PSoC 4 BLE (MCU + Touch + Mixed-Signal)

NEW

Q416
BCM20719
CM42, SPI, UART, I2C3,
IR TX/RX4, ADC, 6 PWM,
KB Scanner5, Mouse QD6,
Crypto7, 4 TRIAC Control,
40 GPIO, 1MB Flash,
512KB RAM, BT8 4.2,
2 Mbps support, WICED SDK9
Q316

CYBL1117x
CM0, DMA10, 2 SCB11, I2S
4 TCPWM12, 4 PWM, ADC,
36 GPIO, 256KB Flash,
32KB RAM, BT 4.2,
PSoC Creator
NEW

BCM20738
CM3, SPI, UART, I2C,
IR TX/RX, ADC, 4 PWM,
KB Scanner, Mouse QD,
40 GPIO, 60 KB RAM,
BT 4.0, ADK

Q316

Q316

Q316

CYBL1147x/57x
CM0, DMA, 2 SCB, I2S
2-Finger1, 4 TCPWM, 4 PWM,
ADC, 36 GPIO, 256KB Flash,
32KB RAM, BT 4.2,
PSoC Creator

CY8C41x8-BL5xx
CM0, DMA, 2 SCB, 4 Opamp,
2 CMP13, ADC, 4 TCPWM,
36 GPIO, 256KB Flash,
32KB RAM, BT 4.2,
PSoC Creator

CY8C42x8-BL5xx
CM0, DMA, 2 SCB, 4 Opamp,
2 CMP, 4 UDB14, ADC,
4 TCPWM, 36 GPIO,
256KB Flash, 32KB RAM,
BT 4.2, PSoC Creator

CYBL1057x
CM0, 2 SCB, I2S
2-Finger, 4 TCPWM,
4 PWM, ADC, 36 GPIO,
256KB Flash, 32KB RAM,
BT 4.1, PSoC Creator

CY8C41x8-BL4xx
CM0, 2 SCB, ADC, 4 Opamp,
2 CMP, 4 TCPWM, 36 GPIO,
256KB Flash, 32KB RAM,
BT 4.1, PSoC Creator

CY8C42x8-BL4xx
CM0, 2 SCB, ADC, 4 Opamp,
2 CMP, 4 UDB, 4 TCPWM,
36 GPIO, 256KB Flash,
32KB RAM, BT 4.1,
PSoC Creator

CYBL1046x/57x
CM0, 2 SCB, I2S, 2-Finger,
4 TCPWM, 4 PWM, ADC,
36 GPIO, 256KB Flash,
32KB RAM, BT 4.2,
PSoC Creator

CY8C41x7-BL4xx
CM0, 2 SCB, ADC, 4 Opamp,
2 CMP, 4 TCPWM, 36 GPIO,
128KB Flash, 16KB RAM,
BT 4.1, PSoC Creator

CY8C42x7-BL4xx
CM0, 2 SCB, ADC, 4 Opamp,
2 CMP, 4 UDB, 4 TCPWM,
36 GPIO, 128KB Flash,
16KB RAM, BT 4.1,
PSoC Creator

NEW

BCM20737
CM3, SPI, UART, I2C,
IR TX/RX, ADC, 4 PWM,
LE Audio, NFC15, Crypto,
14 GPIO, 60KB RAM,
BT 4.1, WICED SDK

NEW

NEW

BCM20732
CM3, SPI, UART, I2C,
IR TX/RX, ADC, 4 PWM,
14 GPIO, 60KB RAM, BT 4.0,
WICED SDK

BCM20736
CM3, SPI, UART, I2C,
IR TX/RX, ADC, A4WP16,
4 PWM, 40 GPIO, 60KB RAM,
BT4.1, WICED SDK

CYBL1016x
CM0, 2 SCB, I2S, 4 TCPWM,
4 PWM, ADC, 36 GPIO,
128KB Flash, 16KB RAM,
BT 4.2, PSoC Creator

Integration and Flexibility


1

Touch-sensing technology with up to 2-finger


gestures
2 ARM Cortex-M0/M0+/M3/M4
3 Broadcom serial communications block
4 Infrared transmit and receive
5 Keyboard scanner
6 Mouse quadrature decoder

Document No. 001-89435 Rev. *L

13

14

Cryptographic accelerator block for security


Bluetooth Specification
9 Software development kit
10 Direct memory access
11 Serial communication block
(SPI/I2C/UART)
12 Timer/Counter/PWM

Comparator
Universal digital block
15 Out-of-Band pairing with NFC
16 Alliance for Wireless Power BLE
Profile

Concept

Development

Sampling

Production

QQYY

QQYY

Status

Availability

56

BCM20737
Bluetooth Low Energy Connectivity MCU with Security and Wireless Charging
Block Diagram

Wearables, medical, home automation, toys

MCU Subsystem

Industrys Most-Widely-Deployed BLE Stack


Bluetooth Low Energy (BLE) Features
Bluetooth 4.1 compliant
Simultaneous multiple Master and Slave (1M, 3S)
Alliance for Wireless Charging (A4WP) support
Proprietary low-energy audio (LE Audio) support
Out-of-band (OOB) pairing using near-field communication (NFC)
Secure over-the-air (OTA) firmware upgrade
Security Engine
RSA, X.509, SHA, AES128
Packages
32-pin QFN (5 x 5 mm), 80-ball WLCSP (2.2 x 2.2 mm)
FCC and CE-certified 6.5 x 6.5 x 1.2-mm modules with antenna
WICED SMART SDK 2.1 (and later)

Collateral

16-bit
DelSig
ADC1

Cortex-M3
24 MHz
SRAM
(60KB)
ROM (320KB)

Communication
Interfaces

BLE Stack

Security Engine
Profiles
A4WP

I/O Subsystem

GPIO x14

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

Master

NFC
LE Audio

SPI

BLE System
(Bluetooth 4.1)
JTAG Debug

BCM20737
WICED SMART SDK
WICED SMART SDK 2.x and
BCM92073x_LE_TAG4

Availability
Production:

1 Effective

Analog Peripheral

System Bus

Features

Datasheet:
Software:
Quick Start Guide:

BLE Connectivity MCU

I/O Ring Bus

Applications

Now

number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

57

BCM20736
Bluetooth Low Energy Connectivity MCU with Wireless Charging

Features
Industrys Most-Widely-Deployed BLE Stack
Bluetooth Low Energy (BLE) Features
Bluetooth 4.1 compliant
Support for all standard Bluetooth 4.1 low energy profiles including
Alliance for Wireless Charging (A4WP)
Simultaneous multiple Master and Slave (1M, 1S)
Pre-standard BLE mesh
Over-the-air (OTA) firmware upgrade
Packages
32-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)
FCC and CE-certified 6.5 x 6.5 x 1.2-mm modules with antenna

BLE Connectivity MCU


MCU Subsystem

Analog Peripheral
16-bit
DelSig
ADC1

Cortex-M3
24 MHz
SRAM
(60KB)
ROM (320KB)

Communication
Interfaces

BLE Stack

Profiles
A4WP

I/O Subsystem

I/O Ring Bus

Beacons, tags, toys, industrial/home automation

Block Diagram

System Bus

Applications

GPIO x40

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

Master

SPI

WICED SMART SDK 2.1 (and later)

Collateral
Datasheet:
BCM20736
Software:
WICED SMART SDK
Quick Start Guide: WICED SMART SDK 2.x and
BCM92073x_LE_TAG4

BLE System
(Bluetooth 4.1)
JTAG Debug

Availability
Production:

1 Effective

Now

number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

58

BCM20738
Bluetooth Low Energy Connectivity MCU

Human interface device (HID), remote control, game controller,


remote sensor

Block Diagram
BLE Connectivity MCU
MCU Subsystem

Analog Peripheral

Features

Bluetooth Low Energy (BLE) Features


Bluetooth 4.0 compliant
LE HID (HoGP1)
Simultaneous multiple Master and Slave (1M, 1S)
Over-the-air (OTA) firmware upgrade
HID-Specific Peripherals
8x20 keyboard scanner
3-axis quadrature decoder for mice/joysticks
40 GPIOs
Packages
40-pin QFN (6 x 6 mm)
80-ball BGA (7 x 7 mm)
HID Application Development Kit (ADK)

24 MHz
SRAM
(60KB)
ROM (320KB)

Communication
Interfaces

BLE Stack

Profiles

System Bus

Industrys Most-Widely-Deployed BLE Stack

16-bit
DelSig
ADC2

Cortex-M3

GPIO x40

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

Master

SPI
BLE System
(Bluetooth 4.0)

I/O Subsystem

I/O Ring Bus

Applications

Keyboard
Scanner

Quad Decoder

JTAG Debug

Collateral
Datasheet:
Software:

BCM20738
HID ADK (Contact Sales)

Availability
Production:

1
2

Now

HID-over-GATT profile
Effective number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

59

BCM20732
Bluetooth Low Energy Connectivity MCU

Proximity and asset tracking, beacons, tags, remote sensor,


cable replacement

Block Diagram
BLE Connectivity MCU
MCU Subsystem

Analog Peripheral

Features

Bluetooth Low Energy (BLE) Features


Bluetooth 4.0 compliant
Entry-level, single connection BLE
Over-the-air (OTA) firmware upgrade

24 MHz
SRAM
(60KB)
ROM (320KB)
BLE Stack

Packages
32-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)
FCC and CE-certified 6.5 x 6.5 x 1.2-mm modules with antenna

Profiles

BLE System
(Bluetooth 4.0)

Digital Peripherals

UART x2
PWM x4
Master

SPI

Collateral

GPIO x14

IR RX/TX

I2C/SPI

WICED SMART SDK 1.x

Datasheet:
BCM20732 (Contact Sales)
Software:
WICED SMART SDK
Quick Start Guide: WICED SMART SDK 1.x and
BCM920732_BLE_KIT

Communication
Interfaces

System Bus

Industrys Most-Widely-Deployed BLE Stack

16-bit
DelSig
ADC1

Cortex-M3

I/O Subsystem

I/O Ring Bus

Applications

Keyboard
Scanner

Quad Decoder

JTAG Debug

Availability
Production:

1 Effective

Now

number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

60

BCM20719
Ultra Low Power Bluetooth Smart Ready Connectivity Secure MCU
Applications
Medical, home automation, wearables, POS

Block Diagram
BLE Connectivity MCU
MCU Subsystem

Analog Peripheral

I/O Subsystem

Bluetooth Low Energy (BLE) Features


Bluetooth 4.2-compliance with LE privacy 1.2, LE data length
extension, LE secure connections
Industrys lowest-power radio
Proprietary low energy audio (LE Audio) support
2-Mbps proprietary BLE support
ARM Cortex-M4 CPU with Floating-Point Unit, Digital-Signal
Processing Logic and 1MB Flash
MIPI-Compliant Display Driver
Security Engine
Public key accelerator (PKA), SHA, AES, RSA, Elliptic Curve
Diffie Hellman (ECDH)
Packages
40-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)

16-bit
DelSig
ADC1

Cortex-M4
96 MHz
SRAM
(512KB)
Flash
(1MB)
ROM
(2MB)
BR/BLE Stack
Profiles
BR/BLE/2-Mbps
Subsystem
(Bluetooth 4.2)
JTAG Debug
32-kHz/128-kHz
On-Chip OSC

Advanced High-Performance Bus (AHB)

Industrys Most-Widely-Deployed Bluetooth Stack

I/O Ring Bus

Features

TRIAC Control
x4
Communication
Interfaces

GPIO x40

Digital Peripherals

IR RX/TX

UART x2

PWM x6
I2C/SPI Master

Keyboard
Scanner

SPI/Dual SPI/
Quad SPI/MIPI

Quad Decoder

Security Engine

PKA

SHA

AES

WICED SMART Ready SDK

Collateral
Datasheet:
Software:
1 Effective

Availability
BCM20719 (Contact Sales)
WICED SMART Ready SDK (Contact Sales)

Sampling:
Production:

Q416
Q117

number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

61

PSoC 4 BLE (CY8C4xxx-BL)


Programmable System-on-Chip with Bluetooth Low Energy
Block Diagram

Features
32-bit MCU subsystem
ARM Cortex-M0 with DMA, 256KB flash and 32KB SRAM
Programmable Analog Front End
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR ADC
CapSense with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller with
touchpad capability
Programmable Digital Logic
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable TCPWM1 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs)2
I2C master or slave, SPI master or slave, or UART
Packages
56-pin QFN, 68/76-ball CSP and thin CSP3
Bluetooth Smart Connectivity with Bluetooth 4.2
2.4-GHz BLE radio with integrated balun

Collateral

modulator
Serial communication block configurable as I2C/SPI/UART

Document No. 001-89435 Rev. *L

MCU Subsystem

Programmable Analog
Blocks

Cortex-M0
48 MHz

BLE System
(Bluetooth 4.2)

Flash
(256KB)
SRAM
(32KB)

DMA

Opamp
x4

SAR
ADC

CMP
x2

CSD

Programmable Digital
Blocks

UDB x4

TCPWM x4

SCB x2

I/O Subsystem
GPIO x8

GPIO x8

GPIO x8

GPIO x8

Segment LCD Drive


Serial Wire Debug
GPIO x4

Availability

Datasheet:
CY8C4xxx-BL
Software:
PSoC Creator IDE
Application Note: Getting Started With PSoC 4 BLE
1 Timer/Counter/Pulse-Width

PSoC 4 BLE One-Chip Solution

Programmable Interconnect and Routing

Sports and fitness monitors, wearable electronics, medical devices,


home automation solutions, game controllers, sensor-based
low-power systems for IoT

Advanced High-Performance Bus (AHB)

Applications

Sampling:
Production:

128KB
Now
Now

256KB
Now
Now

256KB with BLE 4.2


Now
Q316

A thinner CSP package, 0.38 mm thick as compared to 0.55 mm for a regular CSP package

62

PRoC BLE (CYBL1x1x/4x/5xx)


Programmable Radio-on-Chip with Bluetooth Low Energy
Block Diagram

Features
32-bit MCU subsystem
ARM Cortex-M0 with DMA, 256KB flash and 32KB SRAM
with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller with
touchpad capability
CapSense

Analog and Digital Peripherals


One 12-bit, 1-Msps SAR ADC
Four configurable TCPWM1 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs)2
I2C master or slave, SPI master or slave, or UART
Dedicated I2S Tx/Rx interface
Up to four additional PWMs
Packages
56-pin QFN, 68/76-ball CSP and thin CSP3

PRoC BLE One-Chip Solution


MCU Subsystem

Analog Peripheral

I/O Subsystem
GPIO x8

SAR
ADC

CORTEX-M0
48 MHz

BLE System
(Bluetooth 4.2)

Flash
(256KB)
SRAM
(32KB)

DMA

CSD

Digital Peripherals

I2S

TCPWM x4

SCB x2

Programmable Interconnect and Routing

BLE connectivity, wireless touch mice, wireless keyboards


with trackpads, wireless trackpads, wireless remote control
with trackpads, wireless toys

Advanced High-Performance Bus (AHB)

Applications

GPIO x4

Availability

Datasheet:
CYBL1x1x/4x/5xx
Software:
PSoC Creator IDE
Application Note: Getting Started With PRoC BLE
Counter, Pulse-Width Modulator
Serial communication block configurable as I2C/SPI/UART

Document No. 001-89435 Rev. *L

GPIO x8

Segment LCD Drive

Collateral

GPIO x8

Serial Wire Debug

Bluetooth Smart Connectivity With Bluetooth 4.2


2.4-GHz BLE radio with integrated Balun

1 Timer,

GPIO x8

Sampling:
Production:
3

128KB
Now
Now

256KB
Now
Now

256KB with BLE 4.2


Now
Q316

A thinner CSP package, 0.38 mm thick as compared to 0.55 mm for a regular CSP package

63

Wireless Solutions for The Internet of Things (IoT)


Roadmap

Bluetooth classic + BLE PORTFOLIO

Document No. 001-89435 Rev. *L

64

Bluetooth Classic + BLE Portfolio


BR1 +BLE

BR + EDR2

BR + EDR + BLE3

NEW

Q416
BCM20735
48-MHz CM44, 2 SPI (Quad/Dual),
UART, I2C, IR TX/RX5, ADC,
6 PWM, KB Scanner6, Mouse QD7,
GCI8, 4 TRIAC Control,
40 GPIO, 384KB RAM,
BT9 4.2 + BLE + 2 Mbps, C1/C2/C310,
WICED SMART READY

Q416
NEW
BCM207x9
ULP11, 48-MHz CM4, 2 SPI (Quad/Dual),
UART, I2C, IR TX/RX, ADC,
6 PWM, KB Scanner, Mouse QD,
GCI, Crypto12, 4 TRIAC Control,
40 GPIO, 1MB Flash, 512KB RAM,
BT 4.2 + BLE + 2 Mbps, C2/C3,
WICED SMART READY

CPU Performance

NEW

NEW

BCM20707
96-MHz CM3, 2 SPI, UART, I2C,
GCI, 4 PWM, I2S/PCM,
24 GPIO, 352KB RAM,
BT 4.1 + EDR + BLE, C1/C2
WICED SMART READY
NEW

NEW

NEW

BCM20706
96-MHz CM3 Embedded BT SoC,
2 SPI, UART, I2C, IR TX/RX,
ADC, 4 PWM, GCI, I2S/PCM, 4 TRIAC
Control, 24 GPIO, 352KB RAM,
BT 4.1 + EDR + BLE, C1/C2
WICED SMART READY

BCM20704
96-MHz CM3, UART, I2C,
USB 2.0, I2S/PCM, GCI
8 GPIO, 352KB RAM,
BT 4.1 + EDR + BLE, C1/C2
HCI-Over-UART/USB 2.0

BCM20730
24-MHz CM3, 2 SPI, UART, I2C,
IR TX/RX, ADC, 4 PWM, KB Scanner,
Mouse QD, 4 TRIAC Control, 3D Glass,
40 GPIO, 60KB RAM,
BT 3.0, C2/C3, ADK

BCM20734
96-MHz CM3, 2 SPI, UART, I2C, GCI,
IR TX/RX, ADC, 4 PWM, KB Scanner,
Mouse QD, I2S/PCM, 4 TRIAC Control,
3D Glass13, 40 GPIO, 352KB RAM,
BT 4.1 + EDR + BLE, C1/C2, ADK14

NEW

BCM20733
24 MHz-ARM7TDMI-S15, 2 SPI,
UART, I2C, ADC, IR TX/RX, 4 PWM,
KB Scanner, Mouse QD, I2S/PCM,
4 TRIAC Control, 3D Glass,
CDAA16, 58 GPIO, 80KB RAM,
BT 3.0 + EDR, C1/C2/C3, ADK

Integration
1

13

2 Enhanced

14

Basic Rate
data rate
3 Bluetooth Low Energy
4 ARM Cortex-M3/M4
5 Infrared transmit and receive
6 Keyboard scanner

Document No. 001-89435 Rev. *L

Mouse quadrature decoder


Global coexistence interface
9 Bluetooth Specification 3.0/4/1/4.2
10 Class 1 (100 m)/2 (10 m)/3 (1 m)
11 Ultra-low power
12 Cryptographic accelerator block for security

3D Glass shutter control


Application Development Kit
15 ARM 7 Family CPU
16 Class-D Audio Amplifier

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

65

BCM20733
Bluetooth Connectivity MCU

Features
Industrys Most-Widely-Deployed Bluetooth Stack
Bluetooth Features
Basic rate Bluetooth 3.0 stack
Ideal for HID/trackpad applications
HID-Specific Peripherals
Two, independent, half-duplex PCM/I2S interfaces
Integrated 200-mW, filter-less, class-D audio amplifier (CDAA)
Dedicated GPIO for sinking up to 100 mA current
8x20 keyboard scanner, 3-axis quadrature decoder
40 GPIO
Packages
56-pin QFN (7 x 7 mm)
81-ball FBGA (8 x 8 mm)
121-ball FBGA (9 x 9 mm)

HID Application Development Kit (ADK)

Collateral
Datasheet: BCM20733 (Contact Sales)
Software: HID ADK (Contact Sales)

Bluetooth Connectivity MCU


MCU Subsystem

16-bit
DelSig
ADC1

CDAA

Cortex-M3
24 MHz

TRIAC Control
x4

SRAM
(60KB)
ROM (320KB)

Communication
Interfaces

Bluetooth Stack

Profiles

I/O Subsystem

GPIO x40

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

Master

SPI

Keyboard
Scanner

Bluetooth System
(Bluetooth 3.0)

Quad Decoder

JTAG Debug

3D Glass

Availability
Production:

Analog Peripheral

I/O Ring Bus

Human-interface devices (HID), joysticks, remote controls

Block Diagram

System Bus

Applications

Now

Effective number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

66

BCM20730
Bluetooth Connectivity MCU
Applications
Human-interface-devices (HID) and 3D-glasses

Block Diagram
Bluetooth Connectivity MCU
MCU Subsystem

Analog Peripheral

I/O Subsystem

Bluetooth Features
Bluetooth 3.0 stack with basic rate
Optimized low-power sniff mode
Small form factor solution
Application Specific Peripherals
Two independent half-duplex PCM/I2S interfaces
8x20 keyboard scanner, 3-axis quadrature decoder
3D-glass shutter-control
40 GPIO
Packages
32-pin QFN (5 x 5 mm)
40-pin QFN (6 x 6 mm),
64-pin BGA (7 x 7 mm)
HID Application Development Kit (ADK)

16-bit
DelSig
ADC1

ARM7TDMI-S
24 MHz

TRIAC Control
x4

SRAM
(80KB)
ROM (384KB)

Communication
Interfaces

Bluetooth Stack

Profiles

System Bus

Industrys Most-Widely-Deployed Bluetooth Stack

Digital Peripherals

UART x2
PWM x4
Master

SPI

JTAG Debug

GPIO x40

IR RX/TX

I2C/SPI

Bluetooth System
(Bluetooth 3.0)

I/O Ring Bus

Features

I2S/PCM

Keyboard
Scanner

Quad Decoder

3D Glass

Collateral
Datasheet: BCM20730
Software: HID ADK (Contact Sales)

Availability
Production:

1 Effective

Now

number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

67

BCM20707
Bluetooth Connectivity MCU
Block Diagram

HCI-based Bluetooth and dongles

Bluetooth Connectivity MCU


MCU Subsystem

Analog Peripheral

Features

Bluetooth Features
Bluetooth 4.1 + high-speed stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
Global coexistence interface (GCI)
Wideband speech (16K) support
Up to 16 LE connections
Host controller interface (HCI) over UART

Application Specific Peripherals


Two independent half-duplex PCM/I2S interfaces

96 MHz

Bluetooth Stack

Profiles

GPIO x40

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

GCI

Collateral

Communication
Interfaces

ROM (848KB)

Package
49-pin FBGA (4.5 x 4.0 mm)
WICED SMART READY SDK

TRIAC Control
x4

SRAM
(352KB)

System Bus

Industrys Most-Widely-Deployed Bluetooth Stack

16-bit
DelSig
ADC4

Cortex-M3

I/O Subsystem

I/O Ring Bus

Applications

Master

SPI

Bluetooth System
(Bluetooth 4.1)

I2S/PCM

JTAG Debug

Datasheet: BCM20707
Software: WICED SMART READY SDK (Contact Sales)

Availability
Production:
1 Basic

Rate
Enhanced Data Rate

Document No. 001-89435 Rev. *L

Now

Bluetooth Low Energy


Effective number of bits is 10 at 187 ksps

68

BCM20704
Bluetooth Connectivity MCU
Applications
HCI-based Bluetooth and dongles

Block Diagram
Bluetooth Connectivity MCU
MCU Subsystem

I/O Subsystem

Bluetooth Features
Bluetooth 4.1 + high-speed stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
Global coexistence interface (GCI)
Host controller interface (HCI) over UART and USB

Cortex-M3
96 MHz
SRAM
(352KB)

Bluetooth Stack

Package
49-pin FCBGA (4.5 x 4.0 mm)
WICED SMART READY SDK

Profiles

GPIO x8

Communication
Interfaces

ROM (848KB)

System Bus

Industrys Most-Widely-Deployed Bluetooth Stack

I/O Ring Bus

Features

UART x2

I2C/SPI Master

Collateral
Datasheet: BCM20704
Software: WICED SMART READY SDK (Contact Sales)

GCI
I2S/PCM
Bluetooth System
(Bluetooth 4.1)
USB 2.0
JTAG Debug

Availability
Production:

Now

Basic Rate
Enhanced Data Rate
3 Bluetooth Low Energy
2

Document No. 001-89435 Rev. *L

69

BCM20706
Bluetooth Connectivity MCU
Applications

Block Diagram

Speaker/Headset, Bluetooth gateway, automation gateway

Bluetooth Connectivity MCU


MCU Subsystem

Analog Peripheral

I/O Subsystem

Industrys Most-Widely-Deployed Bluetooth Stack

16-bit
DelSig
ADC4

Cortex-M3
96 MHz

Package
49-pin FBGA (4.5 x 4.0 mm)

Communication
Interfaces

ROM (848KB)
Bluetooth Stack

Profiles

WICED SMART READY SDK


GCI

GPIO x24

Digital Peripherals
IR RX/TX

UART x2
PWM x4
I2C/SPI

Master

SPI

Collateral
Datasheet: BCM20706
Software: WICED SMART READY SDK (Contact Sales)

TRIAC Control
x4

SRAM
(352KB)

System Bus

Bluetooth Features
Hostless, complete system-on-chip with Bluetooth 4.1 stack with
BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
A2DP, AVRCP, SPP, GATT support
Global coexistence interface (GCI)

I/O Ring Bus

Features

Bluetooth System
(Bluetooth 4.1)

I2S/PCM

JTAG Debug

Availability
Production:
1 Basic

Rate
Enhanced Data Rate

Document No. 001-89435 Rev. *L

Now

Bluetooth Low Energy


Effective number of bits is 10 at 187 ksps

70

BCM20734
Bluetooth Connectivity MCU
Applications

Block Diagram

Remotes, game controllers, joysticks, POS input devices

Bluetooth Connectivity MCU


MCU Subsystem

Analog Peripheral

I/O Subsystem

Bluetooth Features
Bluetooth 4.1 stack with BR1/EDR2/BLE3
Class 1 (100 meters), Class 2 (10 meters) support
BLE HID profile, Bluetooth device ID profile 1.3
Global coexistence interface (GCI)
HID-Specific Peripherals
8x20 keyboard scanner
3-axis quadrature decoder for mice/joystick
I2S/PCM/PDM for audio use case
40 GPIO

96 MHz

Communication
Interfaces

ROM (848KB)
Bluetooth Stack

Profiles

JTAG Debug

Digital Peripherals

UART x2
PWM x4
Master

SPI

Bluetooth System
(Bluetooth 4.1)

GPIO x40

IR RX/TX

I2C/SPI
GCI

Collateral

TRIAC Control
x4

SRAM
(352KB)

Package
90-pin FBGA (8.5 x 8.5 mm)
HID Application Development Kit (ADK)

16-bit
DelSig
ADC4

Cortex-M3

System Bus

Industrys Most-Widely-Deployed Bluetooth Stack

I/O Ring Bus

Features

I2S/PCM/PDM

Keyboard
Scanner

Quad Decoder

3D Glass

Datasheet: BCM20734
Software: HID ADK (Contact Sales)

Availability
Production:
1 Basic

Rate
Enhanced Data Rate

Document No. 001-89435 Rev. *L

Now

Bluetooth Low Energy


Effective number of bits is 10 at 187 ksps

71

BCM20735
Bluetooth Smart and Basic Rate Connectivity MCU

Features
Industrys Most-Widely-Deployed Bluetooth Stack
Bluetooth Features
Bluetooth 4.2 stack with basic rate and Bluetooth Low Energy (BLE)
All new Bluetooth 4.2 features: LE privacy 1.2, LE data length
extension, LE secure connections
2-Mbps proprietary BLE support
Industrys lowest-power radio
Integrated power amplifier (up to 10 dBm)
ARM Cortex-M4 CPU With Floating-Point Unit (FPU) and
Digital-Signal Processing (DSP) Logic

BLE Connectivity MCU


MCU Subsystem

96 MHz
SRAM
(512KB)

Packages
60-pin QFN (7 x 7 mm)
111-ball FBGA (9 x 9 mm)
WICED SMART READY SDK

Collateral
Datasheet: BCM20735
Software: WICED SMART READY SDK (Contact Sales)
1

TRIAC Control
x4
Communication
Interfaces

ROM
(2MB)
BR/BLE Stack
Profiles
BR/BLE/2-Mbps
Subsystem
(Bluetooth 4.2)
JTAG Debug
32-kHz/128-kHz
On-Chip OSC

I/O Subsystem

16-bit
DelSig
ADC1

Cortex-M4

MIPI-Compliant Display Driver


Security Engine
PKA, SHA, AES

Analog Peripheral

I/O Ring Bus

Remote controls, BR-gateways

Block Diagram

AHB Bus

Applications

GPIO x40

Digital Peripherals

IR RX/TX

UART x2

PWM x6
I2C/SPI Master

Keyboard
Scanner

SPI/Dual SPI/
Quad SPI/MIPI

Quad Decoder

Security Engine

PKA

SHA

AES

Availability
Sampling:
Production:

Now
Q416

Effective number of bits is 10 at 187 ksps

Document No. 001-89435 Rev. *L

72

BCM207x9
Ultra Low Power Multi-Protocol Connectivity MCU
Applications

Block Diagram

Medical, home automation, wearables, POS input devices

Multi-Protocol Connectivity MCU


MCU Subsystem

Analog Peripheral

Industrys Most-Widely-Deployed Bluetooth Stack

16-bit
DelSig
ADC5

Cortex-M4
SRAM
(512KB)

Cortex-M4

CPU With Floating-Point Unit (FPU),


Digital-Signal Processing (DSP) Logic and 1MB Flash

TRIAC Control
x4

Flash
(1MB)

Communication
Interfaces

ROM
(2MB)
BR/BLE/ZigBee/Th
read Stack

802.15.4 ZigBee and Thread Support


ARM

96 MHz

AHB Bus

Bluetooth Features
Industrys lowest power Bluetooth radio
Bluetooth 4.2 stack with BR1/EDR2/BLE3
All new, Bluetooth 4.2 features: LE privacy 1.2, LE data length
extension, LE secure connections
2-Mbps proprietary BLE support
LE audio

Profiles
802.15.4/BR/BLE/
2-Mbps Subsystem
(Bluetooth 4.2)

MIPI-Compliant Display Driver


Security Engine
PKA, SHA, AES, RSA, ECDH4

JTAG Debug

Packages
40-pin QFN (5 x 5 mm)
80-ball WLCSP (2.2 x 2.2 mm)

I/O Subsystem

I/O Ring Bus

Features

32-kHz/128-kHz
On-Chip OSC

GPIO x40

Digital Peripherals

IR RX/TX

UART x2

PWM x6
I2C/SPI Master

Keyboard
Scanner

SPI/Dual SPI/
Quad SPI/MIPI

Quad Decoder

Security Engine

PKA

SHA

AES

WICED SMART READY SDK

Availability

Collateral
Datasheet: BCM207x9 (Contact Sales)
Software: WICED SMART READY SDK (Contact Sales)
1 Basic

Rate
Enhanced Data Rate

Document No. 001-89435 Rev. *L

Bluetooth Low Energy


Elliptic-Curve Diffie Hellman

Sampling:
Production:
5

BCM20719
Q416
Q117

BCM20729
Q117

BCM20739
Q117

Effective number of bits is 10 at 187 ksps

73

Wireless Solutions for The Internet of Things (IoT)


Roadmap

Wi-Fi PORTFOLIO

Document No. 001-89435 Rev. *L

74

Wi-Fi Portfolio
IEEE 802.11a/b/g/n WLAN1

NEW

Q316
BCM43909
Up to 150 Mbps, 802.11a/b/g/n, SISO7, 320-MHz CR48,
GCI SECI9, Security, CCX, DDR3/3L I/F10,
Ethernet (RMII/MII), 6 PWM, SDIO 3.0 (H/D),
USB 2.0 + HSIC (H/D), S/PDIF, 3 UART, Quad SPI, 2 SPI,
2 I2S, 2 I2C, 17 GPIO, Integrated PA for both bands
WICED
NEW

BCM43907
Up to 150 Mbps, 802.11a/b/g/n, SISO, 320-MHz CR4,
GCI SECI, Security, CCX, 6 PWMs, Ethernet (RMII/MII),
SDIO 3.0 (H/D), USB 2.0 + HSIC (H/D),
S/PDIF, 3 UART, Quad SPI, 2 SPI, 2 I2S, 2 I2C
17 GPIO, Integrated PA for both bands
WICED

BCM43243
Up to 300 Mbps, 802.11a/b/g/n,
2x2 MIMO, Security, CCX
USB2.0
13 GPIO, Integrated PA for both bands
Linux Driver

NEW

Single Band
(2.4 GHz)

NEW

BCM43236B
Up to 300 Mbps, 802.11a/b/g/n,
2x2 MIMO2, SECI3, Security4, CCX5,
USB 2.0 + HSIC, SPI,
8 GPIO, Integrated PA6 for both bands
Linux Driver

NEW

NEW

Data Rate

Dual Band
(2.4/5 GHz)

NEW

IEEE 802.11a/b/g/n WLAN + MCU

BCM43143
Up to 150 Mbps, 802.11b/g/n, SISO
GCI SECI, Security,
SDIO 2.0, USB 2.0, I2C/SPI
19 GPIO, Integrated PA
Linux Driver
NEW

BCM43364
Up to 96 Mbps, 802.11b/g/n, SISO
GCI SECI, Security, CCX
SDIO 2.0, SPI,
5 GPIO, Integrated PA
Linux Driver, WICED

NEW

BCM43362
Up to 72 Mbps, 802.11b/g/n, SISO
SECI, Security,
SDIO 2.0, SPI,
5 GPIO, Integrated PA
Linux Driver, WICED

5 Cisco

6 Power

10

Wireless Local Area Network


Multiple-input multiple-output
3 Serial enhanced coexistence interface
4 WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Compatible Extensions
amplifier
7 Single-input single-output
8 ARM Cortex-M3/R4

BCM43903
Up to 72 Mbps, 802.11b/g/n, SISO,
160-MHz CR4, GCI SECI, Security, CCX,
6 PWMs, 3 UART, Quad SPI, 2 SPI, 2 I2C
17 GPIO, Integrated PA
WICED
BCM4390
Up to 72 Mbps, 802.11b/g/n, SISO,
48-MHz CM3, GCI, Security, CCX,
6 PWMs, 4 UART, I2S, 2 SPI, I2C
24 GPIO, Integrated PA
WICED

Global coexistence interface


Double data rate type
three/-L memory interface

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

75

BCM43362
Single-Chip IEEE 802.11n MAC/Baseband/Radio + SDIO Connectivity Solution
Applications
Consumer and commercial internet-of-things (IoT),
sensors and control

Block Diagram
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem

Wi-Fi Subsystem

Features

I/O Ring Bus

MAC

Industrys Most-Widely-Deployed Wi-Fi IP

Security Engine1
WPA and WPA2
AES in hardware
Packages
69-ball WLBGA (4.52 x 2.92 mm)
WICED Wi-Fi SDK, Linux Driver

Collateral
Datasheet:
Software:

PHY

Radio
Communication
Interfaces
Security Engine

ARM

Cortex-M3

UART

SPI
SRAM
(240KB)
ROM
(448KB)

SDIO

SECI

JTAG Debug

BCM43362
WICED Wi-Fi SDK
Linux Driver

Availability
Production:

System Bus

Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and SPI support
3-/4-wire serial enhanced coexistence interface (SECI)

GPIO x5

Now

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

76

BCM43364
Single-Chip IEEE 802.11n MAC/Baseband/Radio
Applications

Block Diagram

Low-cost WLAN connectivity for consumer/commercial IoT

Single-Chip Wi-Fi Connectivity Solution

Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

PHY

Communication
Interfaces
Security Engine

ARM

Cortex-M3

UART

SPI
SRAM
(512KB)

Packages
74-ball WLBGA (4.87 x 2.87 mm)

ROM
(640KB)

WICED Wi-Fi SDK, Linux Driver

SDIO

GCI SECI

JTAG Debug

Collateral
BCM43364
WICED Wi-Fi SDK
Linux Driver

Availability
Production:

GPIO x5

Radio

System Bus

Wi-Fi Features
802.11b/g/n compliant
96-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and SPI support
2-/3-/4-wire global coexistence interface (GCI) SECI1

I/O Ring Bus

MAC

Industrys Most-Widely-Deployed Wi-Fi IP

Datasheet:
Software:

I/O Subsystem

Wi-Fi Subsystem

Features

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

77

BCM43143
Single-Chip IEEE 802.11n MAC/Baseband/Radio + SDIO/USB Connectivity Solution
Applications

Block Diagram

Consumer electronics, printers

Single-Chip Wi-Fi Connectivity Solution

Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

PHY

GPIO x19

Radio
Communication
Interfaces
Security Engine

ARM Cortex-M3

System Bus

Wi-Fi Features
802.11b/g/n compliant
150-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and USB 2.0 support
2-/3-/4-wire global coexistence interface (GCI) SECI1

I/O Ring Bus

MAC

Industrys Most-Widely-Deployed Wi-Fi IP

UART

USB2.0
SRAM
(256KB)

Packages
56-pin QFN (7 x 7 mm)

SDIO
ROM
(448KB)

Linux Driver

Collateral
Datasheet:
Software:

I/O Subsystem

Wi-Fi Subsystem

Features

JTAG Debug

GCI SECI
I2C/SPI

BCM43143
Linux Driver

Availability
Production:

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

78

BCM43243
Single-Chip IEEE 802.11n MAC/Baseband/Radio + USB Connectivity
Applications
Consumer electronics, wireless media applications

Block Diagram
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem

Wi-Fi Subsystem

Features
I/O Ring Bus

MAC

Industrys Most-Widely-Deployed Wi-Fi IP


PHY

2x2 Dual-Band
Radio

Security Engine

Engine1

Security
WPA and WPA2
AES in hardware
Cisco Compatible Extensions
Packages
FCFBGA (10 x 10 mm)
Linux Driver

Communication
Interfaces

USB 2.0
SRAM
(512KB)
ROM
(640KB)

JTAG Debug

Collateral
Datasheet:
Software:

ARM Cortex-M3

GPIO x13

System Bus

Wi-Fi Features
802.11a/b/g/n compliant
300-Mbps data rate
Dual band (2.4/5 GHz)
2x2 Multiple-input multiple-output (MIMO)
USB 2.0 support

BCM43243
Linux Driver

Availability
Production:

Now

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

79

BCM43236/BCM43236B
Single-Chip IEEE 802.11n MAC/Baseband/Radio + USB Connectivity
Applications
USB 2.0 dongles, HSIC media modules

Block Diagram
Single-Chip Wi-Fi Connectivity Solution
I/O Subsystem

Wi-Fi Subsystem

Wi-Fi Features
802.11a/b/g/n compliant
300-Mbps data rate
Dual band (2.4/5 GHz)
2x2 Multiple-input multiple-output (MIMO)
USB 2.0 support
5-wire legacy serial enhanced coexistence interface (SECI)
Security Engine1
WPA and WPA2
AES in hardware
Cisco Compatible Extensions
Packages
88-pin QFN (10 x 10 mm)

MAC

I/O Ring Bus

Industrys Most-Widely-Deployed Wi-Fi IP

PHY

2x2 Dual-Band
Radio

Security Engine

ARM Cortex-M3

GPIO x8

Communication
Interfaces

System Bus

Features

USB 2.0/HSIC
SRAM
(512KB)
ROM
(640KB)

Linux Driver
JTAG Debug

5-Wire Legacy
SECI
SPI

Collateral
Datasheet:
Software:

BCM43236/BCM43236B
Linux Driver

Availability
Production:

Now

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

80

BCM4390
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications

Block Diagram

Consumer, home automation, health, smart energy

Single-Chip Wi-Fi Connectivity Solution


Wi-Fi Subsystem

Features

MAC

Industrys Most-Widely-Deployed Wi-Fi IP

GPIO x24

PHY

Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

AXI

SRAM
(1MB)

Radio

Digital
Peripherals

ROM
(610KB)
Security Engine

AXI

32-bit ARM Cortex-M3 Application MCU Subsystem

I/O Subsystem

Cortex-M3
48 MHz

Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1

ARM

JTAG Debug

PWM x6

Cortex-M3
Communication Interfaces

SRAM
(256KB)

Packages
286-ball WLCSP (4.87 x 5.413 mm)

ROM
(448KB)

WICED Wi-Fi SDK

UART x4

GCISECI

SPI x2

I2C x2

JTAG Debug

Collateral
Datasheet:
Software:

Application MCU Subsystem

BCM4390
WICED Wi-Fi SDK

Availability
Production:

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

81

BCM43907
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications

Block Diagram

Appliances, HID, embedded audio, health/medical

Single-Chip Wi-Fi Connectivity Solution


Wi-Fi Subsystem

Features

Application MCU Subsystem

MAC

GPIO x17

Industrys Most-Widely-Deployed Wi-Fi IP


PHY

SRAM
(1MB)

2.4/5-GHz
Dual-Band Radio

Ethernet (RMII/MII)

Digital
Peripherals

ROM
(610KB)

Security Engine

AXI

32-bit ARM Cortex-R4 Application MCU Subsystem

Cortex-R4
320 MHz

AXI

Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1

I/O Subsystem

JTAG Debug

PWM x6

ARM Cortex-R4
(160 MHz)

Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

Communication Interfaces
SRAM
(2MB)

Packages
316-ball WLCSP (4.58 x 5.53 mm)
WICED Wi-Fi SDK

UART x3

GCI SECI

Ethernet
(RMII/MII)

ROM
(640KB)

SPI x2

I2C x2

USB 2.0
HSIC

JTAG Debug

Quad SPI

SDIO 3.0

Collateral
Datasheet:
Software:

Availability

BCM43907
WICED Wi-Fi SDK

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

Production:

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

82

BCM43909
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications

Block Diagram

Appliances, HID devices, embedded audio, health/medical

Single-Chip Wi-Fi Connectivity Solution


Wi-Fi Subsystem

Features

Application MCU Subsystem

MAC

GPIO x17

Industrys Most-Widely-Deployed Wi-Fi IP


PHY

SRAM
(1MB)

2.4/5-GHz
Dual-Band Radio

Ethernet (RMII/MII), DDR3/3L interface

Digital
Peripherals

ROM
(610KB)

Security Engine

AXI

32-bit ARM Cortex-R4 Application MCU Subsystem

Cortex-R4
320 MHz

AXI

Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1

I/O Subsystem

JTAG Debug

PWM x6

ARM Cortex-R4
(160 MHz)

Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

Communication Interfaces
SRAM
(2MB)

Packages
338-ball FCFBGA (10 x 10 mm)
WICED Wi-Fi SDK

UART x3

GCI SECI

Ethernet
(RMII/MII)

ROM
(640KB)

SPI x2

I2C x2

USB 2.0
HSIC

JTAG Debug

Quad SPI

SDIO 3.0

DDR3/3L
I/F

Collateral
Datasheet:
Software:

BCM43909
WICED Wi-Fi SDK

Availability
Production:

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

83

BCM43903
IEEE 802.11n System-on-Chip with Embedded Application Processor
Applications

Block Diagram

Consumer/home appliances, HID

Single-Chip Wi-Fi Connectivity Solution


Wi-Fi Subsystem

Application MCU Subsystem

I/O Subsystem

Features
MAC

Wi-Fi Features
802.11b/g/n compliant
72-Mbps data rate
Single band (2.4 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Security Engine2
WPA and WPA2
AES in hardware
Cisco Compatible Extensions

PHY

SRAM
(1MB)

Single-Band Radio

Digital
Peripherals

ROM
(610KB)
Security Engine1
JTAG Debug

PWM x6

ARM Cortex-R4
(160 MHz)
Communication Interfaces
SRAM
(1MB)

Packages
151-ball WLBGA (4.91 x 5.85 mm)
WICED Wi-Fi SDK

Collateral
Datasheet:
Software:

Cortex-R4
320 MHz

AXI

32-bit ARM Cortex-R4 Application MCU Subsystem

GPIO x17

AXI

Industrys Most-Widely-Deployed Wi-Fi IP

UART x3

GCI SECI

ROM
(640KB)

SPI x2

I2C x2

JTAG Debug

Quad SPI

SDIO 3.0

BCM43903
WICED Wi-Fi SDK

Availability
Production:

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

84

Wireless Solutions for The Internet of Things (IoT)


Roadmap

Wi-Fi + Bluetooth Combo PORTFOLIO

Document No. 001-89435 Rev. *L

85

Wi-Fi + Bluetooth Combo Portfolio


IEEE 802.11a/b/g/n WLAN1 +
Bluetooth (BR2 + EDR3 + BLE4)
Q117

Single-Band
(2.4 GHz)

Dual-Band
(2.4/5 GHz)

NEW

BCM43012
Up to 96 Mbps, ULP5, 802.11a/b/g/n,
BT6 5.0, SDIO 3.0, Security7, UART,
SPI, 2 PCM/I2S, 16 GPIOs
WICED

NEW

NEW

NEW

BCM4334
Up to 150 Mbps, 802.11a/b/g/n, BT 4.0,
SECI8, Security, SDIO 2.0, SPI,
HSIC, HCI-over-UART, 2 PCM/I2S,
FM RX, I2S for FM, 16 GPIOs,
Linux Driver

BCM43340
Up to 150 Mbps, 802.11a/b/g/n, BT 4.0,
SECI, Security, SDIO 2.0, SPI,
HSIC, HCI-over-UART, 2 PCM/I2S,
I2S/Stereo Audio for FM, 8 GPIOs,
Integrated PA,
Linux Driver, WICED

NEW

NEW

NEW

BCM43438/BCM4343W
Up to 96 Mbps, 802.11b/g/n, BT4.1,
A4WP, GCI SECI, Security, SDIO2.0,
SPI, HCI-over-UART, 2 PCM/I2S,
FM RX, PCM/Stereo Audio for FM,
5 GPIOs, Integrated PA,
Linux Driver, WICED

IEEE 802.11a/b/g/n/ac WLAN +


Bluetooth (BR + EDR + BLE)
BCM43455
Up to 433.3 Mbps, 802.11a/b/g/n/ac,
BT 4.1, A4WP9, GCI10 SECI,
Security, PCIe3.0, SDIO 2.0/3.0,
SPI, HCI-over-UART, PCM/I2S,
FM RX, 15 GPIOs, Integrated PA11,
Linux Driver

NEW

BCM43242
Up to 300 Mbps, 2x2 MIMO,
802.11a/b/g/n w/USB 2.0, Security,
BT 4.1 w/USB/UART, PCM/I2S,
16 GPIOs, Integrated PA,
Linux Driver

BCM4339
Up to 433.3 Mbps, 802.11a/b/g/n/ac,
BT4.1, A4WP, GCI SECI,
Security, SDIO2.0/3.0,
SPI, HCI-over-UART, PCM/I2S,
FM RX, 16 GPIOs, Integrated PA,
Linux Driver

NEW

BCM4356
Up to 867 Mbps, 2x2 MIMO12,
802.11a/b/g/n/ac w/PCIe, Security,
BT 4.1 w/UART, PCM/I2S,
16 GPIOs, Integrated PA,
Linux Driver
NEW

BCM4354
Up to 867 Mbps, 2x2 MIMO,
802.11a/b/g/n/ac w/SDIO, Security,
BT4.1 w/UART, PCM/I2S,
16 GPIOs, Integrated PA,
Linux Driver

BCM4334W
Up to 150 Mbps, 802.11b/g/n, BT4.0,
SECI, Security, SDIO2.0,
SPI, HSIC, HCI-over-UART,
2 PCM/I2S, 8 GPIOs,
Linux Driver

Data Rate

6 Bluetooth

10

Wireless Local Area Network


Basic Rate
3 Enhanced Data Rate
4 Bluetooth Low Energy

Document No. 001-89435 Rev. *L

Ultra-low power
Specification
7 WPA, WAPI STA, WPA2, AES, TKIP
8 Serial enhanced coexistence interface

11
12

Alliance for Wireless Power BLE Profile


Global coexistence interface
Status
Power amplifier
Availability
Multiple-in multiple-out

Concept

Development

Sampling

Production

QQYY

QQYY

86

BCM43438/BCM4343W
Single chip IEEE 802.11n with Integrated Bluetooth 4.1 and FM Receiver
Applications

Block Diagram
Single-Chip Wi-Fi and Bluetooth Connectivity Solution
Wi-Fi Subsystem

Features

Interfaces

MAC And PHY

Wi-Fi Features
802.11b/g/n compliant
96-Mbps data rate
Single band (2.4 GHz)
SDIO 2.0 and SPI support
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.0 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM Features
FM receiver

UART

Single-Band Radio
SPI

Security Engine2
ARM Cortex M3

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

I/O Subsystem

APB

Portable consumer/commercial IoT and wearables

GPIO x5

PCM/I2S x2

SRAM (512KB)
FM Subsystem
SDIO 2.0

ROM (640KB)

FM RX

JTAG/SWD
GCI2

SECI3
PCM/I2S
Stereo Audio

Bluetooth Subsystem
Bluetooth 4.1
Link Layer And PHY

Packages
63-ball WLBGA (4.87 x 2.87 mm)
74-ball WLBGA (4.87 x 2.87 mm)
153-ball WLCSP (4.87 x 2.87 mm)

SRAM (160KB)

AHB

ARM Cortex M3

ROM (576KB)
JTAG/SWD

WICED Wi-Fi SDK, Linux driver

Collateral
Datasheets:
Software:
1

Availability
BCM43438, BCM4343W
WICED Wi-Fi SDK
Linux Driver

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

Production:
2 WPA,

BCM43438
Now

BCM4343W
Now

WAPI STA, WPA2, AES, TKIP security features

87

BCM4334W
Single chip IEEE 802.11n with Integrated Bluetooth 4.0
Applications

Block Diagram

Portable consumer/commercial IoT, wearables

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Wi-Fi Subsystem

Interfaces

MAC And PHY

UART

Single-Band Radio

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

SPI

Wi-Fi Features
802.11b/g/n compliant
150-Mbps data rate,
Single band (2.4 GHz)
SDIO 2.0, SPI and HSIC support

ARM Cortex M3

PCM/I2S x2

SDIO 2.0

ROM (640KB)
JTAG/SWD

Legacy

SECI2

Bluetooth Subsystem
HSIC

Bluetooth 4.0
Link Layer And PHY

Packages
109-ball WLBGA (4.08 x 4.48mm)
208-ball WLCSP (4.08 x 4.48 mm)

Audio Subsystem

MP3
Encoder/Dec
oder
AAC
Decoder

SRAM (173KB)

AHB

ARM Cortex M3

Linux Driver

ROM (680KB)
JTAG/SWD

Collateral
BCM4334W
Linux Driver

Availability
Production:

GPIO x8

SRAM (512KB)

Bluetooth Features
Bluetooth 4.0 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

Datasheet:
Software:

AXI

Security Engine1

APB

Features

I/O Subsystem

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Now

Serial enhanced coexistence interface

88

BCM43340
Single chip IEEE 802.11n with Integrated Bluetooth 4.0 and FM Receiver
Applications

Block Diagram

Portable consumer/commercial IoT applications

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Wi-Fi Subsystem

Interfaces

MAC And PHY

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

I/O Subsystem

UART

Dual-Band Radio

Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
SDIO 2.0, SPI, HSIC support

SPI

ARM Cortex M3

AXI

Security Engine1

APB

Features

GPIO x8

PCM/I2S

SRAM (512KB)
FM Subsystem
SDIO 2.0

ROM (640KB)

Bluetooth Features
Bluetooth 4.0 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

FM RX

JTAG/SWD
Legacy

SECI2
PCM/I2S
Stereo Audio

Bluetooth Subsystem

FM Features
FM receiver

USB/HSIC

Bluetooth 4.0
Link Layer And PHY

SRAM (195KB)

WICED Wi-Fi SDK, Linux Driver

AHB

ARM Cortex M3

Package
141-ball WLBGA (5.67 x 4.47 mm)

ROM (652KB)
JTAG/SWD

Collateral
Datasheet:
Software:

BCM43340 (Contact Sales)


WICED Wi-Fi SDK
Linux Driver

Availability
Production:

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Now

Serial enhanced coexistence interface

89

BCM43242
Single-Chip IEEE 802.11n with Integrated Bluetooth 4.0 + HS
Applications

Block Diagram

Remote controls and sensors

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Wi-Fi Subsystem

Interfaces

MAC And PHY

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

UART

2x2 Dual-Band Radio

Wi-Fi Features
802.11a/b/g/n compliant
2x2 Multiple-input multiple-output (MIMO)
300-Mbps data rate
Dual band (2.4/5 GHz)

SPI

AXI

Security Engine1
ARM Cortex M3

I/O Subsystem

APB

Features

GPIO x16

PCM/I2S

SRAM (544KB)
5-Wire SECI2

ROM (640KB)

Bluetooth Features
Bluetooth 4.0 + High Speed compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

JTAG/SWD
USB
Bluetooth Subsystem
Bluetooth 4.0
Link Layer And PHY

Package
FCFBGA (10 x 10 mm)

SRAM (166KB)

AHB

ARM Cortex M3

Linux Driver

ROM (660KB)
JTAG/SWD

Collateral
Datasheet:
Software:

Availability
BCM43242
WICED Wi-Fi SDK
Linux Driver

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Production:

Now

Serial enhanced coexistence interface

90

BCM4334
Single chip IEEE 802.11n with Integrated Bluetooth 4.0 + HS and FM Receiver
Applications

Block Diagram

Portable consumer/commercial IoT applications

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Wi-Fi Subsystem
MAC And PHY

Wi-Fi Features
802.11a/b/g/n compliant
150-Mbps data rate
Dual band (2.4/5 GHz)
SDIO 2.0, SPI, HSIC support

Security Engine1
ARM Cortex M3

GPIO x16

PCM/I2S
FM Subsystem
SDIO 2.0

ROM (640KB)

FM RX

JTAG/SWD
5-Wire

SECI2
PCM/I2S

Bluetooth Subsystem
USB/HSIC

Bluetooth 4.0
Link Layer And PHY

FM Features
FM receiver

SRAM (173KB)

AHB

ARM Cortex M3

Packages
109-ball (4.08 x 4.48 mm)
208-ball WLCSP (4.08 x 4.48 mm)

ROM (680KB)

Linux Driver

JTAG/SWD

Collateral

SPI

SRAM (512KB)

Bluetooth Features
Bluetooth 4.0 + High Speed compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

Datasheet:
Software:

UART

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

Dual-Band Radio

I/O Subsystem

APB

Features

Interfaces

Availability
BCM4334
Linux Driver

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Production:

Now

Serial enhanced coexistence interface

91

BCM4339
Single chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver
Block Diagram

High-performance, space-constrained consumer IoT applications

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Wi-Fi Subsystem

Features

MAC And PHY


Dual-Band Radio

Wi-Fi Features
802.11b/g/n/ac compliant
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1

Security Engine2

Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

SPI

GPIO x16

PCM/I2S

SRAM (768KB)
FM Subsystem
SDIO 2.0/3.0

ROM (640KB)

FM RX

JTAG/SWD
GCI2

SECI
PCM/I2S

Bluetooth Subsystem
Bluetooth 4.1
Link Layer And PHY

FM Receiver
Packages
160-ball FCFBGA (8 x 8 mm)
145-ball WLBGA (4.87 x 5.41 mm)
286-ball WLCSP (4.87 x 5.41 mm)

SRAM (192KB)

AHB

ARM Cortex M3

ROM (608KB)

Linux Driver

JTAG/SWD

Collateral

ARM Cortex R4

I/O Subsystem

UART

AXI

Industrys Most-Widely deployed Wi-Fi IP and Bluetooth stack

Datasheet:
Software:

Interfaces

APB

Applications

Availability
BCM4339
Linux Driver

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

Production:

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

92

BCM4356
Single-Chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver, A4WP
Block Diagram

Consumer electronics and wireless chargingenabled applications

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Interfaces

Wi-Fi Subsystem

Features

MAC And PHY

Wi-Fi Features
802.11b/g/n/ac compliant
2x2 Multiple-input multiple-output (MIMO)
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
Alliance for Wireless Power (A4WP) Bluetooth Low Energy profile

UART

2x2 Dual-Band Radio


SPI

Security Engine2
ARM Cortex R4

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

I/O Subsystem

APB

Applications

GPIO x16

PCM/I2S

SRAM (768KB)
FM Subsystem
SDIO 2.0/3.0

ROM (640KB)

FM RX

JTAG/SWD
PCIe 3.0

PCM/I2S

Bluetooth Subsystem
GCI2 SECI3

Bluetooth 4.1
Link Layer And PHY

SRAM (200KB)

Packages
192-ball WLBGA (4.87 x 7.67 mm)
395-ball WLCSP (4.87 x 7.67mm)

AHB

ARM Cortex M3

FM Receiver

ROM (668KB)
JTAG/SWD

Linux Driver

Collateral
Datasheet:
Software:
1

Availability
BCM4356
Linux Driver

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

Production:

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

93

BCM43455
Single chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver
Block Diagram

High-performance, space-constrained consumer/commercial IoT

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Interfaces

Wi-Fi Subsystem

Features

MAC And PHY

Wi-Fi Features
802.11b/g/n/ac compliant
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM Receiver

UART

Dual-Band Radio
SPI

Security Engine2
ARM Cortex R4

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

GPIO x15

PCM/I2S

SRAM (800KB)
FM Subsystem
SDIO 2.0/3.0

ROM (704KB)

FM RX

JTAG/SWD
PCIe 3.0

PCM/I2S

Bluetooth Subsystem
GCI2 SECI

Bluetooth 4.1
Link Layer And PHY

Package
140-ball WLBGA (4.47x5.27 mm)

I/O Subsystem

APB

Applications

SRAM (270KB)

Linux Driver

AHB

ARM Cortex M3

ROM (845KB)

Collateral
Datasheet:
Software:

JTAG/SWD

BCM43455
Linux Driver

Availability
Production:

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

94

BCM4354
Single-Chip IEEE 802.11ac with Integrated Bluetooth 4.1 and FM Receiver
Block Diagram

High-performance, space-constrained consumer/commercial IoT

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Interfaces

Wi-Fi Subsystem

Features

MAC And PHY

Wi-Fi Features
802.11b/g/n/ac compliant
2x2 Multiple-input multiple-output (MIMO)
433.3-Mbps data rate
Dual band (2.4/5 GHz)
2-/3-/4-wire global coexistence interface (GCI) SECI1
Bluetooth Features
Bluetooth 4.1 compliant
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART
FM Receiver

ARM Cortex R4

GPIO x16

PCM/I2S

SRAM (768KB)
FM Subsystem
SDIO 2.0/3.0

ROM (640KB)

FM RX

JTAG/SWD
PCIe 3.0

PCM/I2S

Bluetooth Subsystem
GCI2 SECI

Bluetooth 4.1
Link Layer And PHY

AHB

SRAM (200KB)
ROM (668KB)

Linux Driver

JTAG/SWD

Collateral

SPI

Security Engine2

ARM Cortex M3

Packages
192-ball WLBGA (4.87 x 7.67 mm)
395-ball WLCSP (4.87 x 7.67mm)

Datasheet:
Software:

UART

2x2 Dual-Band Radio

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

I/O Subsystem

APB

Applications

Availability
BCM4354
Linux Driver

Serial enhanced coexistence interface

Document No. 001-89435 Rev. *L

Production:

2 WPA,

Now

WAPI STA, WPA2, AES, TKIP security features

95

BCM43012
Single-Chip IEEE 802.11n with Integrated Bluetooth 5.0 Ready
Applications

Block Diagram

Smart-home hub for IoT applications

Single-Chip Wi-Fi and Bluetooth Connectivity Solution


Interfaces

Wi-Fi Subsystem
MAC And PHY
Dual-Band Radio

Ultra-Low-Power

Security Engine1

Wi-Fi Features
802.11b/g/n compliant
96-Mbps data rate
Dual band (2.4/5 GHz)
On-chip, low-noise amplifier for both bands

ARM Cortex M3

UART

SPI

AXI

Industrys Most-Widely-Deployed Wi-Fi IP and Bluetooth Stack

I/O Subsystem

APB

Features

GPIO x16

PCM/I2S x2

SRAM (640KB)
SDIO 2.0/3.0

ROM (1280KB)

Bluetooth Features
Bluetooth 4.2 compliant, Bluetooth 5.0 ready
Class 1 (100 m) and Class 2 (10 m) operation
Host controller interface (HCI)-over-UART

JTAG/SWD
GCI2 SECI3
Bluetooth Subsystem
Bluetooth 4.2/5.0
Link Layer And PHY

Packages
252-ball WLCSP (3.76 x 4.27 mm)
107-ball RWLBGA (3.96 x 4.47 mm)

SRAM (388KB)

AHB

ARM Cortex M4

ROM (1152KB)

Linux Driver

JTAG/SWD

Collateral
Datasheet:
Software:

BCM43012 (Contact Sales)


Linux Driver

Availability
Sampling:

WPA, WAPI STA, WPA2, AES, TKIP security features

Document No. 001-89435 Rev. *L

Global coexistence interface

3 Serial

Q117

enhanced coexistence interface

96

Wireless Solutions for The Internet of Things (IoT)


Roadmap

Automotive wireless PORTFOLIO

Document No. 001-89435 Rev. *L

97

Automotive Wireless Portfolio


Bluetooth (BR1 + EDR2)

IEEE 802.11a/b/g/n/ac WLAN3 + Bluetooth

Performance/Integration

NEW

NEW

Q416
BCM89359
Up to 867 Mbps, 802.11a/b/g/n/ac,
2x2 MIMO10 w/RSDB11, BT 4.2 BR + EDR + BLE,
GCI SECI, SDIO 3.0, PCIe, UART, USB, I2C,
SPI, HCI-over-UART, PCM/I2S, Security12,
20 GPIO, C1/C2,
Linux Driver

BCM89071
24-MHz ARM7TDMI-S4, SPI, UART, I2C,
I2S/PCM, GCI5 SECI6,
HCI7-over-UART/SPI,
8 GPIO, 112KB RAM,
BT8 4.1 BR + EDR, C1/C2/C39

NEW

NEW

BCM88335/BCM43353
Up to 433.3 Mbps, 802.11a/b/g/n/ac, SISO13,
BT4.1 BR + EDR + BLE, GCI SECI,
SDIO2.0/3.0,
SPI, HCI-over-UART, PCM/I2S, Security,
9 GPIO, C1/C2,
Linux Driver

BCM20713
24-MHz ARM7TDMI-S, SPI, UART, I2C,
I2S/PCM, GCI SECI, HCI-over-UART/SPI,
8 GPIO, 16KB RAM,
BT 4.0 BR + EDR, C1/C2/C3

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

11

12

Basic Rate
Enhanced Data Rate
3 Wireless Local Area Network
4 ARM 7 Family CPU
5 Global coexistence interface

Document No. 001-89435 Rev. *L

Serial enhanced coexistence interface


Host controller interface
8 Bluetooth Specification
9 Class 1 (100 m)/2 (10 m)/3 (1 m)
10 Multiple-input multiple-output

Real Simultaneous Dual Band


WPA, WAPI STA, WPA2, AES, TKIP, Cisco
Compatible Extensions security features
13 Single-input single-output

98

Wireless Solutions for The Internet of Things (IoT)


Roadmap

Proprietary Wireless PORTFOLIO

Document No. 001-89435 Rev. *L

99

Proprietary Wireless Portfolio


Programmable Radio-on-Chip (PRoC)

GFSK4

2.4-GHz RF
Transceiver
CYRF8935
WUSB2-NL
1 Mbps,
TX 18 mA, RX 18 mA

CYRF89135
PRoC-Embedded
WUSB-NL, M8C3,
35 GPIO, 32KB Flash

GFSK + DSSS5

TrueTouch

CYRF89535
PRoC-TT
WUSB-NL, M8C,
2-Finger,
35 GPIO, 32KB Flash

CYRF89435
PRoC-CS
WUSB-NL, M8C,
35 GPIO, 32KB Flash

CYRF89235
PRoC-USB
WUSB-NL, M8C, USB,
13 GPIO, 32KB Flash

CYRF6936
WUSB-LP
1 Mbps,
TX 26 mA, RX 21 mA

CapSense

MCU

CYRF69xx3
PRoC-LP
WUSB-LP, M8C, USB,
14 GPIO, 8KB Flash

Integration
Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

1 Touch-sensing

technology with 2-finger gestures

2 WirelessUSB
3 Cypress

4 Gaussian
5 Direct

frequency shift keying


sequence spread spectrum

proprietary 8-bit MCU

Document No. 001-89435 Rev. *L

100

Modules

Document No. 001-89435 Rev. *L

101

EZ-BLETM Module Portfolio


Programmable Radio-on-Chip (EZ-BLETM PRoCTM)
256KB Flash

128KB Flash

256KB Flash

CYBLE-014008-00
EZ-BLE PSoC Module BLE 4.1
4 Opamps, 1 CMP6, 4 UDBs7
CM0, 2 SCB,,25 GPIOs
11 x 11 x 1.80 mm SMT

CYBLE-214009-00 Q316
EZ-BLE PSoC Module BLE 4.1
4 Opamps,1 CMP, 4 UDBs
CM0, 2 SCB,,25 GPIOs
11 x 11 x 1.80 mm SMT

CYBLE-022001-00
EZ-BLEPRoC Module BLE5 4.1
CM03, 2 SCB4
16 GPIOs
10 x 10 x 1.80 mm SMT8

CYBLE-222005-00
EZ-BLE PRoC Module BLE 4.1
CM0, 2 SCB
16 GPIOs
10 x 10 x 1.80 mm SMT

CYBLE-222014-01 Q316
EZ-BLE PRoC Module BLE 4.2
CM0, 2 SCB
16 GPIOs
10 x 10 x 1.80 mm SMT

CYBLE-012011-00
EZ-BLE PRoC Module BLE 4.1
CM0, 2 SCB
23 GPIOs
14 x 19 x 2.00 mm SMT

CYBLE-212019-00 Q316
EZ-BLE PRoC Module BLE 4.1
CM0, 2 SCB
23 GPIOs
14 x 19 x 2.00 mm SMT

CYBLE-212020-01 Q316
EZ-BLE PRoC Module BLE 4.2
CM0, 2 SCB
23 GPIOs
14 x 19 x 2.00 mm SMT

CYBLE-214015-01 Q316
EZ-BLE PSoC Module BLE 4.2
4 Opamps,1 CMP, 4 UDBs
CM0, 2 SCB,,25 GPIOs
11 x 11 x 1.80 mm SMT

CYBLE-012012-10
EZ-BLE PRoC Module BLE 4.1
CM0, 2 SCB
23 GPIOs, NS10, NC11
14 x 19 x 2.00 mm SMT

CYBLE-212023-10 Q316
EZ-BLE PRoC Module BLE 4.1
CM0, 2 SCB
23 GPIOs, NS10, NC11
14 x 19 x 2.00 mm SMT

CYBLE-202007-01 Q316
EZ-BLE PRoC Module BT 4.2
External Antenna via u.FL
CM0, 2 SCB, PA9, 19 GPIOs
15 x 23 x 2.0 mm SMT

CYBLE-224110-00 Q316
EZ-BLEPSoC XT/XR12 Module
BLE 4.1, 4 Opamps,1 CMP,PA9
4 UDBs,CM0,2 SCB, 25 GPIOs
9.5 x 15.4 x 1.80 mm SMT

Long Range2

Standard Range1

128KB Flash

Programmable System-on-Chip (EZ-BLE PSoC)

CYBLE-212006-01 Q316
EZ-BLE PRoC Module BT 4.2
PCB Antenna
CM0, 2 SCB, PA9, 19 GPIOs
15 x 23 x 2.0 mm SMT

NEW

CYBLE-202013-11 Q316
EZ-BLE PRoC Module BT 4.2
External Antenna via RF Pin
CM0, 2 SCB, PA9, 19 GPIOs
15 x 23 x 2.0 mm SMT

CYBLE-224116-01 Q316
EZ-BLEPSoC XT/XR12 BLE 4.2
4 Opamps,1 CMP,4 UDBs,PA9
CM0,2 SCB, 25 GPIOs
9.5 x 15.4 x 1.80 mm SMT

Integration
1 Range

up to 30 meter Line-of-Sight
2 Range up to 400 meter Line-of-Sight
3 ARM Cortex -M0
4 Serial communication block

Document No. 001-89435 Rev. *L

5 BLE

Specification Version
6 Comparator
7 Universal Digital Block
8 Surface mount technology

9
10
11
12

Power Amplifier
NS = No Shield
NC = No Certifications
XT/XR = Extended Temperature/Extended Range

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

102

Cypress Trackpad Portfolio

Gen5 Windows PTP1 Module


5-Finger Detection/Communication
PS2/I2C
60-Vpp2 Charger Armor3

Chrome Trackpad Modules

Modules for Embedded Systems

Gen5 Chrome Module


5-Finger Detection/Communication
I2C
60-Vpp2 Charger Armor3

Gen6 Embedded Module


5-Finger Gesture4
I2C
Max Size5: 120 x 75 mm

Gen6 Chrome Module


5-Finger Detection/Communication
I2C
35-Vpp2 Charger Armor3

Gen4 + KB6 + RF7 Module


5-Finger Gesture4 and KB6 Scan
I2C
Max Size5: 125 x 125 mm

Software

Self
Capacitance

Mutual
Capacitance

Windows Trackpad Modules

Gen2 Embedded Module


2-Finger Gesture4
I2C
Max Size5: 90 x 50 mm

Windows Driver
5-Finger Gesture4
Windows 7/8/8.1/10 Compatible
User Configuration GUI9

1 Microsoft

6 Keyboard

2 Noise

7 Radio

Precision Touchpad
voltage peak to peak
3 System noise detection and reduction
4 Gesture processing
5 Maximum active sensing area

Document No. 001-89435 Rev. *L

Chrome Driver
5-Finger Detection/Communication
MT-B Compliant, Linux

frequency (2.4-GHz wireless)


8 Bluetooth Low Energy, also known as Bluetooth Smart
9 Graphical user interface

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

103

EZ-BLE CYBLE-x220xx-0x Modules


Bluetooth Low Energy Module using PRoC BLE with 128KB and 256KB Flash
Block Diagram

Applications
Bluetooth Low Energy (BLE) connectivity, medical, industrial,
PC accessories, toys and smartphone accessories

Power/
Ground

EZ-BLE PRoC Module

32.768-kHz Crystal

Features

14

Qualification and Certification


Bluetooth SIG QDID1, FCC2, CE3, KC4, MIC5 and IC6
Small Footprint:
10 mm x 10 mm x 1.8 mm, 21/22-pad SMT with 16 GPIO
Bluetooth Smart Connectivity with BLE 4.1 and 4.2
2.4-GHz BLE radio and baseband
-91-dBm Rx sensitivity, +3-dBm Tx output power
Power Modes
1.3-A deep-sleep, 150-nA hibernate, 60-nA stop
Highly Integrated Solution
Two crystals, chip antenna, passives, shield
128KB and 256KB flash sizes
CYBLE-x220xx-EVAL Evaluation Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA7

PRoC BLE

24-MHz Crystal

XRES

SWD8/
GPIO
SPI/
I2C/
UART/
CapSense/
ADC/
PWM/GPIO

Chip
Antenna

VREF10

Collateral
CYBLE-022001-00 Datasheet
CYBLE-222005-00 Datasheet

CYBLE-222014-01 (BT 4.2) Datasheet


PRoC BLE Datasheet

Availability
Sampling:
Production:

Getting Started Application Note


128KB
Now
Now

256KB
Now
Now

BLE 4.2
Now
Q316

PSoC Creator
PSoC Programmer
CySmart11 Windows Host Emulation Tool
CySmart iOS and Android Apps

1 Bluetooth

5 Korea

2 Bluetooth

10

Low Energy, also known as Bluetooth Smart


Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformit Europenne (Europe)

Document No. 001-89435 Rev. *L

Certification
Ministry of Internal Affairs and Communications (Japan)
7 Industry Canada
8 Over-the-Air

Serial wire debug communication protocol


VREF only available on 256KB module
11 A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications

104

EZ-BLE CYBLE-x140xx-0x Modules


Bluetooth Low Energy (BLE) Module using PSoC 4 BLE with up to 256KB Flash
Applications

Block Diagram

Sports and fitness monitors, medical devices, wearable


electronics, home automation solutions and game controllers

5
Power/
Ground

EZ-BLE PSoC Module

SWD9/
GPIO

23

Analog
and Digital
GPIOs

32.768-kHz Crystal

Features
Qualification and Certification
Bluetooth SIG QDID1, FCC2, CE3, KC4, MIC5 and IC6
Small Footprint: 11 mm x 11 mm x 1.8 mm, 32-SMT, 25 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
Highly Integrated Solution
Two crystals, trace antenna, passives, shield
128KB and 256KB flash sizes, with over-the-air firmware
upgrades
Programmable Analog Blocks
Four opamps, configurable as PGAs, comparators, filters, etc.
One 12-bit, 1-Msps SAR7 ADC
Programmable Digital Blocks
Four Universal Digital Blocks (UDBs): custom digital peripherals
Four configurable TCPWM8 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks for I2C/SPI/UART
Power Modes:1.3-A Deep Sleep,150-nA Hibernate,60-nA Stop
CYBLE-x140xx-EVAL Kit for fast evaluation and development

PSoC 4 BLE

24-MHz Crystal

XRES

Trace
Antenna

VREF

Collateral
CYBLE-014008-00 Datasheet

CYBLE-214009-00 Datasheet
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator

Availability
Sampling
Production:

PSoC Programmer

128KB
Now
Now

256KB
Now
Q316

BLE 4.2
Q316
Q416

CySmart10 Windows Host Emulation Tool

CySmart iOS and Android Apps

1 Bluetooth

2 Federal

10

Special Interest Group Qualification Design ID


Communications Commission
3 Conformit Europenne (Europe)
4 Korea Certification

Document No. 001-89435 Rev. *L

Ministry of Internal Affairs and Communications (Japan)


Industry Canada
7 Successive approximation register
8 Timer/Counter/Pulse-Width Modulator

Serial wire debug communication protocol


A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications

105

EZ-BLE CYBLE-x120xx-xx Modules


Cost Optimized Bluetooth Low Energy (BLE) EZ-BLE PRoC Modules
Applications

Block Diagram

BLE connectivity, medical, industrial, PC accessories,


toys and smartphone accessories

Power/
Ground

EZ-BLE PRoC Module

SWD9/
GPIO

21

SPI/
I2C/
UART/
CapSense/
ADC/
PWM/GPIO

32.768-kHz Crystal

Features
Qualification and Certification
Bluetooth SIG QDID1 (CYBLE-012011-00/
CYBLE-212019-00), FCC2, CE3, KC4, MIC5 and IC6
Small Footprint
14.5 mm x 19.2 mm x 2.0 mm, 31-pad SMT with 23 GPIO
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
2.4-GHz BLE radio and baseband
-91-dBm Rx sensitivity, +3-dBm Tx output power
Power Modes
1.3-A Deep-Sleep, 150-nA Hibernate, 60-nA Stop
Highly Integrated Solution
Two crystals, trace antenna, passives, shield7
CYBLE-x120xx-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8

PRoC BLE

24-MHz Crystal

XRES

Trace
Antenna

VREF

Collateral
CYBLE-01200x-x0 Datasheet
CYBLE-212019-00 Datasheet
PRoC BLE Datasheet
Getting Started Application Note

Availability
Sampling:
Production:

PSoC Creator
4.1/128KB 256KB
Now
Now
Now
Q316

BLE 4.2
Q316
Q316

PSoC Programmer

CySmart10 Windows Host Emulation Tool


CySmart iOS and Android Apps

1 Bluetooth

2 Federal

10

Special Interest Group Qualification Design ID


Communications Commission
3 Conformit Europenne (Europe)
4 Korea Certification

Document No. 001-89435 Rev. *L

Ministry of Internal Affairs and Communications (Japan)


Industry Canada
7 CYBLE-0120012-10 does not include metal shield
8 Over-the-Air

Serial wire debug communication protocol


A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications

106

EZ-BLE XT/XR1 Module CYBLE-22411x-0x


Long Range Bluetooth Low Energy Module Supporting Extended Temperatures
Applications

Block Diagram

Bluetooth Low Energy (BLE) connectivity, lighting, industrial


and medical

Power/
Ground

EZ-BLE PSoC XT/XR1 Module

SWD9/
GPIO

23

SPI/
I2C/
UART/
CapSense/
ADC/
PWM/GPIO

32.768-kHz Crystal

Features
Qualification and Certification
Bluetooth SIG QDID2, FCC3, CE4, MIC5, KC6 and IC7
Small Footprint
9.5 mm x 15.4 mm x 1.8 mm, 32-pad SMT with 25 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.1 and 4.2
2.4-GHz BLE radio and baseband
Extended Industrial Temperature Range
Operating Temperature range from -40C to +105C
Long Range
+9.5-dBm Tx output power
- 95 dBm Rx sensitivity
400 meters line-of-sight range
Highly Integrated Solution
2 crystals, trace antenna, power amplifier, passives, shield
CYBLE-22411x-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8

PSoC 4 BLE

24-MHz Crystal

XRES
Chip
Antenna

VREF

Power
Amplifier

Collateral
CYBLE-224110-00 Datasheet
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator
PSoC Programmer

Availability
Sampling:
Production:

CySmart10 Windows Host Emulation Tool


4.1
Now
Q316

4.2
Q316
Q416

CySmart iOS and Android Apps

6 Korea

10

Extended temperature/extended range


Bluetooth Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformit Europenne (Europe)

Document No. 001-89435 Rev. *L

Ministry of Internal Affairs and Communications (Japan)


Certification
7 Industry Canada
8 Over-the-Air

Serial wire debug communication protocol


A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications

107

EZ-BLE XR1 Module CYBLE-2x20xx-x1


Long Range Bluetooth Low Energy Module Supporting External Antenna
Applications

Block Diagram

Bluetooth Low Energy (BLE) connectivity, lighting, industrial


and medical

Power/
Ground

EZ-BLE PRoC XR1 Module

SWD9/
GPIO

17

SPI/
I2C/
UART/
CapSense/
ADC/
PWM/GPIO

32.768-kHz Crystal

Features
Qualification and Certification
Bluetooth SIG QDID2, FCC3, CE4, MIC5, KC6 and IC7
Small Footprint
15.0 mm x 23.0 mm x 2.0 mm, 30-pad SMT with 19 GPIOs
Bluetooth Smart Connectivity with Bluetooth 4.2
2.4-GHz BLE radio and baseband
Extended Industrial Temperature Range
Operating Temperature range from -40C to +85C
Long Range
+7.5-dBm Tx output power
- 93 dBm Rx sensitivity
400 meters line-of-sight range
Highly Integrated Solution
2 crystals, trace antenna (option), power amplifier, passives
CYBLE-2x20xx-EVAL Adapter Board Interface
Easy interface to CY8CKIT-042-BLE Pioneer Kit
Enables testing of CapSense, buttons, GPIOs, OTA8

PRoC 4 BLE

24-MHz Crystal

XRES

Power
Amplifier

VREF

PCB
Antenna
Antenna

Collateral
Datasheet - Contact Sales
PSoC 4 BLE Datasheet
Getting Started Application Note
PSoC Creator
PSoC Programmer

Availability
Sampling:
Production:

CySmart10 Windows Host Emulation Tool


CySmart iOS and Android Apps

Q316
Q416

6 Korea

10

Extended range
Bluetooth Special Interest Group Qualification Design ID
3 Federal Communications Commission
4 Conformit Europenne (Europe)

Document No. 001-89435 Rev. *L

Ministry of Internal Affairs and Communications (Japan)


Certification
7 Industry Canada
8 Over-the-Air

Serial wire debug communication protocol


A GUI-based software tool that installs on your PC to test and debug
BLE functionality; also available in iOS and Android mobile applications

108

Gen5 Chrome Module


Applications

Block Diagram
Host Processor

Chromebook PCs

2 I2C Clock/Data

INT4

Features

Gen5 Chrome Module

Mechanical Construction
Maximum active sensing area of 125 mm x 70 mm
Minimum of 1.3 mm total module thickness
Clickpad1 and standard2 configurations
Overlay assembly and lamination available
Advanced Processing
60-Vpp3 charger noise immunity (1-500 kHz, 9-mm finger)
32-bit ARM Cortex-M0 core for more processing power
I2C communication interface
Report rates up to 150 Hz
Five-finger detection and communication
Low-power, look-for-touch active mode
Google-qualified multi-touch Cypress driver
Compatible with Google Multi-touch Protocol B (MT-B)
Product Support
On-site support for customer product introduction available
Incoming/outgoing test equipment available to customers

CY8CTMA545

I2C
AHB-Lite5

Flash

AHB-Lite5
ARM Cortex-M0

SRAM
116

116
AHB-Lite5

116
Channel
Engine

10-V Tx
Pump

Touch
Sequencer
Rx Channels

Programmable Analog Multiplexer

36

Collateral
Datasheet:

116

AHB-Lite5

Trackpad Sensor I/O: XY00-XY35

Trackpad
Sensor

Contact Sales

1 Trackpad

with integrated mechanical button


with support for external mechanical button inputs
3 Noise voltage peak to peak
4 Interrupt
5 Advanced High-Performance Bus Lite
2 Trackpad

Document No. 001-89435 Rev. *L

Availability
Production:

Now

109

Gen6 Chrome Module


Applications

Block Diagram
Host Processor

Chromebook PCs

2 I2C Clock/Data

INT4

Features

Gen6 Chrome Module

Mechanical Construction
Maximum active sensing area of 120 mm x 75 mm
Minimum of 1.3 mm total module thickness
Clickpad1 and standard2 configurations
Overlay assembly and lamination available
Advanced Processing
35-Vpp3 charger noise immunity (1-500 kHz, 9-mm finger)
32-bit ARM Cortex-M0 core for more processing power
I2C communication interface
Report rates up to 150 Hz
Five-finger detection and communication
Low-power, look-for-touch active mode
Google-qualified multi-touch Cypress driver
Compatible with Google Multi-touch Protocol B (MT-B)
Product Support
On-site support for customer product introduction available
Incoming/outgoing test equipment available to customers

CY8CTMA445A

I2C
AHB-Lite5

Flash

AHB-Lite5
ARM Cortex-M0
AHB-Lite5

5-V Tx Pump

SRAM
116

116
116

Touch
Sequencer

Rx Channels

Programmable Analog Multiplexer

36

Collateral
Datasheet:

116

AHB-Lite5

Trackpad Sensor I/O: XY00-XY35


Trackpad
Sensor

Contact Sales

1 Trackpad

with integrated mechanical button


with support for external mechanical button inputs
3 Noise voltage peak to peak
4 Interrupt
5 Advanced High-Performance Bus Lite
2 Trackpad

Document No. 001-89435 Rev. *L

Availability
Production:

Now

110

Gen5 Windows PTP1 Module


Applications

Block Diagram
Host Processor

Windows PCs

INT5
I2C/PTP1 Only

Features
Mechanical Construction
Maximum active sensing area of 125 mm x 70 mm
Minimum of 1.3 mm total module thickness
Clickpad2 and standard3 configurations
Overlay assembly and lamination available
Advanced Processing
60-Vpp4 charger noise immunity (1-500 kHz, 9-mm finger)
32-bit ARM Cortex-M0 core for more processing power
Dual bus interface PS2 and I2C/PTP1
Report rates of up to 150 Hz
Enhanced palm rejection
Five-finger detection and communication
Low-power, look-for-touch active mode
Windows driver support for 7/8/8.1/10
Product Support
On-site support for customer product introduction available
Incoming/outgoing test equipment available to customers

PS2 and I2C Clock/Data

Gen5 Windows
PTP1 Module
CY8CTMA545

PS2/I2C
AHB-Lite6

116

AHB-Lite6
Flash

AHB-Lite6
ARM Cortex-M0

SRAM
116

116
AHB-Lite6

116
Channel
Engine

10-V Tx
Pump

Touch
Sequencer
Rx Channels

Programmable Analog Multiplexer

36

Trackpad Sensor I/O: XY00-XY35


Trackpad
Sensor

Collateral
Datasheet:

Contact Sales

1 Microsoft

Precision Touchpad
with integrated mechanical button
3 Trackpad with support for external mechanical button inputs
4 Noise voltage peak to peak
5 Interrupt
6 Advanced High-Performance Bus Lite
2 Trackpad

Document No. 001-89435 Rev. *L

Availability
Production:

Now

111

Gen6 Embedded Trackpad Module


Applications

Block Diagram
Host Processor

Keyboards, mice, remote controls and wearables

Gen6 Embedded Module

Mechanical Construction
Maximum active sensing area of 120 mm x 75 mm
Minimum of 1.3 mm total module thickness
Clickpad1 and standard2 configurations
Overlay assembly and lamination available
Advanced Processing
10-Vpp3 charger noise immunity (1-500 kHz, 9-mm finger)
32-bit ARM Cortex-M0 core for more processing power
I2C, UART, or SPI communication interface
Report rates up to 150 Hz
Five-finger detection and communication
Low-power, look-for-touch active mode
Embedded Gesture Detection and Communication
Product Support
On-site support for customer product introduction available
Incoming/outgoing test equipment available to customers

CY8CTMA445A

I2C
AHB-Lite5

Flash

AHB-Lite5
ARM Cortex-M0
AHB-Lite5

5-V Tx Pump

with integrated mechanical button


with support for external mechanical button inputs
3 Noise voltage peak to peak
4 Interrupt
5 Advanced High-Performance Bus Lite

Document No. 001-89435 Rev. *L

116

Touch
Sequencer

Rx Channels

Programmable Analog Multiplexer

Trackpad Sensor I/O: XY00-XY35


Trackpad
Sensor

Contact Sales

2 Trackpad

SRAM
116

116

36

1 Trackpad

116

AHB-Lite5

Collateral
Datasheet:

2 I2C Clock/Data

INT4

Features

Availability
Production:

Now

112

Gen2 Embedded Trackpad Module


Applications

Block Diagram
Host Processor

Keyboards, mice, remote controls and wearables

2 I2C or SPI Clock/Data

INT4

Features

Gen2 Embedded Module

Mechanical Construction
Maximum active sensing area of 90 mm x 55 mm
Minimum of 1.3 mm total module thickness
Clickpad1 and standard2 configurations
Overlay assembly and lamination available
Advanced Processing
Low-power active mode as low as 1 mA
Low-power idle and sleep modes (<30 A)
I2C or SPI communication interface
Report rates up to 100 Hz
Two-finger detection and communication
Embedded Gesture Detection and Communication
Product Support
On-site support for customer product introduction available
Incoming/outgoing test equipment available to customers

CY8CTMG2xx

Flash

I2C/SPI

CPU

SRAM

Analog Front End

Programmable Analog Multiplexer

Collateral
28

Datasheet:

Contact Sales

Trackpad Sensor I/O: XY00-XY27


Trackpad
Sensor

Availability
1 Trackpad

with integrated mechanical button


with support for external mechanical button inputs
3 Noise voltage peak to peak
4 Interrupt
2 Trackpad

Document No. 001-89435 Rev. *L

Production:

Now

113

Gen4 + KB1 + RF2 Module


Wireless Trackpad + Keyboard Solution
Applications
External keyboard and trackpad, standalone trackpad,
remote control and trackpad, tablet keyboard dock and
trackpad

Block Diagram
Gen4 + KB1 + RF2 Module
Antenna
SPI

Features

WUSB-NX

Mechanical Construction
Maximum active sensing area of 125 mm x 125 mm
Clickpad3 and standard4 configurations
Overlay assembly and lamination available
Advanced Processing
32-bit ARM Cortex-M0 core for more processing power
Five-finger detection and communication
Software-free solution allowing fast time-to-market
Embedded gesture detection
Six configurable power modes
2.4-GHz wireless communication
Cypress PSoC4A supporting keyboard scan
Optional LED control
Product Support
Simplification of OEM/ODM supply chains
Incoming/outgoing test equipment available to customers

PSoC4

30

Keyboard GPIO:
XY00-XY29

Keyboard
Matrix

I2C
2

INT5

Mechanical
Buttons

Gen4
Trackpad
Controller

65

GPIO

Trackpad Sensor I/O:


XY00-XY64

LEDs
GPIO

Trackpad
Sensor

Availability
Production:

Now

Collateral
Datasheet:

Contact Sales

1 Keyboard
2 Radio

frequency (2.4-GHz wireless)


with integrated mechanical button
4 Trackpad with support for external mechanical button inputs
5 Interrupt
3 Trackpad

Document No. 001-89435 Rev. *L

114

Asynchronous SRAMs

Document No. 001-89435 Rev. *L

115

Asynchronous SRAM Portfolio

High Density | Wide Voltage Range | Automotive A1, E2 | On-Chip ECC3


Low-Power SRAM (MoBL4)

Fast SRAM

32Mb-128Mb

Non-ECC

ECC

CY7C107x
32Mb; 3.3 V
12 ns; x8, x16
Ind

64Kb-1Mb

2Mb-16Mb

CY7C106x
16Mb; 1.8, 3.3 V
10 ns; x8, x16, x32
Ind

ECC

CY6218x
64Mb; 1.8, 3.0 V
55 ns; x16
Ind

NDA Required
Contact Sales

CY7C106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Ind, Auto E

CY6216x
16Mb;1.8, 3.0, 5.0 V
45 ns; x8, x16
Ind, Auto A

CY6216x
16Mb; 1.8-5.0 V
45 ns; x8, x16, x32
Ind, Auto E

CY7C1012
12Mb; 3.3 V
10 ns; x24
Ind

CY7C105x
8Mb; 3.3, 5.0 V
10 ns; x8, x16
Ind, Auto E

CY6215x
8Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Ind, Auto A, E

CY6216x
8Mb; 3.3, 5.0 V
45 ns; x8, x16, x32
Ind, Auto E

CY7C104x
4Mb; 3.3, 5.0 V
10 ns; x4, x8, x16
Ind, Auto A, E

CY7C1034
6Mb; 3.3 V
10 ns; x24
Ind

CY7C104x
4Mb; 1.8-5.0 V
10 ns; x8, x16
Ind, Auto E

CY6214x
4Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Ind, Auto A, E

CY6214x
4Mb; 1.8-5.0 V
45 ns; x8, x16
Ind, Auto E

CY7C1010/11
2Mb; 3.3 V
10 ns; x8, x16
Ind, Auto A, E

CY7C1024
3Mb; 3.3 V
10 ns; x24
Ind

CY6213x
2Mb; 1.8, 2.5-5.0 V
45 ns; x8, x16
Ind, Auto A, E

CY7C1020
512Kb; 2.6, 3.3, 5.0 V
10 ns; x16
Ind, Auto E

CY7C1019/21/100x
1Mb; 2.6, 3.3, 5.0 V
10 ns; x4, x8, x16
Ind, Auto A, E

CY6212x
1Mb; 2.5-5.0 V
45 ns; x8, x16
Ind, Auto A, E

CY7C185
64Kb; 5.0 V
15 ns; x8
Ind

CY7C19x/1399
256Kb; 3.3, 5.0 V
10 ns; x4, x8
Ind, Auto A

CY6264/62256
64-256Kb; 1.8, 3.0, 5V
55 ns, 70 ns; x8
Ind, Auto A, E

A Fast SRAM with a deep-sleep mode in addition to a


conventional standby mode. For example, the
12-ns 16Mb offering has a deep-sleep current of
1.37 A/Mb and a standby current of 1.87 mA/Mb

Document No. 001-89435 Rev. *L

ECC

Serial SRAM (with ECC)


Quad-SPI

HyperBus6

NDA Required
Contact Sales

NDA Required
Contact Sales

CY6217x
32Mb; 1.8-5.0 V
55 ns; x16
Ind

CY7C105x
8Mb; 3.3 V
10 ns; x8, x16
Ind

AEC-Q100 -40C to +85C


AEC-Q100 -40C to +125C
3 Error correcting code
4 More Battery Life
2

Non-ECC

PowerSnooze5

CY7S106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Ind, Auto E

CY7S104x
4Mb; 1.8-5.0 V
10 ns; x8, x16
Ind, Auto E

A high-bandwidth,12-signal interface that


transfers information over 8 I/O signals at
Status
Double Data Rate (DDR), delivering up to
Availability
400 MBps

Concept

Development

Sampling

Production

QQYY

QQYY

Roadmap 116

Fast SRAM Family with ECC1


Applications

Family Table

Switches and routers


IP phones
Test equipment
Automotive
Computation servers
Military and aerospace systems

Features
Access time: 10 ns
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
ECC to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Error indication (ERR) pin to indicate single-bit errors

Density

MPN

Access Time

4Mb
8Mb
16Mb

CY7C104x
CY7C105X
CY7C106x

10 ns
10 ns
10 ns

Operating Current
(Maximum at 85C)
45 mA
110 mA
110 mA

Block Diagram
Fast SRAM with ECC
SRAM Array

ECC
Encoder

Input
Buffer

18-23
Address

Address
Decoder

Collateral

8, 16, 32
Data
ERR

I/O Mux

SRAM Array

Sense
Amps

ECC
Decoder

Datasheet: Async SRAM with ECC datasheets


Control Logic

CE

OE

WE

BHE2

BLE3

Availability
1

Error-correcting code
Byte high enable
3 Byte low enable
2

Document No. 001-89435 Rev. *L

Sampling:
Production:

Now
Now
Product Overview 117

MoBL1 SRAM Family With ECC2


Applications

Family Table

Programmable logic controllers


Handheld devices
Multifunction printers
Automotive
Implantable medical devices
Computation servers

Features
Access time: 45 ns
Standby current: 8.7 A for 4Mb
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
ECC to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Error indication (ERR) pin to indicate single-bit errors

Density

MPN

4Mb
8Mb
16Mb

CY6214x
CY6215x
CY6216x

Standby Current
(Maximum at 85C)
8.7 A
16.0 A
16.0 A

Standby Current
(Typical at 25C)
3.5 A
5.5 A
5.5 A

Block Diagram
MoBL SRAM with ECC
SRAM Array

ECC
Encoder

Input
Buffer

18-23
Address

Address
Decoder

I/O Mux

SRAM Array

Collateral

8, 16, 32
Data
ERR

Datasheet: Async SRAM with ECC datasheets

Sense
Amps

ECC
Decoder

Control Logic

CE

OE

WE

BHE3

BLE4

Availability
1

More Battery Life


Error-correcting code
3 Byte high enable
4 Byte low enable
2

Document No. 001-89435 Rev. *L

Sampling:
Production:

Now
Now
Product Overview 118

Fast SRAM Family with PowerSnooze1


Applications

Family Table

Programmable logic controllers


Handheld devices
Multifunction printers
Automotive
Computation servers

Features
Access time: 10 ns
PowerSnooze: Additional power-saving (deep-sleep) mode
Deep-sleep current: 15 A for 4Mb (see Family Table)
Bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Industrial and automotive temperature grades
Industry-standard, RoHS-compliant packages
Error-Correcting Code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors

Density

MPN

Access Time

4Mb
16Mb

CY7S104x
CY7S106x

10 ns
10 ns

Deep Sleep Current


(Maximum at 85C)
15 A
22 A

Block Diagram
Fast SRAM with PowerSnooze
ECC
Encoder

20
Address

Address
Decoder

Collateral
Datasheet: Async SRAM with ECC datasheets

DS2

8, 16, 32
Data
ERR

I/O Mux

SRAM Array

Power
Management
Block
(Enables
PowerSnooze)

Input
Buffer

Sense
Amps

ECC
Decoder

Control Logic

CE

OE

WE BHE3 BLE4

Availability
1

A Fast SRAM with a deep-sleep mode in addition to a conventional standby mode.


For example, the 12-ns 16Mb offering has a deep-sleep current of 1.37 A/Mb and a
standby current of 1.87 mA/Mb
2 Deep-sleep
3 Byte high enable
4 Byte low enable

Document No. 001-89435 Rev. *L

Sampling:
Production:

Now
Now

Product Overview 119

Synchronous SRAMs

Document No. 001-89435 Rev. *L

120

Synchronous SRAM Portfolio

High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth


Standard Sync
and NoBL

Standard Sync and


NoBL with ECC2

QDR -II/
DDR-II

QDR-II+/
DDR-II+

QDR-II+X/
DDR-II+X

QDR-IV

Max RTR1: 250 MT/s


Max BW: 18 Gbps
Latency: 1 Cycle
Pipeline and
Flow-through Modes

Max RTR1: 250 MT/s


Max BW: 18 Gbps
Latency: 1 Cycle
Pipeline and
Flow-through Modes

Max RTR1: 666 MT/s


Max BW: 47.9 Gbps
Latency: 1.5 Cycles
CIO3 and SIO4

Max RTR1: 666 MT/s


Max BW: 79.2 Gbps
Latency: 2 or
2.5 Cycles
CIO3and SIO4, ODT5

Max RTR1: 900 MT/s


Max BW: 91.1 Gbps
Latency: 2.5 Cycles
SIO4, ODT5

Max RTR1: 2.1 GT/s


Max BW: 153.5 Gbps
Latency: 5 or 8 Cycles
Dual-Port Bidirectional
ODT5

CY7C161/2xKV18
144Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4

CY7Cx4/5/6/7xKV18
144Mb; 300-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C151/2xKV18
72Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4

CY7Cx54/5/6/7KV18
72Mb; 250-550 MHz
1.8 V; x18, x36
RH6; Burst 2, 4

CY7C156/7xXV18
72Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C141/2xKV18
36Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36
Burst 2, 4

CY7Cx24/5/6/7xKV18
36Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C126/7x
36Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C131/2/9xKV18
18Mb; 250-333 MHz
1.8 V; x8, x18, x36
Burst 2, 4

CY7Cx14/5/6/7xKV18
18Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C147/8xB
72Mb; 133-250 MHz
2.5, 3.3 V; x18, x36

Density

NEW

CY7C144/6xK
36Mb; 133-250 MHz
2.5, 3.3 V; x36, x72

CY7C144/6xK
36Mb; 133-250 MHz
2.5, 3.3 V; x18, x36
NEW

CY7C137/8xD/K
18Mb; 100-250 MHz
3.3 V; x18, x32, x36

CY7C137/8xK
18Mb; 100-250 MHz
2.5, 3.3 V; x18, x36

CY7C135/6xC
9Mb; 100-250 MHz
3.3 V; x18, x32, x36
Auto E7

NEW

CY7C41xKV13
144Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2

NEW

CY7C40xKV13
72Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2

CY7C1911xKV18
18Mb; 250-333 MHz
1.8 V; x9
Burst 2, 4

CY7C134/2xG
2,4Mb; 100-250 MHz
3.3 V; x18, x32, x36

Random Transaction Rate


1 Rate

of truly random accesses to


memory, expressed in transactions
per second (MT/s, GT/s)

Document No. 001-89435 Rev. *L

2 Error-correcting
3 Common

I/O
4 Separate I/O

code

5 On-die

termination; parts are CY7C2x


hardened, military grade
7 AEC-Q100 -40C to +125C
6 Radiation

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

2121

QDR-IV Product Overview


Family Table

Switches and routers


High-performance computing
Military and aerospace systems
Test and measurement

Density

MPN

Max Freq

RTR

QDR-IV HP

72Mb
144Mb

CY7C40x1KV13
CY7C41x1KV13

667 MHz

1,334 MT/s

QDR-IV XP

72Mb
144Mb

CY7C40x2KV13
CY7C41x2KV13

1,066 MHz

2,132 MT/s

Block Diagram

Available in two options: QDR-IV HP (RTR 1,334 MT/s) and


QDR-IV XP (RTR 2,132 MT/s)
Two independent, bidirectional DDR1 data ports
Error-correcting code (ECC) to reduce soft error rate to less
than 0.01 Failure-in-Time (FIT) per megabit
Bus inversion to reduce simultaneous switching I/O noise
On-die termination (ODT) to reduce board complexity
De-skew training to improve signal-capture timing
I/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD2)
Package: 361-pin FCBGA3
Bus widths: x18, x36

Address/
Control
Clock

QDR-IV

Data Valid

x2

x18, x36
Data Port A

Address Interface

x2

x2

SRAM Array

Impedance Matching

1 Double

x21,x22

x2

ODT

Datasheet:

Address Parity
Parity Error

ECC

Data Clocks x2

Bus Inversion

Collateral

Bus
Address
Inversion
Port

x2

Data Port A
(HSTL/SSTL or POD)

Features

Option

Data Port B
(HSTL/SSTL or POD)

Applications

Control
Logic
Control

x4

x2

Data Clocks

Data Valid

x18, x36
Data Port B

x2

Bus Inversion

Test
Engine
JTAG Interface

Availability
QDR-IV datasheets

Data Rate: two data transfers per clock cycle

Document No. 001-89435 Rev. *L

Sampling:
Production:
2 Pseudo

Now
Now

open drain: Signaling interface that uses strong pull-down and weak pull-up drive strength

3 Flip-chip

ball grid array


3122

Nonvolatile RAM

Document No. 001-89435 Rev. *L

123

nvSRAM Portfolio
High Density | High Speed
6 nvSRAM
SPILPC
nvSRAM

I2C nvSRAM

CY14B116R/S
16Mb; 3.0 V
25, 45 ns; x32; Ind1
RTC2

CY14B116K/L
16Mb; 3.0 V
25, 45 ns; x8; Ind1
RTC2

CY14V116F/G
16Mb; 3.0, 1.8 V I/O
30 ns; ONFI3 1.0
x8, x16; Ind1

Higher Densities
nvSRAM
NDA Required
Contact Sales

CY14B104NA
4Mb; 3.0 V
25, 45 ns; x16
Auto E4; RTC2

CY14B108K/L
8Mb; 3.0 V
25, 45 ns; x8; Ind1
RTC2

CY14B108M/N
8Mb; 3.0 V
25, 45 ns; x16; Ind1
RTC2

CY14B116M/N
16Mb; 3.0 V
25, 45 ns; x16; Ind1
RTC2

CY14B104K/LA
4Mb; 3.0 V
25, 45 ns; x8; Ind1
RTC2

CY14V104LA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x8; Ind1

CY14B104M/NA
4Mb; 3.0 V
25, 45 ns; x16; Ind1
RTC2

CY14V104NA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x16; Ind1

CY14V101PS
1Mb; 3.0, 1.8 V I/O
108 MHz QSPI7; Ind1
Ext. Ind8; RTC2

CY14V101QS
1Mb; 3.0, 1.8 V I/O
108 MHz QSPI7; Ind1
Ext. Ind8

CY14B101I
1Mb; 3.0 V
3.4 MHz I2C; Ind1
RTC2

CY14B101KA/LA
1Mb; 3.0 V
25, 45 ns; x8; Ind1
RTC2

CY14V101LA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x8; Ind1

CY14B101MA/NA
1Mb; 3.0 V
25, 45 ns; x16; Ind1
RTC2

CY14V101NA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x16; Ind1

CY14B101PA
1Mb; 3.0 V
40 MHz SPI; Ind1
RTC2

CY14B512P
512Kb; 3.0 V
40 MHz SPI; Ind1
RTC2

CY14B512I
512Kb; 3.0 V
3.4 MHz I2C; Ind1
RTC2

CY14B256KA/LA
256Kb; 3.0 V
25, 45 ns; x8; Ind1
RTC2

CY14V/U256LA
256Kb; 3.0, 1.8V I/O
35 ns; x8; Ind1

CY14E256LA
256Kb; 5.0 V
25, 45 ns; x8; Ind1

STK14C88-5
256Kb; 5.0 V
35, 45 ns; x8; Mil5

CY14B256PA
256Kb; 3.0 V
40 MHz SPI; Ind1
RTC2

CY14B256I
256Kb; 3.0 V
3.4 MHz I2C; Ind1
RTC2

STK11C68-5
64Kb; 5.0 V
35, 55 ns; x8; Mil5

STK12C68-5
64Kb; 5.0 V
35, 55 ns; x8; Mil5

CY14B064PA
64Kb; 3.0 V
40 MHz SPI; Ind1
RTC2

CY14B064I
64Kb; 3.0 V
3.4 MHz I2C; Ind1
RTC2

64Kb - 256Kb

512Kb - 16Mb

Parallel Parallel
nvSRAM
nvSRAM

grade 40C to +85C


clock
3 Open NAND flash interface

40C to +125C
Military grade 55C to +125C
6 Low-pin-count

1 Industrial

4 AEC-Q100

2 Real-time

Document No. 001-89435 Rev. *L

Higher Densities
nvSRAM
NDA Required
Contact Sales

Quad serial peripheral interface


Extended Industrial grade 40C to +105C

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

124

F-RAM Portfolio
Low Power | High Endurance
Processor
Companion

4Kb - 256Kb

512Kb - 8Mb

LPC1 F-RAM
FM25H20/V20A
2Mb; H20: 2.7-3.6 V
V20A: 2.0-3.6 V
40 MHz SPI; Ind2
CY15B102Q
2Mb; 2.0-3.6 V
25 MHz SPI; Auto E3

Wireless
Memory

Higher Densities
F-RAM
NDA Required
Contact Sales

CY15B104Q
4Mb; 2.0-3.6 V
40 MHz SPI; Ind2

FM22L16/LD16
4Mb; 2.7-3.6 V
55 ns; x8; Ind2

FM25V10/VN10
FM24V10/VN10
1Mb; 2.0-3.6 V
1Mb; 2.0-3.6 V
40 MHz SPI; Ind2, Auto A3 3.4 MHz I2C; Ind2 , Auto A3

FM25V05
512Kb; 2.0-3.6 V
40 MHz SPI; Ind2, Auto A3

FM24V05
512Kb; 2.0-3.6 V
3.4 MHz I2C; Ind2 , Auto A3

FM25V02A/W256
256Kb; V02A: 2.0-3.6 V
W256: 2.7-5.5 V
40 MHz SPI; Ind2, Auto A3

FM24V02A/W256
FM33256
256Kb; V02A: 2.0-3.6 V 256Kb; 3.3V; 16 MHz SPI
W256: 2.7-5.5 V
Ind2; RTC5; Power Fail
3.4 MHz I2C; Ind2, Auto A3
Watchdog; Counter

FM25V01A
128Kb; 2.0-3.6 V
40 MHz SPI; Ind2, Auto A3

FM24V01A
128Kb; 2.0-3.6 V
3.4 MHz I2C; Ind2, Auto A3

FM31256/31(L)278
256Kb; 3.3, 5.0V; 1 MHz
I2C; Ind2; RTC5; Power
Fail; Watchdog; Counter

FM25640/CL64
64Kb; 3.3, 5.0 V
20 MHz SPI; Ind2, Auto E4

FM24C64/CL64
64Kb; 3.3, 5.0 V
1 MHz I2C; Ind2, Auto E4

FM3164/31(L)276
64Kb; 3.3, 5.0 V; 1 MHz
I2C; Ind2; RTC5; Power
Fail; Watchdog; Counter

FM25C160/L16
16Kb; 3.3, 5.0 V
20 MHz SPI; Ind2, Auto E4

FM24C16/CL16
16Kb; 3.3, 5.0 V
1 MHz I2C; Ind2 , Auto A3

FM25040/L04
4Kb; 3.3, 5.0 V
20 MHz SPI; Ind2, Auto E4

FM24C04/CL04
4Kb; 3.3, 5.0 V
1 MHz I2C; Ind2 , Auto A3
40C to +125C
clock

4 AEC-Q100

5 Real-time

Low-pin-count
Industrial grade 40C to +85C
3 AEC-Q100 40C to +85C

Document No. 001-89435 Rev. *L

Parallel F-RAM

Wireless Memory
NDA Required
Contact Sales

FM28V102A
1Mb; 2.0-3.6 V
60 ns; x16; Ind2

FM28V202A
2Mb; 2.0-3.6 V
60 ns; x16; Ind2

CY15B101N
1Mb; 2.0-3.6 V
60 ns; x16; Auto A3

CY15B102N
2Mb; 2.0-3.6 V
60 ns; x16; Auto A3

FM28V020
256Kb; 2.0-3.6 V
70 ns; x8; Ind2

FM18W08
256Kb; 2.7-5.5 V
70 ns; x8; Ind2

FM1808B
256Kb; 5.0 V
70 ns; x8; Ind2

FM16W08
64Kb; 2.7-5.5 V
70 ns; x8; Ind2

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

125

nvSRAM Packages
Family

32-pin
SOIC

44-pin
TSOP
II

48-ball
FBGA

48-pin
SSOP

4Mb

8Mb

16Mb

28-pin
SOIC

28-pin
CDIP

28-pad
LCC

64Kb

256Kb

Density

8-pin
SOIC

8-pin
DFN

16-pin
SOIC

1Mb
Parallel

64Kb

256Kb

512Kb

1Mb

64Kb

LPC

Document No. 001-89435 Rev. *L

512Kb

Wafer

1Mb

165ball
FBGA

256Kb
I2C

48-pin 54-pin 60-ball


TSOP I TSOPII FBGA

126

F-RAM Packages
Family

LPC

I2C

8-pin
SOIC

8-pin
DFN

4Kb

16Kb

64Kb

128Kb

256Kb

512Kb

1Mb

Density

14-pin
SOIC

28-pin
SOIC

28-pin
TSOP I

32-pin
TSOP I

44-pin
TSOP II

48-ball
FBGA

Wafer

2Mb

4Mb

4Kb

16Kb

64Kb

128Kb

256Kb

512Kb

1Mb

64Kb
Processor
Companion 256Kb

Parallel

8-pin
EIAJ

64Kb

256Kb

2Mb

4Mb

1Mb

Document No. 001-89435 Rev. *L

127

1Mb Quad SPI nvSRAM


Applications

Block Diagram

Computing and networking


Industrial automation
RAID storage

VCAP2

1Mb Quad SPI


nvSRAM
Store

Control

Features
QSPI I/Os

Quad SPI interface: 108 MHz


Unlimited write endurance
One million store cycles on power fail
Data retention of 20 years at 85C
Operating voltages: 3.0 V, 1.8-V I/O
Low standby (280-A) and sleep (10-A) currents
Industrial temperature range: -40C to +85C
Extended Industrial temperature range: -40C to +105C
Integrated, high-accuracy real-time clock (RTC)
Package: 16-SOIC

Control
Logic

Store/Recall
Control

SRAM Array
I/O
Control

Recall
Software
Command
Detect

XIN1
XOUT1

RTC

VRTC

HSB3

Availability

Collateral
Final Datasheet: CY14V101QS

Sampling:
Production:
1
2

Document No. 001-89435 Rev. *L

Power
Control

SONOS Array

Now
Now

Crystal connections
External capacitor connection

3 Hardware

store busy

128

Timing Solutions

Document No. 001-89435 Rev. *L

129

Timing Solutions Portfolio


Programmable | High-Performance | EMI Reduction | Automotive
Clock Generators
EMI Reduction

Standard
Performance

High
Performance

NEW

CY274x
Max. Frequency: 700 MHz
12 Outputs; PCIe 3.0; 4 PLL
0.7-ps RMS Jitter1; Ind2; Auto A3

NEW

2-PLL Clock Generator


Max. Frequency: 700 MHz
0.7-ps RMS Jitter1
Contact Sales

Clock Buffers

Non-EMI Reduction
NEW

NEW

Q316
CY294x/ CY5107
Max. Frequency: 2.1 GHz
1 Output; 40/100 GbE; 1 PLL
0.15-ps RMS Jitter1; Ind2

PLL ICs

Zero/Non-Zero Delay Buffer

MB15F63UL
Max. Input Frequency: 2 GHz
Sigma-Delta and Integer PLL;
-88.5 dBc/Hz CNR8; Ind2;
CY2DLx/DMx/DPx/CPx
Max. Frequency: 1.5 GHz
2-10 Outputs; LVDS, LVPECL, CML
0.05-ps RMS Jitter1; Ind2

4-PLL Clock Generator


Max. Frequency: 2.1 GHz
0.15-ps RMS Jitter1
Contact Sales

CY2Xx (FleXO)
Max. Frequency: 690 MHz
1 Output; Frequency Margining
0.6-ps RMS Jitter1; Ind2
CY254x/CY251x
Max. Frequency: 166 MHz
3-9 Outputs; 1-4 PLL; I2C
100-ps CCJ4; Ind2

CY2239x/CY229x/CY2238x
Max. Frequency: 200 MHz
3-6 Outputs; 3-4 PLL; I2C
400-ps CCJ4; Ind2; Auto E5

MB15E07SL/05SL/03SL
Max. Input Frequency: 2.5GHz
1 PLL; < 4mA PSC7 ; Ind2;

CY230x/EP0x
Max. Frequency: 220 MHz
5-9 Outputs; LVCMOS
22-ps CCJ4; Ind2; Auto A3

CY22800/801/2429x
Max. Frequency: 200 MHz
2-4 Outputs; 1 PLL; PCIe 1.1
250-ps CCJ4; Ind2; Auto A3

CY22050/150
Max. Frequency: 200 MHz
3-6 Outputs; 1 PLL
250-ps CCJ4; Ind2

MB15E07SR/06SR/05SR
Max. Input Frequency: 3GHz
1 PLL; -86 dBc/Hz CNR8 ; Ind2

CY230xNZ
Max. Frequency: 133 MHz
4-18 Outputs; LVCMOS
250-ps CCJ4; Ind2

MB88151Ax/2Ax/3Ax/4Ax
Max. Frequency: 134 MHz
1 Output; 1 PLL;
< 200-ps CCJ4; Ind2;

MB15F78UL/73UL/72UL
Max. Input Frequency: 2.6 GHz
2 PLL; < 2.8 mA PSC7; Ind2;

CY23S02/05/08/09/FP12
Max. Frequency: 200 MHz
2-12 Outputs; Spread Aware
200-ps CCJ4; Ind2

MB88155x
Max. Frequency: 80 MHz
1 Output; 1 PLL;
< 200-ps CCJ4; Ind2;

MB15F07SL
Max. Input Frequency: 1.1 GHz
2 PLL; < 5 mA PSC7; Ind2;

CY7B99x (RoboClock)
Max. Frequency: 200 MHz
8-18 Outputs; Configurable Skew
50-ps CCJ4; Ind2

2 Industrial

Integrated phase noise across 12-kHz to 20-MHz offset


grade: -40C to +85C
3 AEC-Q100: -40C to +85C
4 Cycle-to-cycle jitter

Document No. 001-89435 Rev. *L

AEC-Q100: -40C to +125C


Automatic clock switching on failure of a clock source
7 Power supply current
8 Carrier-to-noise ratio

Production Sampling Development Concept


Status
Availability

QQYY

QQYY

130

CY294x: High-Performance 1-PLL


Programmable Oscillator
Applications

Block Diagram

Routers
Switches
Base stations
Storage area networks
Network backplanes
Wireless infrastructure
Military/Aerospace
Test and measurement
Video

High-Performance Programmable Oscillator

Crystal
Oscillator
PLL

Features
High frequency: 2,100-MHz differential, 250-MHz single-ended
LVPECL1, LVDS2, HCSL3 and CML4 outputs
RMS phase jitter5 ~110 fs (typical) at all output frequencies
Frequency select to choose from four preprogrammed
configurations
Voltage-controlled frequency synthesis (VCFS) with tunable
pull range of 50 ppm to 275 ppm
Pin select and I2C programming
VDD support: 1.8 V, 2.5 V and 3.3 V
Operating temperature range from -40C to +85C
Available in a 5 mm x 7 mm, 5 mm x 3.2 mm LCC package

SCLK6
SDAT6
VIN7
FS18
FS08

Preliminary Datasheet: Contact Sales

OUT1P
OUT1N

Memory
and
Control
Logic

Sampling:
Production:

Now
Q3 2016

8 Frequency

Document No. 001-89435 Rev. *L

Output
Bank

Availability

Collateral

Low-voltage positive emitter coupled logic


Low-voltage differential signaling
3 High-speed current steering logic

Divider

Current mode logic


The uncertainty of the clock rising and falling edge timing
6 I2C input

Voltage input pin for VCFS


select inputs

131

Specialty Memory

Document No. 001-89435 Rev. *L

132

Specialty Memory Portfolio


Intelligent Memory | High Density | High Throughput
Dual-Port SRAM
Asynchronous

FIFO
Synchronous

Asynchronous

Synchronous

2 Mb-72 Mb

CYFB0072V4
72Mb; 1.8, 3.3 V
133 MHz
x36; Ind1
CYD02/9/18/36SxxV18
22Mb,
Mb, 99Mb,
Mb, 18
Mb,36Mb;
36 Mb;1.8
1.8VV
18Mb,
167 MHz, 200 MHz
x18, x36, x72; Ind1

CYFX18V/36V/72V
18Mb, 36Mb, 72Mb; 1.8, 3.3 V
100 MHz, 133 MHz
x9 to x36 Prog3; Ind1

2 Kb-64 Kb

128 Kb-1 Mb

CY7C083x/5x
2Mb, 4Mb, 9Mb, 18Mb; 3.3 V
100 MHz, 133 MHz, 167 MHz
x18, x36, x72; Ind1
CY7C02x/3x/5x
512Kb, 1Mb; 3.3, 5.0 V
12 ns, 15 ns, 20 ns, 25 ns
x8, x16, x18, x36; Ind1

CY7C09279/289/389/579
512Kb, 1Mb; 3.3 V
7, 9, 12 ns; 83 MHz, 100 MHz
x8, x16, x18, x36; Ind1

CY7C4275/81/85/91
512Kb, 1Mb; 3.3 V
67 MHz, 100 MHz
x9, x18; Ind1

CY7C006/025/026
128Kb, 256Kb; 3.3, 5.0 V
15 ns, 20 ns, 25 ns, 55 ns
x8, x16, x18; Ind1

CY7C09269/369
256Kb; 3.3 V
9 ns, 12 ns
x16, x18; Ind1

CY7C4255/61/65/71
128Kb, 256Kb; 3.3, 5.0 V
67 MHz, 100 MHz
x9, x18; Ind1

CY7C024/144
64Kb; 3.3, 5.0 V
15 ns, 20 ns, 25 ns, 55 ns
x8, x16, x18; Ind1

CY7C09159/349
64Kb; 3.3 V
9 ns, 12 ns
x9, x18; Comm2

CY7C421
4Kb; 5.0 V
15 ns, 20 ns
x9; Ind1

CY7C13x
8Kb, 16Kb, 32Kb; 5.0 V
15 ns, 25 ns, 55 ns
x8; Ind1

Industrial grade: -40C to +85C


Commercial grade: 0C to +70C
3 Programmable bus width
2

Document No. 001-89435 Rev. *L

CY7C4201/11
2Kb, 4Kb; 3.3 V
67 MHz
x9; Ind1
4

Production Sampling Development Concept

CYFB denotes Video Frame Buffer products


Status
Availability

QQYY

QQYY

133

Flash Memory

Document No. 001-89435 Rev. *L

134

NOR Flash Memory Family Decoder


S 29 G L 128 S

Document No. 001-89435 Rev. *L

Technology:

J = 110 nm Floating Gate


K = 90 nm Floating Gate
L = 65 nm Floating Gate

N = 110 nm MirrorBit
P = 90 nm MirrorBit
R, S = 65 nm MirrorBit
T = 45 nm MirrorBit

Density:

008 = 8Mb
016 = 16Mb
032 = 32Mb
064 = 64Mb

128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb

02G = 2Gb
0BG = 32Gb
04G = 4Gb
0CG = 64Gb
08G = 8Gb
0AG = 16Gb

Voltage:

D = 2.5V

L = 3.0V

S = 1.8V

Family:

A = Standard ADP (Address-Data Parallel)


C = Burst Mode ADP (Address-Data Parallel)
F = Serial
G = Page Mode
J = Simultaneous Read/Write ADP (Address-Data Parallel)
K = HyperBus
N = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
P = Page Mode Simultaneous Read/Write ADP (Address-Data Parallel)
V = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
W = Burst Mode Simultaneous Read/Write ADP (Address-Data Parallel)
X = Burst Mode Simultaneous Read/Write AADM (Address-Address-Data
Multiplexed)

Series:

25 = SPI
29 = NOR

Prefix:

26 = HyperFlash
70 = Stacked Die

1 = 63 nm DRAM

27 = HyperRAM
79 = Dual Quad SPI

Product Selector Guide 135

Parallel NOR Flash Memory Portfolio


S29AS-J
110 nm, 1.8 V

S29AL-J
110 nm, 3.0 V

S29JL-J1
110 nm, 3.0 V

S29PL-J1, 2
110 nm, 3.0 V

S29GL-N2
110 nm, 3.0 V

All parts supported by


Longevity Program
unless noted

128Mb
60 ns / 20 ns
* I, A

32Mb

64-128Mb

256Mb

Density
Initial / Page Access
* Temp Range

16Mb
70 ns / -* I, A

16Mb
55 ns / -* I, A, N, M

8Mb
70 ns / -* I, A

8Mb
55 ns / -* I, A, N, M

* I = Industrial: -40C to +85C


A = Industrial, AEC-Q100: -40C to +85C
V = Industrial-plus: -40C to +105C
B = Industrial-plus, AEC-Q100: -40C to +105C

Document No. 001-89435 Rev. *L

64Mb
55 ns / -* I, A

64Mb
55 ns / 20 ns
* I, A

64Mb
90 ns / 25 ns
* I, A

32Mb
60 ns / -* I, A

32Mb
55 ns / 20 ns
* I, A

32Mb
90 ns / 25 ns
* I, A

N = Extended: -40C to +125C


M = Extended, AEC-Q100: -40C to +125C
1 Supports Simultaneous Read/Write Operation
2 Supports Page Mode
3 S70 series (stacked die)

S29GL-P2
90 nm, 3.0 V

S29GL-S2
65 nm, 3.0 V

S29GL-T2
45 nm, 3.0 V

2Gb3 Q317
110 ns / 25 ns
*I

2Gb3
110 ns / 20 ns
* I, A, V, B

Q316
2Gb3
110 ns / 20 ns
* I, A, V, B, N, M

Q317
1Gb
110 ns / 25 ns
*I

1Gb
100 ns / 15 ns
* I, A, V, B

1Gb
100 ns / 15 ns
* I, A, V, B, N, M

512Mb Q317
100 ns / 25 ns
*I

512Mb
100 ns / 15 ns
* I, A, V, B

512Mb
100 ns / 15 ns
* I, A, V, B, N, M

256Mb
90 ns / 25 ns
*I

256Mb
90 ns / 15 ns
* I, A, V, B

128Mb
90 ns / 25 ns
*I

128Mb
90 ns / 15 ns
* I, A, V, B
64Mb
70 ns / 15 ns
* I, A, B, N

Concept Development Sampling


Status
Availability
EOL (Last-Time-Ship)

QQYY

Production
QQYY
QQYY

136

S29WS-P1
90 nm, 1.8 V

S29NS-P2
90 nm, 1.8 V

S29VS-R2
65 nm, 1.8 V

S29XS-R3
65 nm, 1.8 V

Density
Initial Access / SDR Clock
* Temp Range

All parts supported by


Longevity Program
unless noted

512Mb
80 ns / 104 MHz
*W

512Mb
80 ns / 83 MHz
*W

256Mb
80 ns / 104 MHz
*W

256Mb
80 ns / 108 MHz
* W, I

256Mb
80 ns / 108 MHz
* W, I

128Mb
80 ns / 104 MHz
*W

128Mb
80 ns / 108 MHz
* W, I

128Mb
80 ns / 108 MHz
* W, I

64Mb
80 ns / 108 MHz
* W, I

64Mb
80 ns / 108 MHz
* W, I

32Mb

64-128Mb

256Mb

Burst NOR Flash Memory Portfolio

* W = Wireless: -25C to +85C


I = Industrial: -40C to +85C
A = Industrial, AEC-Q100: -40C to +85C
N = Extended: -40C to +125C
M = Extended, AEC-Q100: -40C to +125C

Document No. 001-89435 Rev. *L

H = Hot: -40C to +145C


T = Hot, AEC-Q100: -40C to +145C
1 ADP (Address Data Parallel) Burst
2 ADM (Address Data Multiplex) Burst
3 AADM (Address high, Address low, Data Multiplex) Burst

S29CD-J1
110 nm, 2.5 V

S29CL-J1
110 nm, 3.0 V

32Mb
54 ns / 75 MHz
* I, A, N, M, H, T

32Mb
54 ns / 75 MHz
* I, A, N, M, H, T

16Mb
54 ns / 66 MHz
* I, A, N, M, H, T

16Mb
54 ns / 66 MHz
* I, A, N, M, H, T

Concept Development Sampling


Status
Availability
EOL (Last-Time-Ship)

QQYY

Production
QQYY
QQYY

137

SPI NOR Flash Memory Portfolio


S25FL1-K
90 nm, 3.0 V
4KB2

S25FL-L
65 nm, 3.0 V
4KB2

S25FL-P
90 nm, 3.0 V
>4KB2

Density
SDR Clock / DDR Clock
* Temp Range
All parts supported by
Longevity Program
unless noted

64-128Mb

256Mb

S25FL2-K1
90 nm, 3.0 V
4KB2

64Mb
108 MHz / -* I, A, V, B, N4, M4

S79FL-S3
65 nm, 3.0 V
>4KB2

S25FS-S
65 nm, 1.8 V
>4KB2

1Gb5
133 MHz / 80 MHz
* I, A, V, B

1Gb
133 MHz / 80 MHz
* I, A, V, B

1Gb5
133 MHz / 80 MHz
* I, A, V, B

512Mb
133 MHz / 80 MHz
* I, A, V, B

512Mb
133 MHz / 80 MHz
* I, A, V, B

512Mb
133 MHz / 80 MHz
* I, A, V, B

256Mb
133 MHz / 80 MHz
* I, A, V, B

256Mb
133 MHz / 80 MHz
* I, A, V, B

256Mb Q416
133 MHz / 66 MHz
* I, A, V, B, N, M

256Mb5
104 MHz / -* I, A

256Mb
133 MHz / 80 MHz
* I, A, V, B, N, M

128Mb
133 MHz / 66 MHz
* I, A, V, B, N, M

128Mb6
104 MHz / -* I, A, V, B

128Mb8
133 MHz / 80 MHz
* I, A, V, B, N, M

128Mb7
104 MHz / -* I, A, V, B

128Mb9
108 MHz / -* I, A, V, B

64Mb
108 MHz / 54 MHz
* I, A, V, B, N, M

32Mb
108 MHz / -* I, A, V, B, N4, M4

32Mb

S25FL-S
65 nm, 3.0 V
>4KB2

64Mb
104 MHz / -* I, A, V, B

128Mb
133 MHz / 80 MHz
* I, A, V, B

64Mb
133 MHz / 80 MHz
* I, A, V, B, N, M

32Mb
104 MHz / -* I, A, V, B

16Mb
108 MHz / -* I, A, V, B, N4, M4
Q117
8Mb
76 MHz / -*I

* I = Industrial: -40C to +85C


A = Industrial, AEC-Q100: -40C to +85C
V = Industrial-plus: -40C to +105C
B = Industrial-plus, AEC-Q100: -40C to +105C
N = Extended: -40C to +125C
M = Extended, AEC-Q100: -40C to +125C

Document No. 001-89435 Rev. *L

S25FL2-K Dual SPI


Logical sector size
3 S79 series, Dual Quad SPI (stacked die)
4 Contact Sales
5 S70 series (stacked die)
6 S25FL129P Quad SPI

S25FL128P Dual SPI


S25FL128S 133-MHz SDR / 80-MHz DDR
9 S25FL127S 108-MHz SDR
Status
Availability
EOL (Last-Time-Ship)

Concept Development Sampling


QQYY

Production
QQYY
QQYY

138

HyperFlash and HyperRAM Portfolio


HyperFlash
S26KS-S1
65 nm, 1.8 V

HyperFlash
S26KL-S1
65 nm, 3.0 V

HyperRAM
S27KS-12
63 nm, 1.8 V

HyperRAM
S27KL-12
63 nm, 3.0 V

256Mb3
Contact Sales

Density
Initial Access / DDR Clock
* Temp Range

64-128Mb

256Mb

All parts supported by


Longevity Program
unless noted

1Gb3
96 ns / 166 MHz
* I, A, V, B, N, M

1Gb3
96 ns / 100 MHz
* I, A, V, B, N, M

512Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4

512Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4

256Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4

256Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4

256Mb3
Contact Sales

128Mb
96 ns / 166 MHz
* I, A, V, B, N4, M4

128Mb
96 ns / 100 MHz
* I, A, V, B, N4, M4

128Mb3
Contact Sales

* C = Commercial: -0C to +70C


I = Industrial: -40C to +85C
A = Industrial, AEC-Q100: -40C to +85C
V = Industrial-plus: -40C to +105C
B = Industrial-plus, AEC-Q100: -40C to +105C

Document No. 001-89435 Rev. *L

Q416

Q316
64Mb
36 ns / 166 MHz
* I, A, V, B

N = Extended: -40C to +125C


M = Extended, AEC-Q100: -40C to +125C
1 S26 = HyperFlash
2 S27 = HyperRAM
3 S70 series (stacked die)
4 Contact sales

Q416

128Mb3
Contact Sales
Q316
64Mb
36 ns / 100 MHz
* I, A, V, B

Concept Development Sampling


Status
Availability
EOL (Last-Time-Ship)

QQYY

Production
QQYY
QQYY

139

NAND and e.MMC Family Decoder


NAND
S 34 M L 08G 2
Technology: 1 = 4x nm

2 = 32 nm

3 = 16 nm

Density:

01G = 1Gb
02G = 2Gb

04G = 4Gb
08G = 8Gb

16G = 16Gb

Voltage:

L = 3.0V

S = 1.8V

Family:

M = NAND (Address-Data Multiplexed)


S = SecureNAND (Address-Data Multiplexed)

Series:

34 = NAND

Prefix:

e.MMC
S 40 41 016 1 B1
Controller: B1 = e.MMC 4.51
Revision:

1 = NAND MLC1 19 nm

Density:

008 = 8GB
016 = 16GB

Controller Architecture:

1 Multi-level

B2 = e.MMC 5.1
2 = NAND MLC1 15 nm

032 = 32GB
064 = 64GB
41 = e.MMC

Series:

40 = Managed Memory

Prefix:

cell

Document No. 001-89435 Rev. *L

Product Selector Guide

140

SLC NAND Portfolio


S34ML-11
4x nm, 3.0 V
SLC, ONFI 1.04

S34MS-11
4x nm, 1.8 V
SLC, ONFI 1.04

S34ML-22
32 nm, 3.0 V
SLC, ONFI 1.04

S34MS-22
32 nm, 1.8 V
SLC, ONFI 1.04

16Gb; x8
40 MBps
* I, A5, V5, B5

S34SL-22, 3
32 nm, 3.0 V
SLC, ONFI 1.04

S34ML-31
16 nm, 3.0 V
SLC, ONFI 1.04

S34MS-31
16 nm, 1.8 V
SLC, ONFI 1.04

16Gb; x8
40 MBps
* I, A5, V5, B5

16Gb; x8
40 MBps
* I, A, V, B

16Gb; x8
40 MBps
* I, A, V, B

8Gb; x8
40 MBps
* I, A, V, B

8Gb; x8
40 MBps
* I, A, V, B

8Gb; x8
40 MBps
* I, A, V, B

8Gb; x8
40 MBps
* I, A, V, B

1Gb-4Gb

8Gb-16Gb

Density; Bus Width


Interface Bandwidth
* Temp Range
All parts supported by
Longevity Program
unless noted

8Gb; x8 Q218
40 MBps
* I, A, V5, B

4Gb; x8/16
40 MBps
* I, A, V , B

Q218

4Gb; x8
40 MBps
* I, A5, V, B

Q218

4Gb; x8/16
40 MBps
* I, A, V, B

4Gb; x8/16
40 MBps
* I, A, V, B

4Gb; x8
40 MBps
* I, V

4Gb; x8
40 MBps
* I, A, V, B

4Gb; x8
40 MBps
* I, A, V, B

2Gb; x8/16
40 MBps
* I, A, V, B

Q218

2Gb; x8/16
40 MBps
* I, A5, V, B

Q218

2Gb; x8/16
40 MBps
* I, A5, V5, B5

2Gb; x8/16
40 MBps
* I, A5, V5, B5

2Gb; x8
40 MBps
* I, V5

2Gb; x8
40 MBps
* I, A, V, B

2Gb; x8
40 MBps
* I, A, V, B

1Gb; x8
40 MBps
* I, A, V, B

Q218

1Gb; x8/16
40 MBps
* I, A5, V, B

Q218

1Gb; x8/16
40 MBps
* I, A, V, B

1Gb; x8/16
40 MBps
* I, A, V, B

1Gb; x8
40 MBps
* I, V

1Gb; x8
40 MBps
* I, A, V, B

1Gb; x8
40 MBps
* I, A, V, B

Status
Availability
EOL (Last-Time-Ship)

Concept Development Sampling

* I = Industrial: -40C to +85C


A = Industrial, AEC-Q100: -40C to +85C
V = Industrial-plus: -40C to +105C
B = Industrial-plus, AEC-Q100: -40C to +105C

Document No. 001-89435 Rev. *L

1 1-bit

Error-Correcting Code (ECC)


Error-Correcting Code (ECC)
3 SecureNAND: Cypresss SLC NAND Flash Memory with
full-capacity Volatile and Nonvolatile Block Protection
4 Open NAND Flash Interface
5 Contact Sales
2 4-bit

QQYY

Production
QQYY
QQYY

141

e.MMC Portfolio
S4041-1B1
19 nm, 3.0-V
MLC, e.MMC1 4.51

S4041-2B2
15 nm, 3.0-V
MLC, e.MMC1 5.1

32GB-64GB

Density; Bus Width


Interface Bandwidth
* Temp Range
64GB; x8
400 MBps
* I, A

8GB-16GB

32GB; x8
400 MBps
* I, A

16GB; x8
200 MBps
* W, I

Q117

16GB; x8
400 MBps
* I, A

8GB; x8
200 MBps
* W, I

Q117

8GB; x8
400 MBps
* I, A

Concept Development Sampling


*W = Embedded: -25C to +85C
I = Industrial: -40C to +85C
A = Industrial, AEC-Q100: -40C to +85C

Document No. 001-89435 Rev. *L

e.MMC = Embedded Multi Media Card

Status
Availability
EOL (Last-Time-Ship)

QQYY

Production
QQYY
QQYY

142

Flash and RAM MCP Decoder


S 71 N S 512 R D
RAM Density:

A = 16Mb

B = 32Mb

C = 64Mb

D = 128Mb

E = 256Mb

Flash Technology: N = 110 nm MirrorBit

P = 90 nm MirrorBit

R, S = 65 nm MirrorBit

Flash Density:

032 = 32Mb
064 = 64Mb

128 = 128Mb
256 = 256Mb

512 = 512Mb
01G = 1Gb

Voltage:

L = 3.0V

Family:

Series:

G = Page Mode
K = HyperFlash
N = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
V = Burst Mode Simultaneous Read/Write ADM (Address-Data Multiplexed)
W = Burst Mode Simultaneous Read/Write ADP (Address-Data Parallel)
X = Burst Mode Simultaneous Read/Write AADM (Address-Address-Data Multiplexed)
71, 98 = NOR Flash + pSRAM
72 = NOR Flash + DRAM

Prefix:

Memory Type:

2 = NAND SLC, x16 NAND, x16 LPDDR1, 200 MHz DDR, 1.8 V

RAM Density:

9 = 512Mb

Flash Density:

A = 1Gb

Voltage:

L = 3.0V

Family:

M = NAND

Series:

76 = NAND Flash + DRAM

Prefix:

S = 1.8V

S 76 M S A 9 2

Document No. 001-89435 Rev. *L

S = 1.8V

Product Selector Guide

143

Flash and RAM MCP Memory Portfolio


S71WS-P1
90 nm, 1.8 V
Flash Density
RAM Density
* Temp Range

S71NS-P2
90 nm, 1.8 V

S71VS-R2
65 nm, 1.8 V

S72VS-R3
65 nm, 1.8 V

S72XS-R3
65 nm, 1.8 V

S98GL-N4
110 nm, 3.0 V

S76MS5
3x nm, 1.8 V

S71KS-S6
65nm, 1.8V

S71KL-S6
65nm, 3.0V

All parts supported by


Longevity Program
unless noted

256Mb

1Gb
512Mb
*I
512Mb
64Mb9
* I, A, V, B

512Mb Q316
64Mb9
* I, A, V, B

256Mb
64Mb
*W

256Mb
64Mb9
* I, A, V, B

256Mb
64Mb9
* I, A, V, B

128Mb
64Mb
*W

128Mb
64Mb9
* I, A, V, B

128Mb
64Mb9
* I, A, V, B

512Mb
128Mb
*W

256Mb
256Mb7
*I
256Mb
128Mb
*W

64-128Mb

256Mb
64Mb
*W

256Mb
256Mb
*W

256Mb
256Mb8
* W, I

128Mb
32Mb
*W
64Mb
32Mb
*W

* W = Wireless: -25C to +85C


I = Industrial: -40C to +85C
A = Industrial, AEC-Q100: -40C to +85C
V = Industrial-plus: -40C to +105C
B = Industrial-plus, AEC-Q100: -40C to +105C
1 ADP (Address Data Parallel) Burst
2 ADM (Address Data Multiplex) Burst

Document No. 001-89435 Rev. *L

3 AADM

64Mb
32Mb
*I

(Address high, Address low, Data Multiplex) Burst


Page Mode

4 Parallel,

Concept Development Sampling

5 NAND
6 HyperFlash
7 DRAM

Version 2
Version 1
9 HyperRAM
8 DRAM

Status
Availability
EOL (Last-Time-Ship)

QQYY

Production
QQYY
QQYY

144

Parallel NOR Flash Memory Packages


Family Density Device

48-ball
FBGA

48-ball
FBGA

56-ball
BGA

64-ball
BGA

64-ball
Fortified BGA

(0.8-mm pitch) (0.5-mm pitch) (0.8-mm pitch) (0.8-mm pitch) (1.0-mm pitch)
AS-J
AL-J
JL-J

PL-J

GL-N

GL-P

GL-S

GL-T

S29AS008J

16Mb

S29AS016J

8Mb

S29AL008J

16Mb

S29AL016J

32Mb

S29JL032J

64Mb

S29JL064J

32Mb

S29PL032J

64Mb

S29PL064J

128Mb

S29PL127J

32Mb

S29GL032N

64Mb

S29GL064N

128Mb

S29GL128P

256Mb

S29GL256P

512Mb
1Gb

8Mb

48-pin
TSOP

56-pin
TSOP

KGD

S29GL512P

S29GL01GP

2Gb

S70GL02GP

64Mb

S29GL064S

128Mb

S29GL128S

256Mb

S29GL256S

512Mb

S29GL512S

1Gb

S29GL01GS

2Gb

S70GL02GS

512Mb

S29GL512T

1Gb

S29GL01GT

2Gb

S70GL02GT

Document No. 001-89435 Rev. *L

145

Burst NOR Flash Memory Packages


Family

WS-P

NS-P

VS-R

XS-R

44-ball
FBGA
(0.5-mm pitch)

64-ball
BGA
(0.5-mm pitch)

84-ball Fortified
BGA
(0.8-mm pitch)

80-ball
FBGA
(1.0-mm pitch)

80-pin
PQFP

KGD

S29CD016J

32Mb

S29CD032J

16Mb

S29CL016J

32Mb

S29CL032J

Density

Device

128Mb

S29WS128P

256Mb

S29WS256P

512Mb

S29WS512P

512Mb

S29NS512P

64Mb

S29VS064R

128Mb

S29VS128R

256Mb

S29VS256R

64Mb

S29XS064R

128Mb

S29XS128R

256Mb

S29XS256R

16Mb
CD-J

CL-J

Document No. 001-89435 Rev. *L

146

SPI NOR Flash Memory Packages


Family

Density

Device

FL2-K

8Mb
16Mb
32Mb
64Mb
64Mb
128Mb
256Mb
32Mb
64Mb
128Mb
128Mb
256Mb
128Mb
128Mb
256Mb
512Mb
1Gb
256Mb
512Mb
1Gb
64Mb
128Mb
256Mb
512Mb
1Gb

S25FL208K
S25FL116K
S25FL132K
S25FL164K
S25FL064L
S25FL128L
S25FL256L
S25FL032P
S25FL064P
S25FL128P
S25FL129P
S70FL256P
S25FL127S
S25FL128S
S25FL256S
S25FL512S
S70FL01GS
S79FL256S
S79FL512S
S79FL01GS
S25FS064S
S25FS128S
S25FS256S
S25FS512S
S70FS01GS

FL1-K

FL-L

FL-P

FL-S

FL-S
Dual
Quad

FS-S

SOIC-8
150 mil

SOIC-8
208 mil

UD
UD

SOIC-16
300 mil

UD
UD

CF

USON
4 x 3 mm

WSON
4 x 4 mm

WSON
6 x 5 mm

CF

CF

UD
UD

WSON
8 x 6 mm

VSOP8
208 mil

UD

LGA (CF)

LGA (CF)

CF

BGA24
8 x 6 mm
5 x 5 ball

BGA24
8 x 6 mm
4 x 6 ball

UD
UD

UD
UD

KGD

CF = Contact Factory
UD = Under Development

Document No. 001-89435 Rev. *L

147

HyperFlash and HyperRAM Packages


Family

KS-S

KL-S

KS-1

KL-1

BGA24
8 x 6 mm
5 x 5 ball

KGD

S26KS128S

CF

256Mb

S26KS256S

CF

512Mb

S26KS512S

CF

1Gb

S70KS01GS

128Mb

S26KL128S

CF

256Mb

S26KL256S

CF

512Mb

S26KL512S

CF

1Gb

S70KL01GS

64Mb

S26KS0641

128Mb

S70KS1281

256Mb

S70KS2561

64Mb

S26KL0641

128Mb

S70KL1281

256Mb

S70KL2561

Density

Device

128Mb

CF

CF

CF = Contact Factory

Document No. 001-89435 Rev. *L

148

SLC NAND Packages


Family

ML-1

ML-2

ML-3

MS-1

MS-2

MS-3

Density

Device

1Gb
2Gb
4Gb
8Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
8Gb
16Gb

S34ML01G1
S34ML02G1
S34ML04G1
S34ML08G1
S34ML01G2
S34ML02G2
S34ML04G2
S34ML08G2
S34ML16G2
S34ML01G3
S34ML02G3
S34ML04G3
S34ML08G3
S34ML16G3
S34MS01G1
S34MS02G1
S34MS04G1
S34MS01G2
S34MS02G2
S34MS04G2
S34MS08G2
S34MS16G2
S34MS01G3
S34MS02G3
S34MS04G3
S34MS08G3
S34MS16G3

Document No. 001-89435 Rev. *L

63-ball
BGA
(0.8-mm pitch)

67-ball
BGA
(0.8-mm pitch)

48-pin
TSOP

149

e.MMC and SecureNAND Packages


Family

41-1B1

41-2B2

SL-2

153-ball
FBGA
(0.5-mm pitch)

100-ball
LBGA
(1.0-mm pitch)

S40410081B1

16GB

S40410161B1

8GB

S40410082B2

16GB

S40410162B2

32GB

S40410322B2

64GB

S40410642B2

1Gb

S34SL01G2

2Gb

S34SL02G2

4Gb

S34SL04G2

Density

Device

8GB

Document No. 001-89435 Rev. *L

63-ball
BGA
(0.8-mm pitch)

150

Flash and RAM MCP Memory Packages


56-ball
Very Thin FBGA
(0.5-mm pitch)

56-ball
FBGA
(0.8-mm pitch)

84-ball
FBGA
(0.8-mm pitch)

130-ball
BGA
(0.65-mm pitch)

133-ball
FBGA
(0.5-mm pitch)

Family

Flash
Density

RAM
Density

S71WS-P

256Mb

64Mb

S71NS-P

512Mb

128Mb

256Mb

128Mb

256Mb

64Mb

128Mb

64Mb

128Mb

32Mb

64Mb

32Mb

S72VS-R

256Mb

256Mb

S72XS-R

256Mb

256Mb

S98GL-N

64Mb

32Mb

1Gb

512Mb

128Mb

64Mb

256Mb

64Mb

512Mb

64Mb

128Mb

64Mb

256Mb

64Mb

512Mb

64Mb

S71VS-R

S76MS

S71KS-S

S71KL-S

Document No. 001-89435 Rev. *L

151

APPENDIX

Document No. 001-89435 Rev. *L

152

Cypress 3.0-V 64Mb (S25FL064L)


Quad SPI NOR Flash Memory
Applications

Block Diagram

Set-top boxes
Printers
White goods
Smart meters
Automotive instrument clusters and infotainment systems

64Mb Quad SPI NOR Flash Memory


CS#8
SRAM
SCK8

Features

IO08

Operating voltage range: 2.7 V to 3.6 V


100,000 Program1/Sector Erase2 endurance cycles3
20-year data retention at +55C
SDR4 clock rate: 108-MHz QIO5
DDR6 clock rate: 54-MHz QIO5
Program1 time (256B): 0.70 ms (typical)
Sector Erase2 time (64KB): 400 ms (typical)
Industrial temp range (AEC-Q100 optional): -40C to +85C
Industrial-plus temp range (AEC-Q100 optional): -40C to
+105C
Extended temp range (AEC-Q100 optional): -40C to +125C
Packages: 8-SOIC 208 mil, 8-WSON7 4 mm x 4 mm or 5 mm x
6 mm, 24-ball BGA 6 mm x 8 mm

X/Y
Decoder

Array
Right

IO18
I/O
IO28
IO38

Control
Logic

RD10

Data Path

RESET#9

Collateral
Datasheet:
App Notes:

Array
Left

Availability
S25FL064L
Cypress FL-L SPI NOR Flash Memory

The operation required to change a value 1 to a value 0 in NOR Flash memory


The operation required prior to a NOR Flash Memory Program, in which all the bits
in a Sector are set to value 1
3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it
wears out
4 Single-data-rate: A mode of data transfer in which data is transferred once per clock cycle

Sampling:
Production:

Quad input/output (QIO): An interface that transfers addresses or data on four I/Os simultaneously
Double-data-rate: A mode of data transfer in which data is transferred twice per clock cycle
7 Very, Very Thin, Small-Outline, No-Lead semiconductor package
8 Signals used for standard Quad (x4) SPI interface.
9 RESET# is an optional signal available on 16-SOIC and BGA packages.
10 Read data buffer

Document No. 001-89435 Rev. *L

TBD
TBD

Product Overview 153

Cypress 3.0-V 128Mb (S25FL128L)


Quad SPI NOR Flash Memory
Applications

Block Diagram

Video game consoles


Advanced driver assistance systems (ADAS)
Automotive instrument clusters and infotainment systems
White goods
Set-top boxes

128Mb Quad SPI NOR Flash Memory


CS#8
SRAM
SCK8

Features

IO08

Operating voltage range: 2.7 V to 3.6 V


100,000 Program1/Sector Erase2 endurance cycles3
20-year data retention at +55C
SDR4 clock rate: 133-MHz QIO5
DDR6 clock rate: 66-MHz QIO5
Program1 time (256B): 0.30 ms (typical)
Sector Erase2 time (64KB): 270 ms (typical)
Industrial temp range (AEC-Q100 optional): -40C to +85C
Industrial-plus temp range (AEC-Q100 optional): -40C to
+105C
Extended temp range (AEC-Q100 optional): -40C to +125C
Packages: 16-SOIC 300 mil, 8-WSON7 5 mm x 6 mm,
24-ball BGA 6 mm x 8 mm

X/Y
Decoder

Array
Right

IO18
I/O
IO28
IO38

Control
Logic

RD10

Data Path

RESET#9

Collateral
Datasheet:
App Notes:

Array
Left

Availability
S25FL128L
Cypress FL-L SPI NOR Flash Memory

The operation required to change a value 1 to a value 0 in NOR Flash memory


The operation required prior to a NOR Flash Memory Program, in which all the bits
in a Sector are set to value 1
3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it
wears out
4 Single-data-rate: A mode of data transfer in which data is transferred once per clock cycle

Sampling:
Production:

Quad input/output (QIO): An interface that transfers addresses or data on four I/Os simultaneously
Double-data-rate: A mode of data transfer in which data is transferred twice per clock cycle
7 Very, Very Thin, Small-Outline, No-Lead semiconductor package
8 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL128L datasheet for signal
definitions in the x1 and x2 mode.
9 RESET# is an optional signal available on 16-SOIC and BGA packages.
10 Read data buffer

Document No. 001-89435 Rev. *L

TBD
TBD

Product Overview 154

Cypress 3.0-V 256Mb (S25FL256L)


Quad SPI NOR Flash Memory
Applications

Block Diagram

Video game consoles


Advanced driver assistance systems (ADAS)
Automotive instrument clusters and infotainment systems
Networking devices
Set-top boxes

256Mb Quad SPI NOR Flash Memory


CS#8
SRAM
SCK8

Features

IO08

Operating voltage range: 2.7 V to 3.6 V


100,000 Program1/Sector Erase2 endurance cycles3
20-year data retention at +55C (typical)
SDR4 clock rate: 133-MHz QIO5
DDR6 clock rate: 66-MHz QIO5
Program1 time (256B): 0.30 ms (typical)
Sector Erase2 time (64KB): 270 ms (typical)
Industrial temp range (AEC-Q100 optional): -40C to +85C
Industrial-plus temp range (AEC-Q100 optional): -40C to
+105C
Extended temp range (AEC-Q100 optional.): -40C to +125C
Packages: 16-SOIC 300 mil, 8-WSON7 6 mm x 8 mm,
24-ball BGA 6 mm x 8 mm

X/Y
Decoder

Array
Right

IO18
I/O
IO28
IO38

Control
Logic

RD10

Data Path

RESET#9

Collateral
Datasheet:
App Notes:

Array
Left

Availability
S25FL256L
Cypress FL-L SPI NOR Flash Memory

operation required to change a value 1 to a value 0 in NOR Flash memory


operation required prior to a NOR Flash Memory Program, in which all the bits
in a Sector are set to value 1
3 The number of times a NOR Flash Memory Sector can be Programmed/Erased before it
wears out
4 Single-data-rate: A mode of data transfer in which data is transferred once per clock cycle

Sampling:
Production:

1 The

2 The

Document No. 001-89435 Rev. *L

Now
Now

Quad input/output (QIO): An interface that transfers addresses or data on four I/Os simultaneously
Double-data-rate: A mode of data transfer in which data is transferred twice per clock cycle
7 Very, Very Thin, Small-Outline, No-Lead semiconductor package
8 Signals used for standard Quad (x4) SPI interface; refer to the S25FL256L datasheet for signal
definitions in the x1 and x2 mode
9 RESET# is an optional signal available on 16-SOIC and BGA packages
10 Read data buffer
Product Overview 155

Military Memory

Document No. 001-89435 Rev. *L

156

Military Memory Portfolio


Military Temperature | Single Event Latch-up Immune
Fast Async SRAM

Sync SRAM
NoBL2, ECC

CY7S106x
16Mb, 1.8-5.0 V,
10 ns, x8/x16/x32,
Auto E, M

CY7C144/6xK
36Mb, 133-250 MHz,
2.5 V/3.3 V, x18/x36,
M

CY7S105x
8Mb, 1.8-5.0 V,
10 ns, x8/x16/x32,
Auto E, M

CY7C137/8xK Q316
18Mb, 100-250 MHz,
2.5 V/3.3 V, x18/x36,
M

CY7S104x
4Mb, 1.8-5.0 V,
12 ns, x8/x16,
Auto E, M

CY7C136xK Q316
9Mb, 100-250 MHz,
2.5 V/3.3 V, x18/x36,
M

64Kb-256Kb

1Mb-36Mb

64Mb-1Gb

ECC1

NOR Flash

Serial/Parallel I/O

Serial/Parallel I/O, ECC

Serial/Parallel I/O, ECC

CY7C41xKV13
144Mb; 667-1066 MHz,
1.3 V, x18/x36,
Burst 2, M4

S29GL-S
1Gb; 100 ns/15 ns,
3.0 V, x16,
Auto E5, M

CYRS26xKV18
144Mb, 1.8 V, 450 MHz,
x18/x36, Burst 2/4, M

S25FL-S
512Mb; 3.0 V,
133-MHz/80 MHz,
Auto E, M

CYPT154xAV18
72Mb, 1.8 V, 250 MHz,
x18/x36; Burst 2/4, M

S25FS-S
512Mb; 1.8 V,
133-MHz QSPI,
Auto E, M
CY14B116x
16Mb; 1.8-3.0 V,
25 ns/45 ns, x8/x16/x32,
M, RTC6
CY14B104x
4Mb, 1.8-3.0 V,
25 ns/45 ns, x8/x16,
Auto E, M
CY14B101x
1Mb, 1.8-3.0 V,
25 ns/45 ns, x8/x16, SPI
Auto E, M, RTC

CY15B102N
2Mb, 2.0-3.6 V,
60 ns, x16, Auto E, M
CY15B102Q
2Mb, 2.0-3.6 V,
40-MHz SPI, Auto E, M
FM25V10
1Mb; 2.0-3.6 V,
40-MHz SPI, Auto E, M

STK12C68-5
64Kb; 5.0 V,
35 ns/55 ns, x8; QML-Q
5 AEC-Q100

6 Real-time

Document No. 001-89435 Rev. *L

F-RAM

STK14C88-5
256Kb; 5.0 V,
35 ns/45 ns, x8; QML-Q7

Error-correcting code
No Bus Latency
3 Quad Data Rate
4 Military Temperature: 55C to +125C

QDR3II+/IV

Nonvolatile SRAM

-40C to +125C
clock
7 Qualified Manufacturers List Level Q, per MIL-PRF-38535

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

157

256Kb Military nvSRAM


Applications

Block Diagram

Military communication
Military real-time controls
Avionics real-time controls
High-reliability data logging

VCAP1

256kb Parallel nvSRAM

Features
Fast access time (35 ns, 45 ns, or 55 ns)
Available in parallel interface for 64Kb and 256Kb densities
Unlimited read/write endurance
One million store cycles on power fail
100 years data retention at +85C
Qualified Manufacturers List Level Q (QML-Q certified)
per MIL-PRF-38535
Military temperature grade: -55C to +125C
Packages: Ceramic 32-pin DIP, ceramic 32-pin LCC, 28-pin SOIC
and 32-pin SOIC

SONOS Array

STORE

Control

Control
Logic

Data

Store/Recall
Control

SRAM Array

x8

Power
Control

HSB2
RECALL

I/O Control

Address
Decoder

Software
Command
Detect

x14

Collateral

Address

Datasheets: STK12C68
STK14C88

Availability
Sampling: Now
Production: Now
1
2

External capacitor connection


Hardware STORE busy

Document No. 001-89435 Rev. *L

158

SRAM

Applications

Block Diagram

Military communication
Military real-time control
Avionics real-time control

Address
Port
x21, x22

QDR-II+
Data Clocks

Maximum frequency of operation/throughput: 250 MHz/36 Gbps


Burst sizes: 2 or 4
Bus-width configurations: x18 or x36
Military temperature grade: -55C to +125C
Two independent unidirectional data ports for read and write
enable concurrent transactions
Maximum throughput with double data rate (DDR) data ports
Output impedance matching input (ZQ): Matches the device
outputs to system data bus impedance
Bit-interleaving to eliminate multi-bit errors
I/O signaling standards: 1.5-1.8 V (HSTL)
Controllers available for Altera/Xilinx/Microsemi FPGAs
Package: 165-pin CCGA2

Collateral
Datasheets: CYPT1542AV18/CYPT1544AV18
CYPT1543AV18/CYPT1545AV18

1
2

CQ

CQ

Write Data Port


x18, x36

Write Data Port


(HSTL)

Features

Address Interface

SRAM Array

ZQ
Output Impedance Matching

Control
Logic
7

Control

Read Data Port


(HSTL)

72Mb

QDR -II+

Echo Clocks

QVLD Data Valid


Read Data Port
x18, x36

Boundary
Scan
JTAG Interface

Availability
Sampling: Now
Production: Now

Quad Data Rate: Four data transfers per clock cycle


Ceramic column grid array package

Document No. 001-89435 Rev. *L

159

SRAM

High-performance computing
Military and aerospace systems
Test and measurement

Features
Available in two options: QDR-IV HP (RTR 1,334 MT/s)
and QDR-IV XP (RTR 2,132 MT/s)
Two independent, bidirectional DDR2 data ports
Embedded error-correcting code (ECC) to reduce soft error rate
to <0.01 failure-in-time (FIT) per megabit
Bus inversion to reduce simultaneous switching I/O noise
On-die termination (ODT) to reduce board complexity
De-skew training to improve signal-capture timing
I/O levels: 1.2-1.25 V (HSTL/SSTL), 1.1-1.2 V (POD3)
Military temperature grade: -55C to +125C
Package: 361-ball FCBGA4
Bus widths: x18 or x36

Family Table
Option

Density

MPN

Max. Frequency

RTR

QDR-IV HP

72Mb
144Mb

CY7C40x1KV13
CY7C41x1KV13

667 MHz

1,334 MT/s

QDR-IV XP

72Mb
144Mb

CY7C40x2KV13
CY7C41x2KV13

1,066 MHz

2,132 MT/s

Block Diagram
Address
Address/Control Bus
Clock
Inversion Port

Address Parity
Parity Error

x21,x22

QDR-IV

Address Interface
2

2
Data Clocks

2
Data Valid
x18, x36
Data Port A

Collateral
Bus Inversion

ECC

Data Port B
(HSTL/SSTL or POD)

Applications

Data Port A
(HSTL/SSTL or POD)

QDR -IV

SRAM Array

Data Clocks

2
2

Data Valid

x18, x36
Data Port B
2
Bus Inversion

Datasheet: CY7C4021KV13/CY7C4041KV13
ODT
Impedance Matching

Quad Data Rate: Four data transfers per clock cycle


Double Data Rate: Two data transfers per clock cycle
3 Pseudo Open Drain: Signaling interface that uses strong pull-down and weak
pull-up drive strength
4 Flip-chip ball grid array

Control
Logic
Control

Test
Engine
JTAG Interface

Availability

Document No. 001-89435 Rev. *L

Sampling: Now
Production: Contact Sales
160

Sync SRAM With On-Chip ECC

Available in flow-through and pipeline modes1


Single-cycle (SCD)2 and double-cycle (DCD)2 deselect options
Bus-width configurations: x18 or x36
Two voltage options: 2.5 V and 3.3 V
Military temperature grade: -55C to +125C
Error-correcting code (ECC) to detect and correct
single-bit errors
Packages: 165-ball BGA and 100-pin TQFP
Industry-standard, RoHS3-compliant packages

MPN

Standard Sync with


On-Chip ECC Pipeline

9Mb
18Mb
36Mb

CY7C1360/2K
CY7C1370/2K
CY7C1440/2K

250 MT/s

<0.01

Standard Sync with


On-Chip ECC Flow-Through

9Mb
18Mb
36Mb

CY7C1361/3K
CY7C1371/3K
CY7C1441/3K

133 MT/s

<0.01

Block Diagram

Datasheets: CY7C135XKV33/CY7C136XKV33
CY7C137XKV33/CY7C138XKV33
CY7C144XKV33/CY7C146XKV33

1 Modes

of synchronous SRAM operation that optimize either read latency (Flow-Through)


or operating frequency (Pipeline)
2 Modes of operation in Pipeline mode where the output driver is tri-stated after either a
single cycle (SCD) or dual cycle (DCD) of issuing the deselect command
3 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
4 Failures-in-Time (FIT) per Megabit of Data (FIT/Mb): The projected failure rate of a device
where one FIT/Mb equals one failure per billion device hours per megabit of data

Document No. 001-89435 Rev. *L

Input
Register

2
Control
Byte Write
Chip Enable
Clock

Collateral

RTR

FIT/Mb4

Density

Output
Enable
x18, x36
Data Port

Control
Logic

ECC
Encoder

SRAM
Array

Address
Interface

Features

Option

Test
Engine

Avionics engine controls


Radar and signal processing
Test equipment
Military and aerospace systems

Family Table

Data Port and Control


(2.5/3.3V)

Applications

Output
Register
(Pipeline)

x19-x21
Address
Bus

JTAG
Interface

ECC
Decoder

Availability
Sampling: Now
Production: Now (36Mb), Q3 2016 (18Mb/9Mb)

161

Fast SRAM With PowerSnooze


Applications

Family Table

Avionics engine controls


Military helicopter controls
Military/commercial aircraft flight controls

Density

MPN

4Mb
8Mb
16Mb

CY7S104x
CY7S105x
CY7S106x

Access Time
(85C/125C)
10/12 ns
10/12 ns
10/12 ns

Deep Sleep Current


(Max at 85C)
15 A
22 A
22 A

Features
Access time: 10 ns or 12 ns (see Family Table)
PowerSnooze: Additional power-savings (deep-sleep) mode
Deep-sleep current: 22 A for 16Mb (see Family Table)
Multiple bus-width configurations: x8, x16 and x32
Wide I/O operating voltage range: 1.8-5.0 V
Military temperature grade: -55C to +125C
Industry-standard, RoHS2-compliant and leaded BGA packages
Error-correcting code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors

Block Diagram
Fast SRAM with PowerSnooze
ECC
Encoder

Input
Buffer
Data

Address
20

x8, x16, x32

Address
Decoder

SRAM Array

ERR

Power
Management
Block
(Enables
PowerSnooze)

Collateral
Datasheets: CY7S1049G/CY7C1049G
CY7S1059H/CY7C1059H
CY7S1069G/CY7C1069G

I/O Mux

DS3

Sense
Amps

ECC
Decoder

Control Logic

CE

OE WE BHE4 BLE4

Availability
1

A Fast SRAM with a deep-sleep mode in addition to a conventional standby mode.


For example, the 12-ns 16Mb offering has a deep-sleep current of 1.37 A/Mb and a
standby current of 1.87 mA/Mb
2 Restriction of Hazardous Substances: A European Union directive intended to eliminate
the use of environmentally hazardous material in electronic components
3 Deep sleep power mode
4 Byte high enable (BHE)/Byte low enable (BLE)

Document No. 001-89435 Rev. *L

Sampling:
Now
Production: Contact Sales

162

16Mb Parallel nvSRAM


Block Diagram

Applications
Industrial automation
Programmable logic controllers
Gaming machines
Industrial data logging
Networking and storage
Telecom equipment

VCAP4

16Mb Parallel nvSRAM


STORE

Control

Features

Control
Logic

Data

XIN1
XOUT2
INT3

Store/Recall
Control

SRAM Array

HSB5

RECALL

I/O Control

RTC

Power
Control

Address
Decoder

Software
Command
Detect

x21
Address

Availability

Collateral
Datasheet: CY14X116L/CY14X116N/CY14X116S

Document No. 001-89435 Rev. *L

x32

Fast access time (25 ns)


Available in parallel and Open NAND Flash Interface (ONFI)
version 1.0 interfaces
Unlimited read/write endurance
One million store cycles on power fail
20 years data retention at +85C
Optional real-time clock (RTC) functionality
Military temperature grade: -55C to +125C
Packages: 44-pin TSOP-II, 48-pin TSOP-I, 54- pin TSOP-II,
165-ball FBGA

Crystal connection input


Crystal connection output
3 Interrupt output/calibration/square wave

SONOS Array

Sampling: Now
Production: Contact Sales

External capacitor connection


Hardware STORE busy

163

2Mb SPI Serial F-RAM


Applications
Multifunction printers
Industrial controls and automation
Medical wearables
Test and measurement equipment
Smart meters
Aerospace and defense applications
Missiles and launchers

Block Diagram

2Mb SPI Serial F-RAM

Control

Features
40-MHz SPI interface
100-trillion read/write cycle endurance
Operating voltage range: 2.0-3.6 V
Low (20-A) sleep current at +125C
100 years data retention at +85C
Military temperature grade: -55C to +125C
Packages: 8-pin TDFN and 8-pin SOIC

Control
Logic

Instruction
Register

F-RAM
Array

Address
Register
Serial
Input

Data I/O
Register

Serial
Output

Status
Register

Collateral
Datasheet: CY15B102Q

Availability
Sampling: Now
Production: Contact Sales

Document No. 001-89435 Rev. *L

164

1Gb Parallel NOR Flash Memory


Applications

Block Diagram

Military systems boot memory


Avionics boot memory

1Gb Parallel Page Mode NOR Flash Memory


D0 D15 16

Features
Operating voltage range: 2.7 V to 3.6 V
100 program1/sector erase2 endurance cycles3 at +125C
>10 years data retention at +125C
Initial access time: 100 ns
Page access time: 15 ns
Program time (512B): 0.34 ms (typical)
Sector erase time (128KB): 275 ms (typical)
Military temperature grade: -55C to +125C
Packages: 56-pin TSOP (14 x 20 mm), 64-ball fortified4 BGA (9
x 9 and 13 x 11 mm)

Embedded
Voltage
Control

A0 A25 26

X Decoder

Array

RESET
CE
OE

I/O

Y Decoder
Control
Logic

26

WE
WP5
RY/BY6

Data Path
16

Collateral
Datasheet: S29GL01GS

Availability
Sampling: Now
Production: Contact Sales

The operation required to change a NOR Flash memory cell state from 1 to 0
The operation in which all the bytes in a sector of NOR Flash memory are erased
simultaneously prior to programming
3 The number of times a NOR Flash memory sector can be programmed or erased before
it wears out
1

Document No. 001-89435 Rev. *L

Fortified BGA supports a 1-mm ball pitch


Write protect input
6 Ready/busy output

165

512Mb Quad SPI NOR Flash Memory


Applications

Block Diagram

Military systems boot memory


Avionics boot memory

512Mb Quad SPI NOR Flash Memory


CS7
SRAM

Features

SCK7

Operating voltage range: 2.7-3.6 V


100 program1/sector erase2 endurance cycles3 at +125C
>10 years data retention at +125C
SDR4 clock rate: 104-MHz QIO5
DDR6 clock rate: 80-MHz QIO
Program time (512B): 0.340 ms (typical)
Sector erase time (256KB): 520 ms (typical)
Military temperature grade: -55C to +125C
Packages: 16-pin SOIC 300 mil and 24-ball BGA (6x8 mm)

I/O07

Array
Left

X/Y
Decoder

Array
Right

I/O17
I/O
I/O27

Control
Logic

I/O37

RD9

Data Path

RESET8

Collateral
Datasheet: S25FL512S

Availability
Sampling: Now
Production: Contact Sales
The operation required to change a NOR Flash memory cell state from 1 to 0
The operation in which all the bytes in a sector of NOR flash memory are erased
simultaneously prior to programming
3 The number of times a NOR Flash memory sector can be programmed/erased before
it wears out
4 Single Data Rate: A mode of data transfer in which data is transferred once per clock
cycle
1
2

Document No. 001-89435 Rev. *L

Quad Input/Output (QIO): An interface that transfers addresses or data on four I/Os
simultaneously
6 Double Data Rate: A mode of data transfer in which data is transferred twice per clock cycle
7 Signals used for standard Quad (x4) SPI interface. Refer to the S25FL512S datasheet for signal
definitions in the x1 and x2 mode.
8 RESET# is an optional signal available on 16-pin-SOIC and BGA packages.
9 Read data buffer
5

166

Aerospace Memory

Document No. 001-89435 Rev. *L

167

Aerospace Memory Portfolio


Radiation Hardened | Latch-up Immune | QML-V1 Certified
Fast Async SRAM

128Mb-144Mb

Non-ECC2

ECC2

Sync SRAM

Nonvolatile SRAM

QDR-II+/IV

Parallel I/O

Serial I/O

16Mb-72Mb

CYRS109x
128Mb; 1.8-5.0 V
12 ns; x8, x16, x32

CYRS264x
144Mb; 1.8 V; 450 MHz
x18, x36; Burst 2,4

CYRS108x
64Mb Serial; 1.8-5.0 V
SPI, QSPI, 106MHz

CYRS154x
72Mb; 1.8 V; 250 MHz
x18, x36; Burst 2,4

CYRS108x
64Mb; 1.8-5.0 V
12 ns; x8, x16, x32
Q416

Q417

CYRS104x
4Mb; 3.3 V
12 ns; x8

Q216

CYRS14x164
64Mb; 1.8-5.0 V
35 ns; x16, x32
Q217

CYRS14x116
16Mb; 1.8-5.0 V
35 ns; x16, x32

Q218

Q217

CYRS104x
4Mb; 1.8-5.0 V
12 ns; x8, x16, x32

Q117

CYRS15x102
2Mb; 2.0-3.6 V
40 MHz; SPI
Concept

1
2

Parallel I/O

CYRS4141x
144Mb; 1.2 V; 667 MHz
x18, x36; Burst 2

CYRS106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32

2Mb-4Mb

FRAM

Qualified Manufacturers List Level V, per military specification MIL-PRF-38535


Error-correcting code

Document No. 001-89435 Rev. *L

Q417

Q117

Development

CYRS15x102
2Mb; 2.0-3.6 V
60 ns; x16

Q417

Sampling

Production

QQYY

QQYY

Status
Availability

168

72Mb QDR-II+ SRAM with RadStop1


Block Diagram

Applications
Payload processing
Reconfigurable computing platforms

Address
Port
x21,x22

Features
QDR-II+

CQ

CQ

Write Data Port


x18, x36

Read Data Port


(HSTL)

Data Clocks

Address Interface

Write Data Port


(HSTL)

Max frequency of operation/throughput: 250 MHz/36 Gbps


Burst sizes: 2, 4
Bus-width configurations: x18, x36
Military temperature grade: -55C to +125C
Two independent unidirectional data ports for read and write
enable concurrent transactions
Maximum throughput with double data rate (DDR) data ports
Output impedance matching input (ZQ): Matches the device
outputs to system data bus impedance
Bit-interleaving to eliminate multi-bit errors
I/O signaling standards: 1.5-1.8 V (HSTL)
Controller available for Xilinx and Microsemi FPGAs
Total ionizing dose: 300 Krad
Heavy-ION SEL2: 120 LET3 MeV-cm sq/mg
Heavy-ION SEU4: 1.34E-07 (Geosynchronous) Error/Bit-day
QML-V5 qualified (DLAM6 part number: 5962F11201/02VXA)

SRAM Array

ZQ
Output Impedance Matching

Control
Logic
7

Control

Availability

Cypress Datasheets : 72-Mbit SRAMs w/ RadStop


DLAM Datasheets:
72-Mbit SRAMs w/ RadStop
Request FPGA controller IP via email: radstop@cypress.com

Non-space-qualified prototypes (CYPT154x):


QML-V5 space-qualified devices (CYRS154x):
4

proprietary design and process technology that increases radiation-resistance


Single-event latch-up
3 Linear energy transfer

Document No. 001-89435 Rev. *L

QVLD
Data Valid
Read Data Port
x18, x36

Boundary
Scan

Collateral

1 Cypresss

Echo Clocks

JTAG Interface

Now
Now

Single-event upset
Qualified Manufacturers List Level V, per military specification MIL-PRF-38535
6 Defense Logistics Agency Land and Maritime, Columbus, OH

169

4Mb Fast SRAM with RadStop1


Block Diagram

Applications
Payload processing
Sensors and switches

Features
Fast SRAM

Access time: 10 ns (85C), 12 ns (125C)


Bus-width configuration: x8
Operating voltage: 3.3 V
Military temperature grade: -55C to +125C
Bit-interleaving to eliminate multi-bit errors
Package: 36-pin ceramic flat pack (CFP)
Total ionizing dose: 300 Krad
Heavy-ION SEL2: 120 LET3 MeV-cm sq/mg
Heavy-ION SEU4: 5.0E-08 (Geosynchronous) Error/Bit-day
QML-V5 qualified (DLAM6 part number: 5962F11235VXA)

Address Port
x18

Address
Decoder

SRAM
Array

Sense
Amps

OE

x8

WE

Collateral

Availability

Cypress Datasheet: 4-Mbit SRAM w/ RadStop


DLAM Datasheet:
4-Mbit SRAM w/ RadStop

Non-space-qualified prototypes (CYPT1049):


QML-V5 space-qualified devices (CYRS1049):

1 Proprietary

Document No. 001-89435 Rev. *L

Data Port

Control Logic

CE

Cypress design and process technology that increases radiation-resistance


Single-event latch-up
3 Linear energy transfer

I/O
MUX

Now
Now

Single-event upset
Qualified Manufacturers List Level V, per military specification MIL-PRF-38535
6 Defense Logistics Agency Land and Maritime, Columbus, OH

170

Energy Harvesting PMIC

Document No. 001-89435 Rev. *L

171

Series Solar Cell by


Panasonic (AM-1801)

Wearable

Residential

Building

Industrial

Activity Monitor

WSNs2 for HVAC3, Level


of Light Emitted,
Temperature, Humidity,
Motion

WSNs2 for HVAC3, Level


of Light Emitted,
Temperature, Humidity,
Motion, BLE4 Beacon5

WSNs2 for Infrastructure, Agriculture,


Transportation, Factory Automation, Animal
Monitoring

Indoor/Outdoor

Single Solar Cell by


Ningbo Hebe Solar (HSC125155)
NEW

Light
Piezoelectric Device by
Thrive (K7520BS3)

S6AE101A
Linear, Power Gating6,
Multiplexer7,
10-pin QFN

Series
Solar Cell

Indoor

NEW

NEW

S6AE102A
Linear, Power Gating6,
Multiplexer7, LDO8,
Comparator, 20-pin QFN

S6AE103A
Linear, Power Gating6,
Multiplexer7, LDO8, Timer,
Comparator, 24-pin QFN

MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN

MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN

MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN

S6AE101A
Linear, Power Gating6,
Multiplexer7,
10-pin QFN

NEW

Energy Harvesting PMIC1 Portfolio

Electromagnetic Device by
Perpetuum (PMG-FSH)

Light

Single
Solar Cell
MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN

Vibration
TEG by Micropelt
(TGP-651)

Piezoelectric,
Electromagnetic

MB39C831
Boost DC/DC, MPPT9,
Li-ion Protection,
40-pin QFN

Thermoelectric
Generator (TEG)
Management IC
2 Wireless Sensor Nodes
3 Heating, ventilation, air conditioning
4 Bluetooth Low Energy
5 A wireless device that transmits data (e.g., signal strength and ID)
over a periodic radio signal from a known location

Document No. 001-89435 Rev. *L

MB39C831
Boost DC/DC, MPPT9,
Li-ion Protection,
40-pin QFN

MB39C811
Buck DC/DC, Dual-Bridge
Rectifier, Power Good,
40-pin QFN

Heat

1 Power

Outdoor

6 Output

Market Segment

power control circuit that controls power provided


to the system load
7 Power source switch circuit for primary battery or Energy
Harvesting Device
8 Low drop out regulator
9 Maximum Power Point Tracking

Concept

Development

Sampling

Production

QQYY

QQYY

Status
Availability

Roadmap

172

Energy Harvesting PMIC1 (S6AE101A)


Applications

Block Diagram

Series solar cell energy harvesting2 and wireless sensor nodes3


Primary
Battery
(Optional)

Features
Ultra-low power: Enables 1 cm2 minimum solar cell size for
startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 250 nA
Startup power: 1.2 W
Power gating6 switch circuit
Storage control circuit
Multiplexer7 circuit (battery vs. solar cell)
Overvoltage protection
Packages: 10-pin SON (3.0 x 3.0 mm)

S6AE101A

System
Load
Power Gating6
Switch

+
Multiplexer7

Storage
Control

Series
Solar Cell
Overvoltage
Protection

Vref8

Control Block

Collateral
Datasheet:
S6AE101A Datasheet
Development Kits: Solar-Powered IoT Device Kit
S6AE10xA Evaluation Board
Software:
Easy DesignSim Software

Availability
Sampling:
Production:

1 Power

2 The

Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile
device

Document No. 001-89435 Rev. *L

Now
Now

Estimate based on solar cell power = 2 W/cm2 at 100 lx


Current consumed at no load condition
6 Output power control circuit that controls power provided to the system load
7 Power source switch circuit for primary battery and Energy Harvesting Device
8 Voltage reference circuit for internal block

Product Overview

173

Energy Harvesting PMIC1 (S6AE102A)


Applications

Block Diagram

Series solar cell energy harvesting2 and wireless sensor nodes3

Primary Battery
(Optional)

Features

S6AE102A
Power Gating6
Switch

Ultra-low power: Enables 1 cm2 minimum solar cell size for


startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 280 nA
Startup power: 1.2 W
Low quiescent current5 low drop out regulator (LDO): 400 nA
Dual channel power gating6 switch circuit with IRQ7 control
Signal output circuit of power gating switch control
Multiplexer8 circuit (battery vs. solar cell)
Hybrid storage control circuit9 and overvoltage protection
Packages: 20-pin QFN (4.0 x 4.0 mm)

Multiplexer8

Hybrid Storage
Control9

Series
Solar
Cell

Overvoltage
Protection

VIN_LDO

LDO

Control Block

ENA_LDO
STBY_LDO

IRQ7 for Power


Gating
Switch Control

INT

Vref10

Datasheet:
S6AE102A Datasheet
Development Kits: S6AE10xA Evaluation Board
Software:
Easy DesignSim Software

Availability
Sampling:
Production:

1 Power

2 The

Document No. 001-89435 Rev. *L

System
Load2

SW_CONT

VOUT_LDO

Collateral

Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile device
4 Estimate based on solar cell power = 2 W/cm 2 at 100 lx

Power Gating6
Switch

System
Load1

Now
Now

Current consumed at no load condition


Output power control circuit that controls power provided to the system load
7 Interrupt request control function for power management
8 Power source switch circuit for primary battery or series solar cell
9 Uses a small and large capacitor to automatically store excess power for backup
10 Voltage reference circuit for internal block
Product Overview

174

Energy Harvesting PMIC1 (S6AE103A)


Applications

Block Diagram

Series solar cell energy harvesting2 and wireless sensor nodes3

Primary Battery
(Optional)

Features
Ultra-low power: Enables 1 cm2 minimum solar cell size for
startup operation4
Input voltage range:
Series solar cell: 2.0-5.5 V
Primary battery: 2.0-5.5 V
Output voltage range: 1.1-5.2 V
Quiescent current5: 280 nA
Startup power: 1.2 W
Low quiescent current5 low drop out regulator (LDO): 400 nA
Low consumption current CR timer6: 30 nA
General-purpose low consumption current comparator: 20 nA
Dual channel power gating7 switch circuit with CR timer6 and
IRQ6 control
Signal output circuit of power gating switch control
Multiplexer8 circuit (battery vs. solar cell)
Hybrid storage control circuit9 and overvoltage protection
Packages: 24-pin QFN (4.0 x 4.0 mm)

S6AE103A
Gating7

Power
Switch

+
Multiplexer8

Power Gating7
Switch
Hybrid Storage
Control9

Series
Solar Cell
VIN_LDO

System
Load1
System
Load2

Overvoltage
Protection

SW_CONT/
COMPOUT

LDO

ENA_COMP
ENA_LDO
STBY_LDO

VOUT_LDO
Control Block

Vref10
COMPP

Comparator

COMPM

CR Timer6 & IRQ6


for Power Gating
Switch Control

INT

Collateral
Datasheet:
S6AE103A Datasheet
Development Kits: S6AE10xA Evaluation Board
Software:
Easy DesignSim Software

Availability
Sampling:
Production:

1 Power

2 The

Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 A sensor-based device that monitors conditions such as temperature, humidity and pressure
and wirelessly transmits that data to a control unit, such as a PC or a mobile device
4 Estimate based on solar cell power = 2 W/cm 2 at 100 lx

Document No. 001-89435 Rev. *L

Now
Now

Current consumed at no load condition


Time (or IRQ: Interrupt request) control function for power management
7 Output power control circuit that controls power provided to the system load
8 Power source switch circuit for primary battery or series solar cell
9 Uses a small and large capacitor to automatically store excess power for backup
10 Voltage reference circuit for internal block
Product Overview

175

Energy Harvesting PMIC1 (MB39C811)


Applications

Block Diagram

Series solar cell energy harvesting2, Piezoelectric3 energy


harvesting and wireless sensor nodes (WSN)4
MB39C811

Features
Ultralow-power buck DC/DC converter dual-bridge rectifiers
Quiescent current5: 1.5 A
Input voltage range: 2.6 V-23 V
Output voltage: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 3.6 V, 4.1 V,
4.5 V and 5.0 V
Output current: 100 mAmax
Overcurrent protection
Low-loss full-wave bridge rectifier: VF6 = 0.28 V (IF = 10 A),
IR7 = 20 nAmax (Vreverse = 18 V)
Shunt for input protection: VIN 21 V, up to 100-mA pulldown
Input and output power good monitoring
Package: 40-pin QFN (6.0 x 6.0 mm)

VIN

Series
Solar cell

Shunt
Bridge
Rectifier

Piezoelectric

VOUT
Bridge
Rectifier

VB Reg8

S2
S1
S0

VOUT
Setting

Buck DC/DC
Converter

BGR9

ERR
CMP10

Collateral
Datasheet:
MB39C811 Datasheet
Development Kits: Energy Harvesting Starter Kit
MB39C811 Evaluation Board
Software:
Easy DesignSim Software

Availability
Sampling:
Production:

1 Power

2 The

Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 Power generation device using vibration
4 A sensor-based device that monitors conditions such as temperature, humidity and
pressure and wirelessly transmits that data to a control unit, such as a PC or a mobile device

Document No. 001-89435 Rev. *L

Power Good

VIN
Power
Good
VOUT
Power
Good

Now
Now

Current consumed at no load condition


Bridge rectifier reverse breakdown voltage
7 Bridge rectifier reverse bias leak current
8 Regulator for internal block
9 Band Gap Reference
10 Error Comparator
Product Overview

176

Energy Harvesting PMIC1 (MB39C831)


Applications
Single solar cell energy harvesting2, thermoelectric generator3
energy harvesting and wireless sensor nodes4

Block Diagram
VIN

MB39C831

Features
Ultralow-voltage startup boost DC/DC converter
Input voltage range: 0.3 V-4.75 V
Startup voltage: 0.35 V
Output voltage: 3.0 V, 3.3 V, 3.6 V, 4.1 V, 4.5 V, 5.0 V
(Constant voltage mode only)
Quiescent current5: 32 A
Output current: 8 mA (VDD = 0.6 V, VOUT = 3.3 V) and
80 mA (VDD = 3.0 V, VOUT = 3.3 V)
Input peak current limit: 200 mA
Built-in Maximum Power Point Tracking (MPPT)6 function
Built-in Li-ion charge function
Input and output power good monitoring
Package: 40-pin QFN (6.0 x 6.0 mm)

VDD Voltage
Detector
(UVLO7)

Startup

VCC Voltage
Detector
VOUT Voltage
Detector
MPPT6
Enable
Enable
S2
S1
S0

VOUT-VDD
Voltage
Inversion
Detector
BGR8

VOUT
Boost DC/DC
Converter

Energy
Storage
Device

MPPT6
Controller

Collateral
Datasheet:
MB39C831 Datasheet
Development Kits: MB39C831 Evaluation Board
Software:
Easy DesignSim Software

VIN & VOUT


Power Good

Availability
Sampling:
Production:

1 Power

5 Current

2 The

6 Maximum

Management IC
process of capturing and converting tiny amounts of energy
(e.g., from light, vibration or heat) into electricity
3 Power Generation Device using heat
4 A sensor-based device that monitors conditions such as temperature, humidity and pressure
and wirelessly transmits that data to a control unit, such as a PC or a mobile device

Document No. 001-89435 Rev. *L

Now
Now

consumed at no load condition


Power Point Tracking maximizes the Energy Harvest by adjusting
current drawn from a solar panel
7 Undervoltage lockout
8 Band Gap Reference
Product Overview

177

Automotive Products

Document No. 001-89435 Rev. *L

178

Table of Contents
Page

Topic

180

Automotive TrueTouch

187

Automotive CapSense

193

Automotive PSoC

201

Automotive Traveo Instrument Cluster MCU Family

206

Automotive Traveo Body Control MCU Family

210

Automotive Traveo MPN Selector Guides

215

Automotive Asynchronous SRAM

219

Automotive Synchronous RAM

221

Automotive Nonvolatile RAM

226

Automotive Flash Memory

237

Automotive USB

243

Automotive Timing Solutions

247

Automotive Power Management IC

252

Automotive LED Driver

Document No. 001-89435 Rev. *L

179

Automotive TrueTouch Roadmap

Document No. 001-89435 Rev. *L

180

Automotive Portfolio: TrueTouch


Gen4

Gen6

Gen7

10 Finger, AutoArmor1, DualSense2, H2O3, Glove Touch4


In-Cell7 or SLIM8, Gestures, AMS5
Thick Glove6 or Thick/Curved Overlay

Next Generation

CYAT8168X-88
88 I/O, 100-Hz RR10
Grades: A12 and S13

CYAT8X68X-88
88 I/O, 100-Hz RR10
Grades: A12 and S13

CYAT8X7XX
NDA Required, Contact Sales

CY8CTMA1036
65 I/O, 80-Hz RR10
Gestures, Thin Glove14
Grades: A12 and S13

CYAT8168X-77/71
77/71 I/O, 120-Hz RR10
Grades: A12 and S13

CYAT8X68X-77/71
77/71 I/O, 120-Hz RR10
Grades: A12 and S13

CY8CTMA768
56 I/O, 80-Hz RR10
Gestures, Thin Glove14
Grades: A12 and S13

CYAT8168X-61
61 I/O, 120-Hz RR10
Grades: A12 and S13

CYAT8X68X-61
61 I/O, 120-Hz RR10
Grades: A12 and S13

CYTMA461
48/43 I/O15, 80-Hz RR10
AMS5, Thick Overlay, Thick Glove6
Grades: A12 and S13

CYAT8165X-48
48 I/O, 100-Hz RR10
Grades: A12 and S13

CYAT8X65X-48
48 I/O, 100-Hz RR10
Grades: A12 and S13

CY8CTMA460
48/43 I/O15, 100-Hz RR10
Gestures, Thin Glove14
Grades: A12 and S13

CYAT816XX-36
36 I/O, 120-Hz RR10
Grades: A12 and S13

CYAT8X6XX-36
36 I/O, 100-Hz RR10
Grades: A12 and S13

3-8

7-12
Active Touch Area

> 12

Gestures, AMS5
Thick Glove6 or Thick Overlay

1 Enables

compliance with chip-level emission,


immunity and system-level specifications
2 Self-Capacitance + Mutual-Capacitance
3 Waterproofing and wet-finger tracking
4 A feature that allows the detection of gloved fingers
on a touch sensor
5 Automatic Mode Switching
6 1-mm to 5-mm glove thickness (ski gloves)

Document No. 001-89435 Rev. *L

CYAT8X7XX
NDA Required, Contact Sales

Q316

A type of sensor stack-up in which the RX sensor is


inside the LCD module under the color-filter glass
8 Single-Layer Independent Multi-Touch
9 AutoArmor + Test report on touch functionality during
immunity conditions
10 Refresh rate
11 A type of sensor stack-up in which the RX sensor is inside the
LCD module as part of the TFT layer

12

AEC-Q100: -40C to +85C


AEC-Q100: -40C to +105C
14 Less than 1-mm glove thickness (normal leather gloves)
15 Number of available I/Os depends on package selection
Concept Development Sampling Production
Industrial
Automotive
QQYY
QQYY
Availability
13

181

Automotive Portfolio:
TrueTouch Software1
PSoC Designer

TrueTouch Host
Emulator2

TrueTouch Driver for


Android3

Manufacturing Test
Kit4

5.4 SP1

3.3.10

3.5

1.8.5

CY8CTMA616

Production

Production

CY8CTMA884

Production

TTDA 2.5.1
Production

CY8CTMA460

Production

CY8CTMA768

Production

CY8CTMA1036

Production

CY8CTMA461

Production

Production

CYAT8168X-61

Production

Production

CYAT8168X-71

Production

Software

MPN

Current Version
Gen 1

Gen 3

Gen 4

Gen 6

CY8CTMA120

Production

CY8CTMG120

Production

Production
Production

TTDA 2.5
Production

Production
Production

Production
Contact Sales

CYAT8168X-77

Production

Production

CYAT8168X-88

Production

Production

Contact sales for the latest TrueTouch software, drivers and tools
1 PSoC

Designer, TTHE and MTK releases are backward compatible. The latest version is recommended for new designs.
Host Emulator (TTHE) is a front-end tool used to configure, tune, debug and demonstrate TrueTouch devices
3 TrueTouch Driver for Android (TTDA) is the driver for Android that translates touch information into Linux/Android events
4 TrueTouch Manufacturing Test Kit (MTK) enables customers and ITO partners to test touch panels that use Cypress TrueTouch controllers through the manufacturing flow
2 TrueTouch

Document No. 001-89435 Rev. *L

182

CY8CTMA460/768/1036
Automotive TrueTouch Gen4 Family
Applications

Block Diagram
Host Processor

Touchscreens
Trackpads

1 - I2 C
2 - Serial Peripheral Interface (SPI)

INT8

Features
Advanced User Interface
Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 1-mm-thick gloves
Proprietary Analog Front End2 with AutoArmorTM 3
True 10-V TX-Boost with multiphase TX4
DualSense: Self5- and mutual6-capacitance analog front end
(U.S. patents 8,358,142; 8,319,505; and 8,067,948)
System Solutions
Supports thin ITO7 stackups and metal mesh sensors
AutoArmor enables compliance with chip-level emission
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
Android driver support
Manufacturing test kits for production testing
Packages
100-pin TQFP, 56-pin QFN (TMA460 only)

Collateral
Datasheet:
CY8CTMA1036/768/460
Evaluation Kit: CY3290-TMA1036A

CY8CTMA
460/768/1036

32
32

Flash

ARM Cortex
CPU

32

SRAM

32

10-V TX
Pump

Touch
Sequencer

RX
Channels

Programmable Analog Multiplexer

65

Touchscreen Sensor I/O: XY00-XY64

Touchscreen Sensor

Availability
Sampling:
Production:

56-pin QFN: Now


100-pin TQFP: Now; 56-pin QFN: Q3 2016

1 The

5 The

2 Analog

6 The

ability of a Touchscreen Sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure Self- and Mutual-Capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously

Document No. 001-89435 Rev. *L

I2C/SPI

capacitance of a row or column line in a Touchscreen Sensor


capacitance between a row and a column in a Touchscreen Sensor
7 Indium tin oxide
8 Interrupt

183

CY8CTMA461

Automotive TrueTouch Gen4 Family


Applications

Block Diagram
Host Processor

Touchscreens
Trackpads

1 - I2 C
2 - Serial Peripheral Interface (SPI)

INT8

Features

CY8CTMA461
I2C/SPI

Advanced User Interface


Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 5-mm-thick gloves or thick overlay
Proprietary Analog Front End2 with AutoArmorTM 3
True 10-V TX-Boost with multiphase TX4
DualSense: Self5- and mutual6-capacitance analog front end
(U.S. patents 8,358,142; 8,319,505; and 8,067,948)
System Solutions
Supports thin ITO7 stackups and metal mesh sensors
AutoArmor enables compliance with chip-level emission
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
Android driver support
Manufacturing test kits for production testing
Packages
100-pin TQFP, 56-pin QFN

Collateral
Datasheets and Design Guides:
Contact Sales or automotive@cypress.com

32
32

Flash

32

SRAM

32

10-V Tx
Pump

Touch
Sequencer

Rx
Channels

Programmable Analog Multiplexer

48

Touchscreen Sensor I/O: XY00-XY47

Touchscreen Sensor

Availability
Sampling:
Production:

56-pin QFN: Now


100-pin TQFP: Now; 56-pin QFN: Q3 2016

1 The

5 The

2 Analog

6 The

ability of a Touchscreen Sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure Self- and Mutual-Capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously

Document No. 001-89435 Rev. *L

ARM Cortex
CPU

capacitance of a row or column line in a Touchscreen Sensor


capacitance between a row and a column in a Touchscreen Sensor
7 Indium tin oxide
8 Interrupt

184

CYAT8168X

Automotive TrueTouch Gen6 Family


Applications

Block Diagram
Host Processor

Large touchscreen human machine interface (HMI) systems

1 - I2C
2 - Serial Peripheral Interface (SPI)

INT7

Features

CYAT8168X
I2C/SPI

Advanced User Interface


Waterproofing1: Works with water droplets, condensation, sweat
and wet-finger tracking
Tracking with up to 5-mm thick gloves or thick overlay
Proprietary Analog Front End2 with AutoArmor3
True 5-V TX-Boost with Multi-Phase TX4
54 Receive Channels to support 100 Hz refresh rates
DualSense: Self5- and Mutual6-Capacitance analog front end
(U.S. Patents 8,773,146; 8,358,142; 8,319,505; and 8,067,948)
AutoArmor enables compliance with chip-level emissions
(IEC 61967), immunity (IEC 62132) and system-level
(CISPR 25) specifications
System Solutions
Manufacturing test kits for production testing
Package
128-pin TQFP, 100-pin TQFP

32
32

Flash

ARM Cortex
CPU

32

SRAM

32

Channel
Engine
Touch
Sequencer
5-V TX
Pump

RX
Channels

Programmable Analog Multiplexer


88

Touchscreen Sensor I/O: XY00-XY87

Touchscreen Sensor

Collateral
Datasheets and Design Guides:
Contact Sales or automotive@cypress.com

Availability
Production:

Now

1 The

5 The

2 Analog

6 The

ability of a Touchscreen Sensor to work properly in the presence of water droplets, condensation or sweat
circuit in the touchscreen controller used to measure Self- and Mutual-Capacitance
3 Cypress proprietary technology used to reduce emissions and improve EMI immunity to meet automotive EMC
requirements
4 A scanning method used to drive multiple TX lines simultaneously

Document No. 001-89435 Rev. *L

capacitance of a row or column line in a Touchscreen Sensor


capacitance between a row and a column in a Touchscreen Sensor
7 Interrupt

185

Automotive TrueTouch Packages


Package

QFN

Pins
Body Size

56

100

128

8 x 8 mm

14 x 14 mm

14 x 20 mm

0.5 mm

0.5 mm

0.5 mm

Family

Pitch

Gen 1

CY8CTMA120

, 1

CY8CTMG120

Gen 3

Gen 4

CY8CTMA616

CY8CTMA884

CY8CTMA460

CY8CTMA768

CY8CTMA1036

CY8CTMA461
Gen 6

TQFP

CYAT8168X-61

CYAT8168X-71

CYAT8168X-77

CYAT8168X-88

Wettable flanks package to allow automated optical inspection (AOI)

Document No. 001-89435 Rev. *L

186

Automotive CapSense Roadmap

Document No. 001-89435 Rev. *L

187

Entry

Value

Performance

Automotive Portfolio: CapSense


CapSense Express

CapSense Plus

PSoC

Configurable1

Programmable2

Programmable System-on-Chip

CY8CMBR3106S
11 Buttons, 2 Sliders
SmartSense_EMCplus3
Proximity
Grades: A4 and S5

CY8CMBR3116
16 Buttons, 8 LEDs
SmartSense_EMCplus3
Proximity, Water Tolerance
Grades: A4 and S5

CY8C20xx7/S
31 Buttons, 6 Sliders
16, 32KB Flash; 2KB SRAM
Proximity, Water Tolerance
Glove, Stylus Support

CY8CMBR3108
8 Buttons, 4 LEDs
Proximity, Water Tolerance
SmartSense_EMCplus3

CY8CMBR3110 Q416
10 Buttons, 5 LEDs
SmartSense_EMCplus3
Proximity, Water Tolerance
Grades: A4 and S5

CY8CMBR3102
2 Buttons, Proximity
SmartSense_EMCplus3

CY8CMBR2110
10 Buttons, 10 LEDs
SmartSense Auto-tuning

CY8CMBR310XLP
1-4 Buttons, Low Power
Contact Sales

CY8CMBR2016
16 Buttons
SmartSense Auto-tuning

CY8CMBR2044
4 Buttons, 4 LEDs
SmartSense Auto-tuning

CY8CMBR2010
10 Buttons, 10 LEDs
SmartSense Auto-tuning

CY8C24x94
43 Buttons, 8 Sliders
16KB Flash, 1KB SRAM
Grade: A4

CY8CMBR3002
2 Buttons, 2 LEDs
SmartSense_EMCplus3

CY8C201xx
10 Buttons, 5 LEDs
2 Sliders

CY8C20234
10 Buttons, 2 Sliders
8KB Flash, 512Byte SRAM
Grade: A4

CY8C20236A
10 Buttons, 2 Sliders
8KB Flash, 1KB SRAM
SmartSense Auto-tuning
Grade: A4
CY8C21x34
20 Buttons, 4 Sliders
8KB Flash, 512Byte SRAM
Proximity, Water Tolerance
Grades: A4 and E6

CY8C20xx6H
25 Buttons, 5 Sliders
8,16KB Flash; 1,2KB SRAM
SmartSense Auto-tuning
Haptics

CY8C4246/7-M Q416
51 Buttons, 10 Sliders
64, 128KB Flash
Proximity, Water Tolerance
Grades: A4 and S5

CY8C4246/7-L
96 Buttons, 19 Sliders
128, 256KB Flash
Proximity, Water Tolerance
Contact Sales

CY8C41xx-S
32 Buttons, 5 Sliders
16-64KB Flash
Proximity, Water Tolerance
Grades: A4 and S5

CY8C36xx/38xx
62 Buttons, 12 Sliders
32, 64KB Flash
Proximity, Water Tolerance
Grades: A4 and E6

CY8C41xx/42xx
24 Buttons, 4 Sliders
16, 32KB Flash
Proximity, Water Tolerance
Grades: A4 and S5

CY8C32xx/34xx
62 Buttons, 12 Sliders
16-64KB Flash
Proximity, Water Tolerance
Grades: A4 and E6

CY8C21x12
20 Buttons, 4 Sliders
8KB Flash, 512Byte SRAM
Proximity, Water Tolerance
Grades: A4 and E6

CY8C40xx-S
32 Buttons, 5 Sliders
16, 32KB Flash
Proximity, Water Tolerance
Grades: A4 and S5

CY8C2xx45
36 Buttons, 7 Sliders
16KB Flash, 1KB SRAM
Grades: A4 and E6
CY8C40xx
16 Buttons, 3 Sliders
16KB Flash, 2KB SRAM
Proximity, Water Tolerance
Grades: A4 and S5

Integration
1 Standard

products are configured for target applications with a graphical user interface
2 Microcontroller-based products can be freely programmed to implement additional functions
3 SmartSense Electromagnetic Compatible = SmartSense Auto-tuning + high noise immunity

Document No. 001-89435 Rev. *L

4 AEC-Q100:

-40C to +85C
5 AEC-Q100: -40C to +105C
6 AEC-Q100: -40C to +125C

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

188

Automotive Portfolio:
CapSense Software1
Software
Current Version

PSoC Creator2

PSoC Designer

3.3 CP3

PSoC 1

PSoC Programmer4

EZ-Click

5.4 SP1

3.24.4

2.0 SP1

Production

Production

PSoC 3

Production

Production

PSoC 4

Production

Production

CapSense Plus
CapSense Express

Production
Production

Download the latest PSoC software version here

1 All

software and tool releases are backward compatible. The latest versions are recommended for new designs
Creator is an Integrated Design Environment (IDE) that allows concurrent hardware and firmware design of PSoC 3 and PSoC 4 systems
3 PSoC Designer is an IDE that enables firmware design using a library of precharacterized peripherals for PSoC 1 systems
4 PSoC Programmer can be used with PSoC Designer and PSoC Creator to program and debug any design onto a PSoC device
5 EZ-Click is a Windows GUI-based tool that enables development of CapSense MBR solutions. It allows you to set up sensor configuration, apply global system properties, monitor real-time
sensor output, and run production-line system diagnostics
2 PSoC

Document No. 001-89435 Rev. *L

189

Automotive PSoC 4100-Series


Intelligent Analog Family
Block Diagram

MCU and discrete analog replacement


Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks
Opamp
x1

32-bit MCU Subsystem


24-MHz ARM Cortex-M0 CPU
Up to 32KB flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 806-Ksps SAR2 ADC
CapSense with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four configurable 16-bit timer, counter or pulse-width modulator
(TCPWM) blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP

Collateral
Datasheet:

24 MHz

Flash
(16KB to 32KB)

SRAM
(4KB)

CMP
x2

GPIO x6

SAR2
ADC

CSD

Programmable Digital
Blocks
TCPWM x4

SCB x2

Segment LCD Drive

GPIO x4

GPIO x6

GPIO x4

Serial Wire Debug


GPIO x4

Availability
Automotive PSoC 4100 Datasheet

1 Programmable
2 Successive

Cortex-M0

Advanced High-Performance Bus (AHB)

Features

I/O Subsystem

Programmable Interconnect and Routing

Applications

gain amplifier
approximation register

Document No. 001-89435 Rev. *L

3 Industrial:

Sampling:
Production:

Now
Now

-40C to +85C

190

Automotive PSoC 4200-Series


Programmable Digital Family

MCU and discrete analog replacement


Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning

Block Diagram
PSoC 4 One-Chip Solution
MCU Subsystem

Programmable Analog
Blocks
Opamp
x1

32-bit MCU Subsystem


48-MHz ARM Cortex-M0 CPU
Up to 32KB flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP

Collateral
Datasheet:

Cortex-M0
48 MHz

Flash
(16KB to 32KB)

SRAM
(4KB)

Serial Wire Debug

Advanced High-Performance Bus (AHB)

Features

CMP
x2

I/O Subsystem
GPIO x6

SAR2
ADC

CSD

Programmable Digital
Blocks
UDB x4

TCPWM3 x4

SCB x2

Segment LCD Drive

Programmable Interconnect and Routing

Applications

GPIO x4

GPIO x6

GPIO x4

GPIO x4

Availability
Automotive PSoC 4200 Datasheet

Sampling:
Production:

Now
Now

1 Programmable

gain amplifier
approximation register
3 Timer, counter, pulse-width modulator
2 Successive

Document No. 001-89435 Rev. *L

191

Automotive CapSense Packages


Package

LQFP

Pins
Body Size

Family

Pitch

PSoC 1

2XX45

QFN

SOIC

24

40

56

16

20

28

48

64

7 x 7 mm

4 x 4 mm

6 x 6 mm

8 x 8 mm

150 Mil

210 Mil

5 x 10 mm

300 Mil

10 x 10 mm

0.5 mm

0.5 mm

0.75 mm

0.5 mm

1.27 mm

0.65 mm

0.65 mm

0.635 mm

0.5 mm

21X34

24X23

29X66
4000

41/42XX

TQFP

48

24894

PSoC 4

SSOP

Wettable flanks package to allow automated optical inspection (AOI)

Document No. 001-89435 Rev. *L

192

Automotive PSoC Roadmap

Document No. 001-89435 Rev. *L

193

Automotive PSoC and MCU Portfolio


8-Bit

32-Bit ARM
Cortex-M0/M0+

32-Bit ARM
Cortex-M3

32-Bit ARM
Cortex-M4

32-Bit ARM
Cortex-M7

High Analog Integration

Ultra-Low-Power
8-/16-Bit Replacement

Mid-Range
Performance

High Performance

Next Generation

Analog and Digital Integration

Programmable System-on-Chip (PSoC) is the worlds only programmable embedded


system-on-chip integrating an MCU core, PABs1, PDBs2, programmable interconnect
and routing, and CapSense capacitive sensing
Flexible MCU (FM) is a portfolio of high-performance ARM Cortex-M-based
MCUs for industrial and consumer applications

PSoC 5LP
Cortex-M3
80 MHz, 256KB Flash
20 PAB1, 30 PDB2, 72 I/Os

PSoC 4
Cortex-M0
48 MHz, 128KB Flash
Up to 13 PAB1, 16 PDB2, 51 I/Os
PSoC 3
8051 CPU
67 MHz, 64KB Flash
Up to 19 PAB1, 30 PDB2, 72 I/Os
PSoC 1
M8C CPU
24 MHz, 32KB Flash
16 PAB1, 16 PDB2, 56 I/Os

PSoC 7
Cortex-M7
NDA Required, Contact Sales

PSoC 6
Cortex-M4 and Cortex-M0+
NDA Required, Contact Sales

FM7 MCUs
Cortex-M7
NDA Required, Contact Sales

FM4 MCUs
Cortex-M4
200 MHz, 2MB Flash, 190 I/Os

FM3 MCUs
Cortex-M3
144 MHz, 1.5MB Flash, 154 I/Os

PSoC Analog Coprocessor


CY8C4Axx
48 MHz, 32KB Flash
Up to 12 PAB1, 11 PDB2, 38 I/Os
FM0+ MCUs
Cortex-M0+
40 MHz, 512KB Flash, 102 I/Os

Concept Development Sampling Production


1

A programmable analog block that is configured using PSoC software to create analog front ends, signal conditioning circuits
with opamps and filters
2 A programmable digital block that is configured using PSoC software to implement custom digital peripherals and glue logic

Document No. 001-89435 Rev. *L

Industrial
Automotive
Availability

QQYY

QQYY

194

Automotive Portfolio: PSoC 1


M8C Core | 24 MHz
PSoC MCU

Programmable Digital

Intelligent Analog

Performance Analog

Analog: 2x CMP1

Analog: 1x/2x CMP1,


4xSC/CT PAB2
Interfaces: I2C, SPI, UART

Analog: 2x/4x CMP1,


6xSC/CT PAB2, PGA3
Interfaces: I2C, SPI, UART

Analog: 4x CMP1,
12x/16x SC/CT PAB2, PGA3
Interfaces: I2C, SPI, UART

Interfaces: I2C, SPI

CY8C29x66
32K/2K4, 44 GPIOs5
1x14-bit ADC6
Grades: A7 and E8
CY8C27x43
32K/2K4, 44 GPIOs5
CapSense, 1x14-bit ADC6
CY8C24894
16K/1K4, 56 GPIOs5
CapSense, 2x14-bit SAR ADC6
Grade: A7

CY8C28xxx
16K/1K4, 44 GPIOs5
CapSense, 4x14-bit ADC6

Performance

CY8C2xx45
16K/1K4, 38 GPIOs5
CapSense, 1x10-bit SAR ADC6
Grades: A7 and E8
CY8C21x34
8K/0.5K4, 28 GPIOs5
CapSense, 1x10-bit ADC6
Grades: A7 and E8

CY8C24x23
4K/0.25K4, 24 GPIOs5
CapSense, 1x14-bit ADC6
Grades: A7 and E8

CY8C23x33
8K/0.25K4, 26 GPIOs5
CapSense, 1x 8-bit SAR ADC6
CY8C24x93
32K/2K4, 36 GPIOs5
1x10-bit ADC6

CY8C21x23
4K/0.25K4, 16 GPIOs5
1x10-bit ADC6

Integration
1 Comparator
2 Switched

capacitor/continuous time programmable analog block


3 Programmable gain amplifier
4 Flash KB/SRAM KB
5 General-purpose input/output pins

Document No. 001-89435 Rev. *L

6 Analog-to-digital

converter: Includes incremental, successive


approximation register (SAR) or Delta-Sigma () ADCs
7 AEC-Q100: -40C to +85C
8 AEC-Q100: -40C to +125C

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

195

Automotive Portfolio: PSoC 4


ARM Cortex-M0/M0+ | CapSense | Timer/Counter/PWM
PSoC MCU
PSoC 4000

Intelligent Analog
PSoC 4100
BL = BLE-Series

Programmable Digital
PSoC 4200
S = S-Series

M = M-Series

CY8C4248-L
48-MHz M0, 256K/32K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7, CAN8
USB

CY8C4248-BL
48-MHz M0, 256K/32K1
CMP2, Opamp, ADC3
SCB4, IDAC5, BLE6, UDB7

CY8C4247-M Q416
48-MHz M0, 128K/16K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7, CAN8
Grades: A10 and S11

CY8C4247-L
48-MHz M0, 128K/16K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7, CAN8,
USB

CY8C4247-BL
48-MHz M0, 128K/16K1
CMP2, Opamp, ADC3
SCB4, IDAC5, BLE6, UDB7

CY8C4246-M Q416
48-MHz M0, 64K/8K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7
Grades: A10 and S11

CY8C4246-L
48-MHz M0, 64K/8K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7, CAN8
USB

Flash

CY8C4128-BL
24-MHz M0, 256K/32K1
CMP2, Opamp, ADC3
SCB4, IDAC5, BLE6

Q316

CY8C4045-S
48-MHz M0+, 32K/4K1
NDA Contact Sales
Q316

CY8C4024-S
24-MHz M0+, 16K/2K1
NDA Contact Sales

CY8C4127-M Q416
24-MHz M0, 128K/16K1
CMP2, Opamp, ADC3
SCB4, IDAC5
Grades: A10 and S11

CY8C4127-BL
24-MHz M0, 128K/16K1
CMP2, Opamp, ADC3
SCB4, IDAC5, BLE6

CY8C4126-M Q416
24-MHz M0, 64K/8K1
CMP2, Opamp, ADC3
SCB4, IDAC5
Grades: A10 and S11

CY8C4146-S
48-MHz M0+, 64K/8K1
NDA Contact Sales

CY8C4125
24-MHz M0, 32K/4K1
CMP2, Opamp, ADC3
SCB4, IDAC5
Grades: A10 and S11

CY8C4125-S
24-MHz M0+, 32K/4K1
NDA Contact Sales

CY8C4124
24-MHz M0, 16K/4K1
CMP2, Opamp, ADC3
SCB4, IDAC5
Grades: A10 and S11

CY8C4124-S
24-MHz M0+, 16K/2K1
NDA Contact Sales

CY8C4244
48-MHz M0, 16K/4K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7
Grades: A10 and S11

7 Universal

10

Q316

Q316

Q316

L = L-Series

CY8C4245
48-MHz M0, 32K/4K1
CMP2, Opamp, ADC3
SCB4, IDAC5, UDB7
Grades: A10 and S11

CY8C4014
16-MHz M0, 16K/2K1
CMP2, I2C, IDAC5
Grades: A10 and S11
Concept Development Sampling Production
1 Flash

KB/SRAM KB
2 Comparator
3 Analog-to-digital converter

4 Serial

communication block
5 Current-output DAC
6 Bluetooth Low Energy

Document No. 001-89435 Rev. *L

digital block
8 Controller area network
9 Programmable I/Os

AEC-Q100: -40C to +85C


11 AEC-Q100: -40C to +105C

Industrial
Automotive
Availability

QQYY

QQYY

196

Automotive Portfolio:
PSoC Software1
Software
Current Version

PSoC Creator2

PSoC Designer

3.3 CP3

PSoC 1
PSoC 4

Production

PSoC Programmer4

EZ-Click

5.4 SP1

3.24.4

2.0 SP1

Production

Production

Production

Download the latest PSoC software version here

1 All

software and tool releases are backward compatible. The latest versions are recommended for new designs
Creator is an Integrated Design Environment (IDE) that allows concurrent hardware and firmware design of PSoC 3 and PSoC 4 systems
3 PSoC Designer is an IDE that enables firmware design using a library of precharacterized peripherals for PSoC 1 systems
4 PSoC Programmer can be used with PSoC Designer and PSoC Creator to program and debug any design onto a PSoC device
5 EZ-Click is a Windows GUI-based tool that enables development of CapSense MBR solutions. It allows you to set up sensor configuration, apply global system properties, monitor real-time
sensor output, and run production-line system diagnostics
2 PSoC

Document No. 001-89435 Rev. *L

197

Automotive PSoC 4100-Series


Intelligent Analog Family
Block Diagram

MCU and discrete analog replacement


Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning

PSoC 4 One-Chip Solution


MCU Subsystem

Programmable Analog
Blocks
Opamp
x1

32-bit MCU Subsystem


24-MHz ARM Cortex-M0 CPU
Up to 32KB flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 806-Ksps SAR2 ADC
CapSense with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four configurable 16-bit timer, counter or pulse-width modulator
(TCPWM) blocks
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP

Collateral
Datasheet:

24 MHz

Flash
(16KB to 32KB)

SRAM
(4KB)

CMP
x2

GPIO x6

SAR2
ADC

CSD

Programmable Digital
Blocks
TCPWM x4

SCB x2

Segment LCD Drive

GPIO x4

GPIO x6

GPIO x4

Serial Wire Debug


GPIO x4

Availability
Automotive PSoC 4100 Datasheet

1 Programmable
2 Successive

Cortex-M0

Advanced High-Performance Bus (AHB)

Features

I/O Subsystem

Programmable Interconnect and Routing

Applications

gain amplifier
approximation register

Document No. 001-89435 Rev. *L

3 Industrial:

Sampling:
Production:

Now
Now

-40C to +85C

198

Automotive PSoC 4200-Series


Programmable Digital Family

MCU and discrete analog replacement


Digital and analog one-chip sensor hub
User interface for heating, ventilation, air conditioning

Block Diagram
PSoC 4 One-Chip Solution
MCU Subsystem

Programmable Analog
Blocks
Opamp
x1

32-bit MCU Subsystem


48-MHz ARM Cortex-M0 CPU
Up to 32KB flash and 4KB SRAM
Programmable Analog Blocks
Two comparators (CMP)
One opamp, configurable as PGA1, CMP, filter, etc.
One 12-bit, 1-Msps SAR2 ADC
CapSense with SmartSense Auto-tuning
One Cypress Capacitive Sigma-Delta (CSD) controller
Capacitive sensing supported on up to 24 pins
Programmable Digital Blocks
Four universal digital blocks (UDBs): custom digital peripherals
Four configurable TCPWM3 blocks: 16-bit timer, counter or PWM
Two configurable serial communication blocks (SCBs): I2C master
or slave, SPI master or slave, UART or LIN slave
Packages
28-pin SSOP

Collateral
Datasheet:

Cortex-M0
48 MHz

Flash
(16KB to 32KB)

SRAM
(4KB)

Serial Wire Debug

Advanced High-Performance Bus (AHB)

Features

CMP
x2

I/O Subsystem
GPIO x6

SAR2
ADC

CSD

Programmable Digital
Blocks
UDB x4

TCPWM3 x4

SCB x2

Segment LCD Drive

Programmable Interconnect and Routing

Applications

GPIO x4

GPIO x6

GPIO x4

GPIO x4

Availability
Automotive PSoC 4200 Datasheet

Sampling:
Production:

Now
Now

1 Programmable

gain amplifier
approximation register
3 Timer, counter, pulse-width modulator
2 Successive

Document No. 001-89435 Rev. *L

199

Automotive PSoC Packages


Package

LQFP

Pins
Body Size
Family

Pitch

PSoC 1

2XX45

QFN

SOIC

24

40

56

16

20

28

48

64

7 x 7 mm

4 x 4 mm

6 x 6 mm

8 x 8 mm

150 Mil

210 Mil

5 x 10 mm

300 Mil

10 x 10 mm

0.5 mm

0.5 mm

0.75 mm

0.5 mm

1.27 mm

0.65 mm

0.65 mm

0.635 mm

0.5 mm

21X34

24X23

29X66

4000

41/42XX

TQFP

48

24894

PSoC 4

SSOP

Wettable flanks package to allow automated optical inspection (AOI)

Document No. 001-89435 Rev. *L

200

Automotive Instrument Traveo Cluster MCUs

Document No. 001-89435 Rev. *L

201

Feature Overview
Traveo Instrument Cluster MCU Family

QPRC1
I/O Timer2

Source Clock
Timer

External NMI/
External IRQ5

IRQ

DMA6

Standard I/O
Relocation

Watchdog
CSV7

Oscillators

PLLs
SSCG PLL8

Power Mgmt.
Temp. Sensor9

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU13

TPU14

Reload Timer

Boot ROM
RTC3

OCD (JTAG)
Trace10

Cortex R5F
FPU, Safety, Security

Sound
LVD11

CRC12

eSHE

Wave Gen x5
Mixer
SMC + ZPD4

TCON15

3D Engine

Base Timer

VRAM

12-bit ADC

Command
Sequence

Video In

Dithering
Gamma16
Vector
Drawing

2D Engine

Signature
Unit

Video Out/
LCD Bus

HyperBus

3-Pin MLB17

4-bit x2
DDR HSSPI18

APIX AIC19

Multifunctional
Serial

CAN FD

Ethernet AVB20

PCM/PWM21

Audio-DAC

I2S22

4COM x 32SEG
LCDC

EBI23

15

16

Quad position and revolution counter


Input/output timer
3 Real-time clock
4 Stepper motor control + zero point detection
5 Nonmaskable interrupt/interrupt request
6 Direct memory access
7 Clock supervisor

Document No. 001-89435 Rev. *L

Spread-spectrum clock generator/phase-locked loop


Power management, temperature sensor
10 On-chip debug (Joint Test Action Group)
11 Low-voltage detection
12 Cyclic redundancy check
13 Peripheral protection units
14 Timing protection unit

Timing controller
Dithering and gamma correction
17 Media local bus
18 Double data rate high-speed serial peripheral
interface
19 Automotive pixel link/automatic interconnect
20 Audio/video bridging

21

Pulse-code modulation/pulse-width
modulation
22 Inter-IC sound bus
23 External bus interface

202

S6J3120 Series
Traveo Instrument Cluster MCU Family: Virgo
Applications

Block Diagram1

Instrument clusters
2-ch QPRC

Features
32-bit MCU Core Systems
112-MHz ARM Cortex-R5, up to 1MB Flash and
80KB RAM with backup RAM
Supply Voltage
5.0 V
Interfaces
3-ch CAN FD, DDR HSSPI, 10-ch multifunctional serial
Cluster Features
4COM x 32SEG LCDC and 3-ch sound generator
Package
144-pin TEQFP

4-ch Source
Clock Timer

External NMI/
16 External IRQ

IRQ

16-ch DMA

Standard I/O
Relocation

Watchdog
CSV

Oscillators

PLLs
SSCG PLL

Power
Management

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU

TPU

12-ch I/O Timer


10-ch Reload
Timer

Boot ROM
RTC

Cortex R5
Safety, Security

OCD (JTAG)
Trace
Sound
LVD

CRC

4-ch SMC ZPD

Datasheet:
S6J3120 Series
Hardware Manual: S6J3120 Series
1

TCON

3D Engine

30-ch Base
Timer

VRAM

50-ch 12-bit
ADC

Command
Sequencer

Video In

Dithering
Gamma
2D Engine

Vector
Drawing

Signature Unit

Video Out

HyperBus

3-Pin MLB

1-ch 4-bit x2
DDR HSSPI

APIX AIC

10-ch Multifunctional
Serial

3-ch CAN FD

Ethernet AVB

PCM/PWM

Audio-DAC

I2S

EBI

Collateral

eSHE

Wave Gen
Mixer

4COM x 32SEG
LCDC

Availability
Sampling: Now
Production: Q3 2016

Blue boxes highlighted in the block diagram indicate features available on the device shown. Gray boxes indicate omitted features.

Document No. 001-89435 Rev. *L

203

S6J3200 Series
Traveo Instrument Cluster MCU Family: Amethyst (1MB)/Amber (2MB)
Applications

Block Diagram7

Instrument clusters, head-up displays (HUDs), HVACs


2-ch QPRC

Features
32-bit MCU Core Systems
Up to 240-MHz ARM Cortex-R5F, 2MB Flash,
256KB RAM with backup RAM and 2MB VRAM
Supply Voltages
1.2 V, 3.3 V or 5.0 V
Interfaces
4-ch CAN FD, 2-ch DDR HSSPI, 3-ch HyperBus1,
12-ch multifunctional serial, MLB2, Ethernet AVB3
Cluster Features
3D OpenGL ES1.1 on-the-fly (optional), 2D engine,
2-ch (maximum)/1-ch (maximum) video-out/-in,
audio-DAC, PCM/PWM4 and I2S5
Packages
208-pin TEQFP, 216-pin TEQFP and 256-pin TEQFP6

Collateral

External NMI/
32 External IRQ

IRQ

16-ch DMA

Standard I/O
Relocation

Watchdog
CSV

Oscillators

PLLs
SSCG PLL

Power
Management

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU

TPU

24-ch I/O Timer


10-ch
Reload Timer

Boot ROM
RTC
OCD (JTAG)
Trace

Cortex

R5F
FPU, Safety, Security

Sound
LVD

CRC

eSHE

Wave Gen x5
Mixer
6-ch
SMC ZPD

TCON

3D Engine

24-ch
Base Timer

VRAM

50-ch
12-bit ADC

Command
Sequencer

Dithering
Gamma
2D Engine

Vector
Drawing

Signature
Unit

1-ch Video In

2-ch
RGB/LVDS
Video Out

3-ch (maximum)
HyperBus

1-ch 3-Pin MLB

2-ch 4-bit x2
DDR HSSPI

APIX AIC

12-ch Multifunctional
Serial

4-ch CAN FD

1-ch Ethernet AVB

1-ch PCM/PWM

Audio-DAC

2-ch I2S

4COM x 32SEG
LCDC

EBI

Datasheet:
S6J3200 Series
Hardware Manual: S6J3200 Series
Cypresss high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 Audio/video bridging
4 Pulse-code modulation/pulse-width modulation
5 Inter-IC sound bus
6 Contact Sales for 256-pin TEQFP availability
7 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.

4-ch Source
ClocK Timer

Document No. 001-89435 Rev. *L

Availability
Amethyst
Amber

Sampling:
Production:
Sampling:
Production:

Now
Q3 2016
Now
Q3 2016
204

S6J3300 Series
Traveo Instrument Cluster MCU Family: Juno (4MB)/Artemis (2MB)
Applications

Block Diagram8

Instrument clusters, vehicle controllers


2-ch QPRC

Features

4-ch Source
Clock Timer

External NMI/
24 External IRQ

IRQ

16-ch DMA

Standard I/O
Relocation

Watchdog
CSV

Oscillators

PLLs
SSCG PLL

Power
Management

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU

TPU

12-ch I/O Timer

32-bit MCU Core Systems


240-MHz ARM Cortex-R5F, up to 4MB Flash and
512KB RAM with backup RAM
Supply Voltages
1.15V, 3.3V or 5.0V
Interfaces
6-ch CAN FD, DDR HSSPI, HyperBus1, MLB2,
12-ch multifunctional serial, EBI3, APIX AIC4 and
Ethernet AVB4
Cluster Features
Simple video out and LCD-bus interface audio-DAC,
PCM/PWM6 and I2S7
Packages
144-pin TEQFP, 176-pin TEQFP, 208-pin TEQFP

6-ch Reload
Timer

Boot ROM
RTC
OCD (JTAG)
Trace
Sound
LVD

CRC

eSHE

Wave Gen x5
Mixer

6-ch SMC ZPD

TCON

3D Engine

32-ch Base
Timer

VRAM

32+16-ch
12-bit ADC

Command
Sequencer

1-ch Video In

Dithering
Gamma
2D Engine

Vector
Drawing

Signature
Unit

LCD Bus
Video-Out

1-ch HyperBus

1-ch 3-Pin MLB

1-ch 4-bit x2
DDR HSSPI

APIX AIC

12-ch Multifunctional
Serial

6-ch CAN FD

1-ch Ethernet AVB

1-ch PCM/PWM

Audio-DAC

2-ch I2S

Collateral
Datasheet:
S6J331x Series
Hardware Manual: S6J3300 Series
Cypresss high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
2 Media local bus
3 External bus interface
4 Automotive pixel link/automatic interconnect
5 Audio/video bridging
6 Pulse-code modulation/pulse-width modulation
7 Inter-IC sound bus
8 Blue boxes highlighted in the block diagram indicate features available on the
device shown. Gray boxes indicate omitted features.

Cortex R5F
FPU, Safety, Security

4COM x 32SEG
LCDC

EBI2

Document No. 001-89435 Rev. *L

Availability
Juno
Artemis

Sampling:
Production:
Sampling:
Production:

Now
Q1 2017
July 2016
Q1 2017
205

Automotive Traveo Body


Control MCUs

Document No. 001-89435 Rev. *L

206

Feature Overview
Traveo Body Control MCU Family

QPRC1
I/O Timer2

Source Clock
Timer

External NMI/
External IRQ4

Partial
Wakeup

DMA5

Standard I/O
Relocation

Watchdog
CSV6

Oscillators

PLLs
SSCG PLL7

Power
Management

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU11

TPU12

Reload Timer
Boot ROM
RTC3

OCD (JTAG)
Trace8
LVD9

Cortex R5F
FPU, Safety, Security

CRC10

eSHE

4-bit x2 DDR
HSSPI13

HyperBus
Base Timer

CAN FD

Ethernet AVB14

12-bit ADC

EBI15

FlexRay

11

12

Quad position and revolution counter


Input/output timer
3 Real time clock
4 Nonmaskable interrupt/Interrupt request
5 Direct memory access

Document No. 001-89435 Rev. *L

Clock supervisor
Spread-spectrum clock generator/phase-locked loop
8 On-ship debug (Joint Test Action Group)
9 Low-voltage detection
10 Cyclic redundancy check

13
14
15

Multifunctional
Serial

Peripheral protection units


Timing protection unit
Double data rate high-speed serial peripheral interface
Audio/video bridging
External bus interface

207

S6J3110 Series
Traveo Body Control MCU Family: Leo (4MB)/Aries (1MB)
Applications

Block Diagram2

Body control modules (BCM), HVACs, gateways, lighting,


infotainment

Features
32-bit MCU Core System
144-MHz/96-MHz ARM Cortex-R5, up to 4MB Flash
and 384KB RAM with backup RAM
Supply Voltage
5.0 V
Interfaces
Up to 2-ch CAN FD and 22-ch multifunctional serial
AD Converter
Up to 64 ch
Timers
Up to 12-ch I/O timer1 and 30-ch base timer
Packages
144-pin TEQFP and 176-pin TEQFP

Collateral
Datasheets:

S6J3118 to S6J311A Series (Aries)


S6J311B to S6J311E Series (Leo)
Hardware Manuals: Contact Sales

1
2

3-ch Source
Clock Timer

External NMI/
16 External IRQ

Partial
Wakeup

DMA

Standard I/O
Relocation

12-ch I/O Timer

Watchdog
CSV

Oscillators

PLLs
SSCG PLL

Power
Management

Flash

Reload Timer

GPIO

D-Cache

Work-Flash

RTC

OCD (JTAG)
Trace

I-Cache

RAM

PPU

TPU

QPRC

LVD

Cortex R5
Safety, Security

CRC

eSHE

HyperBus

DDR HSSPI

30-ch Base
Timer

2-ch 192-msg
CAN FD

Ethernet AVB

32-ch x2
12-bit ADC

EBI

FlexRay

22-ch Multifunctional
Serial

Availability
Leo
Aries

Sampling:
Production:
Sampling:
Production:

Now
August 2016
Now
Q3 2016

Input/output timer
Blue boxes highlighted in block diagram indicate features available on the device shown. Gray boxes indicate omitted features

Document No. 001-89435 Rev. *L

208

S6J3350 Series
Traveo Body Control MCU Family: Neptune
Applications

Block Diagram5

Body control modules (BCM), gateways


2-ch QPRC

4-ch Source
Clock Timer

External NMI/
24 External IRQ

Partial
Wakeup

DMA

Standard I/O
Relocation

Watchdog
CSV

Oscillators

PLLs
SSCG PLL

Power
Management

Flash

D-Cache

Work-Flash

I-Cache

RAM

PPU

TPU

Features
32-bit MCU Core Systems
240-MHz ARM Cortex-R5F, up to 4MB Flash and
512KB RAM with backup RAM
Supply Voltages
1.15 V, 3.3 V, or 5.0 V
Interfaces
Up to 8-ch CAN FD, up to 12-ch multifunctional serial,
Ethernet AVB1, HyperBus2, 2-ch DDR HSSPI, EBI3
AD Converter
Up to 64 ch (2 units)
Timers
Up to 12-ch I/O timer4 and 64-ch base timer
Packages
144-pin TEQFP, 176-pin TEQFP and 208-pin TEQFP

12-ch I/O Timer

6-ch Reload
Timer

GPIO

1-ch RTC

OCD (JTAG)
Trace

LVD

Cortex R5F
FPU, Safety, Security

CRC

eSHE

1-ch
HyperBus

1-ch 4-bit x2
DDR HSSPI

64-ch Base
Timer

8-ch 192-msg
CAN FD

1-ch
Ethernet AVB

32-ch x2
12-bit ADC

EBI

FlexRay

12-ch
Multifunctional Serial

Collateral
Datasheet:
S6J3350 Series
Hardware Manual: S6J3300 Series
1

Audio/video bridging
Cypresss high-bandwidth, 12-signal interface that transfers data over 8 I/O
signals at double data rate (DDR), delivering 333 MBps
3 External bus interface
4 Input/output timer
5 Blue boxes highlighted in block diagram indicate features available on the
device shown. Gray boxes indicate omitted features

Availability
Sampling:
Production:

Now
Q1 2017

Document No. 001-89435 Rev. *L

209

Automotive Traveo MPN Selector Guides

Document No. 001-89435 Rev. *L

210

Product Selector Guide


S6J3110 Series (Leo/Aries), S6J3120 Series (Virgo)
Part Number
S6J311
S6J311
S6J312

Flash
1.5/2/3/4MB
512/768KB, 1MB
512/768KB, 1MB

RAM
128/192/256/320KB
48/64/80KB
48/64/80KB

SHE1
On/Off
On/Off
On/Off

Chip Erase
Controllable
Controllable
Controllable

Package
TEQFP-144/176
TEQFP-144
TEQFP-144

S6J310 Part Numbering Decoder


S6J 3 1 X X X X X X XX X XXX
Reserved
Packing:

0 = Tray

Packages: E2 = TEFP 0.5-mm Pitch

Reliability:

S = GS Grade, E = ES Grade

Revision:

Option:

A = SHE On + Chip Erase (Controllable)2


B = SHE Off + Chip Erase (Controllable)

Pins:

H = 144, J = 176

Flash Size: 8 = 512KB, 9 = 768KB, A = 1MB


C = 2MB, D = 3MB, E = 4MB
Function:

1 = Body, 2 = Cluster

Product ID: 1 = S6J310 Series


Core:

3 = R5

ID:

S6J = Cypress Automotive MCU

1 Secure
2

hardware extension
Chip erase can be constantly disabled via the chip erase enable register

Document No. 001-89435 Rev. *L

211

Product Selector Guide


S6J335 Series (Neptune)
Part Number
S6J335

Flash
1.5/2/3/4MB

RAM
192/256/384/512KB

ETH1
Yes

SHE2
On/Off

Chip Erase
Enabled/Controllable

VCC / DVCC
5/5 V, 3/5 V, 3/3 V

Package
TEQFP-144/176/208

S6J335 Part Numbering Decoder


S6J 3 3 5 X X X X X XX X XXX
Reserved

Packing:

0 = Tray

Packages:

C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch

Reliability:

S = GS Grade, E = ES Grade

Revision:

Option:

S = SHE On + Chip Erase (Enabled)


T = SHE On + Chip Erase (Controllable)3
U = SHE Off + Chip Erase (Enabled)
V = SHE Off + Chip Erase (Controllable)
S/U/T/V = VCC/DVCC: 5/5 V, A/C/E/G = VCC/DVCC: 3/5 V
B/D/F/H = VCC/DVCC: 3/3 V

Pins:

H = 144, J = 176, K = 208

Flash Size: B = 1.5MB, C = 2MB, D = 3MB, E = 4MB


Function:

5 = ETH

Product ID: 3 = S6J330 Series

1 Ethernet
2

audio/video bridging
Secure hardware extension

Document No. 001-89435 Rev. *L

Core:

3 = R5

ID:

S6J = Cypress Automotive MCU

Chip erase can be constantly disabled via the chip erase


enable register

212

Product Selector Guide


S6J331 Series (Juno/Artemis)
Part Number
S6J331
S6J332
S6J333
S6J334

Flash
1.5/2/3/4MB
1.5/2/3/4MB
1.5/2/3/4MB
1.5/2/3/4MB

RAM
512KB
512KB
512KB
512KB

2D
Yes
Yes
Yes
Yes

ETH1
Yes
Yes
Yes
No

MLB2
Yes
Yes
Yes
No

SS3
Yes
Yes
No
No

APIX4
Yes
No
No
No

SHE5
On/Off
On/Off
On/Off
On/Off

Chip Erase
Enabled/Controllable
Enabled/Controllable
Enabled/Controllable
Enabled/Controllable

VCC / DVCC
5/5 V, 3/5 V, 3/3 V
5/5 V, 3/5 V, 3/3 V
5/5 V, 3/5 V, 3/3 V
5/5 V, 3/5 V, 3/3 V

Package
TEQFP-144/176/208
TEQFP-144/176/208
TEQFP-144/176/208
TEQFP-144/176/208

S6J331 Part Numbering Decoder


S6J 3 3 X X X X X X XX X XXX
Reserved
Packing:

0 = Tray

Packages:

C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch

Reliability:

S = GS Grade, E = ES Grade

Revision:

Option:

S/A/B = SHE On + Chip Erase (Enabled)


T/E/F = SHE On + Chip Erase (Controllable)6
U/C/D = SHE Off + Chip Erase (Enabled)
V/G/H = SHE Off + Chip Erase (Controllable)
S/U/T/V = VCC/DVCC: 5/5 V, A/C/E/G = VCC/DVCC: 3/5 V
B/D/F/H = VCC/DVCC: 3/3 V

Pins:

H = 144, J = 176, K = 208

Flash Size: B = 1.5MB, C = 2MB, D = 3MB, E = 4MB


Function:

1 = 2D + ETH + MLB + SS + APIX + MK_CEER


2 = 2D + ETH + MLB + SS, 3 = 2D + ETH +MLB, 4 = 2D

Product ID: 3 = S6J330 Series

1 Ethernet

audio/video bridging
2 Media local bus
3 Sound system

4 Automotive

pixel link
5 Secure hardware extension

Document No. 001-89435 Rev. *L

Core:

3 = R5

ID:

S6J = Cypress Automotive MCU

6 Chip

erase can be constantly


disabled via the chip erase
enable register

213

Product Selector Guide


S6J320 Series (Amber/Amethyst)
Part Number
S6J323
S6J324
S6J325
S6J326
S6J327
S6J328
S6J32A
S6J32B
S6J32C
S6J32D

Flash
2MB
2MB
2MB
2MB
2MB
2MB
1MB
1MB
1MB
1MB

RAM
256KB
256KB
256KB
256KB
256KB
256KB
128KB
128KB
128KB
128KB

VRAM
2MB
2MB
2MB
2MB
2MB
2MB
1MB
1MB
1MB
1MB

2D
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes

3D
No
No
Yes
Yes
No
Yes
No
No
Yes
Yes

SS1
No
Yes
No
Yes
Yes
Yes
No
Yes
No
Yes

LVDS2
No
No
No
Yes
No
Yes
No
No
No
No

2HB3
No
No
No
No
Yes
Yes
No
No
No
No

SHE4
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off

Package
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216/2565
TEQFP-208/216
TEQFP-208/216
TEQFP-208/216
TEQFP-208/216

S6J320 Part Numbering Decoder


S6J 3 2 X X X X X X XX X XXX
Reserved
Packing:

0 = Tray

Packages:

C2 = TEQFP 0.4-mm Pitch, E2 = TEQFP 0.5-mm Pitch

Reliability:

S = GS Grade, E = ES Grade

Revision:

Option:

S = SHE On, U = SHE Off

Pins:

K = 208, L = 216, M = 256

Flash Size: A = 1MB, C = 2MB


Function:

3 = 2D, 4 = 2D + SS, 5 = 2D + 3D, 6 = 2D + 3D + SS + LVDS,


7 = 2D + SS + 2HB, 8 = 2D + 3D + SS + LVDS + 2HB, A = 2D,
B = 2D + SS, B = 2D + SS, C = 2D, D = 2D + 3D + SS

Product ID: 2 = S6J320 Series

1 Sound

4 Secure

system
Low-voltage differential
signaling interface

Second HyperBus interface


hardware extension

Document No. 001-89435 Rev. *L

Core:

3 = R5

ID:

S6J = Cypress Automotive MCU

Contact Sales for 256-pin


TEQFP availability

214

Automotive Asynchronous SRAM

Document No. 001-89435 Rev. *L

215

Automotive Portfolio:
Asynchronous SRAM
Low-Power SRAM (MoBL1)

Fast SRAM
ECC3

32Mb-128Mb

Non-ECC

CY7C107x
32Mb; 3.3 V
12 ns; x8, x16

2Mb-16Mb

Serial SRAM (with ECC3)

Non-ECC

ECC3

ECC3

Quad-SPI4

HyperBus5

CY6218x
64Mb; 1.8, 3.0 V
55 ns; x16

Other densities
NDA Contact Sales

Other densities
NDA Contact Sales

Other densities
NDA Contact Sales

Other densities
NDA Contact Sales

CY6217x
32Mb; 1.8-5.0 V
55 ns; x16

CY7C106x
16Mb; 1.8, 3.3 V
10 ns; x8, x16, x32

64Kb-1Mb

PowerSnooze2

CY7C106x
16Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Grades: E6

CY6216x
16Mb;1.8, 3.0, 5.0 V
45 ns; x8, x16
Grades: A7

CY6216x
16Mb; 1.8-5.0 V
45 ns; x8, x16, x32
Grades: A6 and E5

CY7C105x
8Mb; 3.3 V
10 ns; x8, x16

CY7C1012
12Mb; 3.3 V
10 ns; x24

CY7C105x
8Mb; 1.8-5.0 V
10 ns; x8, x16, x32
Grade: E5

CY6215x
8Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Grades: A7 and E6

CY6215x
8Mb; 1.8-5.0 V
45 ns; x8, x16, x32
Grade: A6 and E5

CY7C104x
4Mb; 3.3, 5.0 V
10 ns; x4, x8, x16
Grades: A7 and E6

CY7C1034
6Mb; 3.3 V
10 ns; x24

CY7C104x
4Mb; 1.8-5.0 V
10 ns; x8, x16
Grades: E6

CY6214x
4Mb; 1.8, 3.0, 2.5-5V
45 ns; x8, x16
Grades: A7 and E6

CY6214x
4Mb; 1.8-5.0 V
45 ns; x8, x16
Grades: A7 and E6

CY7C1010/11
2Mb; 3.3 V
10 ns; x8, x16
Grades: A7 and E6

CY7C1024
3Mb; 3.3 V
10 ns; x24

CY6213x
2Mb; 1.8, 2.5-5.0 V
45 ns; x8, x16
Grades: A7 and E6

CY7L02Mx
2Mb; 1.8, 3.3 V
40 MHz, 133 MHz
Grades: E6

CY7C1020
512Kb; 2.6, 3.3, 5.0 V
10 ns; x16
Grades: E6

CY7C1019/21
1Mb; 2.6, 3.3, 5.0 V
10 ns; x4, x8, x16
Grades: A7 and E6

CY6212x
1Mb; 2.5-5.0 V
45 ns; x8, x16
Grades: A7 and E6

CY7L01Mx
1Mb; 1.8, 3.3 V
40 MHz, 133 MHz
Grades: E6

CY7C185
64Kb; 5.0 V
15 ns; x8

CY7C199
256Kb; 3.3, 5.0 V
10 ns; x4, x8
Grades: A7 and E6

CY6264/62256
64-256Kb; 1.8, 3.0, 5V
55 ns, 70 ns; x8
Grades: A7 and E6

CY7L064/256x
64, 256Kb; 1.8, 3.3 V
40 MHz, 133 MHz
Grades: E6

More Battery Life


SRAM with low-power sleep mode
3 Error-correcting code
1

2 Fast

Document No. 001-89435 Rev. *L

6 AEC-Q100: -40C to +125C


Serial peripheral interface
7 AEC-Q100: -40C to +85C
A high-bandwidth,12-signal interface that transfers
information over 8 I/O signals at Double Data Rate (DDR),
delivering up to 400 MBps

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

216

Fast SRAM with ECC


Applications

Family Table

Infotainment systems
Driver assistance
Driver information
Powertrain
Telematics

Density

MPN

Access Time

2Mb
4Mb
8Mb
16Mb

CY7C101x
CY7C104x
CY7C105x
CY7C106x

10 ns
10 ns
10 ns
10 ns

Supply Current
(Max. at 85C)
45 mA
45 mA
110 mA
110 mA

Block Diagram
Features
Access time: 10 ns
Multiple bus-width configurations: x8, x16, x32
Wide operating voltage range: 1.65-5.5 V
Available in automotive temperature (A1 and E2) grades
Industry-standard, RoHS-compliant packages
Error-correcting code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Packages: 48-pin VFBGA, 48-pin TSOP1

Fast SRAM with ECC


SRAM Array

18-23
Address

ECC
Encoder

Input
Buffer
8, 16, 32
Data

I/O Mux

Address
Decoder

Sense
Amps

SRAM Array

ECC
Decoder

Collateral
Datasheets:

16Mb CY7C106x
8Mb CY7C105x
4Mb CY7C104x
2Mb CY7C101x

Control Logic

CE

-40C to +85C

2 AEC-Q100:

Document No. 001-89435 Rev. *L

WE

BHE3

BLE4

Availability
Sampling:
Production:

1 AEC-Q100:

OE

-40C to +125C

3 Byte

high enable

Now
Now
4 Byte

low enable

217

MoBL

SRAM with ECC

Applications

Family Table

Infotainment systems
Telematics

Density

MPN

4Mb
8Mb
16Mb
32Mb
64Mb

CY6214x
CY6215x
CY6216x
CY6217x
CY6218x

Standby Current
(Max. at 85C)
8 A
9 A
16 A
58 A
58 A

Standby Current
(Typ. at 25C)
2.5 A
3.0 A
4.6 A
9.0 A
9.0 A

Block Diagram

Features
Access time: 45 ns for 16Mb
Standby current: 16 A for 16Mb
Multiple bus-width configurations: x8, x16 and x32
Wide operating voltage range: 1.65-5.5 V
Available in automotive temperature (A2 and E3) grades
Industry-standard, RoHS-compliant packages
Error-correcting code (ECC) to detect/correct single-bit errors
Bit-interleaving to avoid multi-bit errors
Packages: 48-pin VFBGA, 48-pin TSOP1

MoBL1 SRAM with ECC


SRAM Array

18-23

Address

Address
Decoder

ECC
Encoder

Input
Buffer
8, 16, 32
Data

I/O Mux

SRAM Array

Sense
Amps

ECC
Decoder

Collateral
Datasheets:

Control Logic

16Mb CY6216x
4Mb CY6214x
CE

OE

WE

BHE4

BLE5

Availability
Sampling:
Production:
1 More

Battery Life

2 AEC-Q100:

Document No. 001-89435 Rev. *L

-40C to +85C

3 AEC-Q100:

-40C to +125C

4 Byte

high enable

Now (4Mb, 16Mb), Q3 2016 (8Mb)


Now (4Mb, 16Mb), Q3 2016 (8Mb)
5 Byte

low enable

218

Automotive Synchronous SRAM

Document No. 001-89435 Rev. *L

219

Automotive Portfolio: Synchronous SRAM


High Random Transaction Rate (RTR)1 | Low Latency | High Bandwidth
Standard Sync
and NoBL

Standard Sync and


NoBL with ECC2

QDR -II/
DDR-II

QDR-II+/
DDR-II+

QDR-II+X/
DDR-II+X

QDR-IV

Max RTR1: 250 MT/s


Max BW: 18 Gbps
Latency: 1 Cycle
Pipeline and
Flow-through Modes

Max RTR1: 250 MT/s


Max BW: 18 Gbps
Latency: 1 Cycle
Pipeline and
Flow-through Modes

Max RTR1: 666 MT/s


Max BW: 47.9 Gbps
Latency: 1.5 Cycles
CIO3 and SIO4

Max RTR1: 666 MT/s


Max BW: 79.2 Gbps
Latency: 2 or
2.5 Cycles
CIO3and SIO4, ODT5

Max RTR1: 900 MT/s


Max BW: 91.1 Gbps
Latency: 2.5 Cycles
SIO4, ODT5

Max RTR1: 2.1 GT/s


Max BW: 153.5 Gbps
Latency: 5 or 8 Cycles
Dual-Port Bidirectional
ODT5

CY7C161/2xKV18
144Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4

CY7Cx4/5/6/7xKV18
144Mb; 300-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C151/2xKV18
72Mb; 250-333 MHz
1.8 V; x9, x18, x36
Burst 2, 4

CY7Cx54/5/6/7KV18
72Mb; 250-550 MHz
1.8 V; x18, x36
RH6; Burst 2, 4

CY7C156/7xXV18
72Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4
CY7C126/7x
36Mb; 366-633 MHz
1.8 V; x18, x36
Burst 2, 4

Density

CY7C147/8xB
72Mb; 133-250 MHz
2.5, 3.3 V; x18, x36

CY7C144/6xA
36Mb; 133-250 MHz
2.5, 3.3 V; x36, x72

CY7C144/6xK
36Mb; 133-250 MHz
2.5, 3.3 V; x18, x36

CY7C141/2xKV18
36Mb; 250-333 MHz
1.8 V; x8, x9, x18, x36
Burst 2, 4

CY7Cx24/5/6/7xKV18
36Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C137/8xD
18Mb; 100-250 MHz
3.3 V; x18, x32, x36

CY7C137/8xK
18Mb; 100-250 MHz
2.5, 3.3 V; x18, x36

CY7C131/2/9xKV18
18Mb; 250-333 MHz
1.8 V; x8, x18, x36
Burst 2, 4

CY7Cx14/5/6/7xKV18
18Mb; 400-550 MHz
1.8 V; x18, x36
Burst 2, 4

CY7C136xC
9Mb; 100 MHz
3.3 V; x18, x36
Grade: E7

CY7C41xKV13
144Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2
CY7C40xKV13
72Mb; 667-1066 MHz
1.3 V; x18, x36
Burst 2

CY7C1911xKV18
18Mb; 250-333 MHz
1.8 V; x9
Burst 2, 4

CY7C134xxG
4Mb; 100 MHz
3.3 V; x36
Grade: E7

Random Transaction Rate


1 Rate

of truly random accesses to


memory, expressed in transactions
per second (MT/s, GT/s)

Document No. 001-89435 Rev. *L

2 Error-correcting
3 Common
4 Separate

I/O
I/O

code

5 On-die

termination; parts are CY7C2x


6 Radiation hardened, military grade
7 AEC-Q100: -40C to +125C

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

220

Automotive Nonvolatile RAM

Document No. 001-89435 Rev. *L

221

Automotive Portfolio: nvSRAM


High Density | High Speed
1 nvSRAM
SPI
nvSRAM
LPC

nvSRAM
ParallelParallel
nvSRAM
CY14B116R/S
16Mb; 3.0 V
25, 45 ns; x32; RTC2
Ind3

CY14B116K/L
16Mb; 3.0 V
25, 45 ns; x8; RTC2
Ind3

CY14V116F/G
16Mb; 3.0, 1.8 V I/O
30 ns; ONFI4 1.0
x8, x16; Ind3

Higher Densities
nvSRAM
NDA Contact Sales

CY14B104NA
4Mb; 3.0 V
25, 45 ns; x16; RTC2
Grade: E5

CY14B108K/L
8Mb; 3.0 V
25, 45 ns; x8; RTC2
Ind3

CY14B108M/N
8Mb; 3.0 V
25, 45 ns; x16; RTC2
Ind3

CY14B116M/N
16Mb; 3.0 V
25, 45 ns; x16; RTC2
Ind3

CY14B104K/LA
4Mb; 3.0 V
25, 45 ns; x8; RTC2
Ind3

CY14V104LA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x8
Ind3

CY14B104M/NA
4Mb; 3.0 V
25, 45 ns; x16; RTC2
Ind3

CY14V104NA
4Mb; 3.0, 1.8 V I/O
25, 45 ns; x16
Ind3

CY14V101PS
1Mb; 3.0, 1.8 V,
108 MHz QSPI7; RTC2
Ind3, Ext. Ind8

CY14V101QS
1Mb; 3.0, 1.8 V,
108 MHz QSPI7
Ind3, Ext. Ind8

CY14B101I
1Mb; 3.0 V
3.4 MHz I2C; RTC2
Ind3

CY14B101KA/LA
1Mb; 3.0 V
25, 45 ns; x8; RTC2
Ind3

CY14V101LA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x8
Ind3

CY14B101MA/NA
1Mb; 3.0 V
25, 45 ns; x16; RTC2
Ind3

CY14V101NA
1Mb; 3.0, 1.8 V I/O
25, 45 ns; x16
Ind3

CY14B101PA
1Mb; 3.0 V
40 MHz SPI; RTC2
Ind3

CY14B512P
512Kb; 3.0 V
40 MHz SPI; RTC2
Ind3

CY14B512I
512Kb; 3.0 V
3.4 MHz I2C; RTC2
Ind3

CY14B256KA/LA
256Kb; 3.0 V
25, 45 ns; x8; RTC2
Ind3

CY14V/U256LA
256Kb; 3.0, 1.8V I/O
35 ns; x8
Ind3

CY14E256LA
256Kb; 5.0 V
25, 45 ns; x8
Ind3

STK14C88-5
256Kb; 5.0 V
35, 45 ns; x8
Mil6

CY14B256P
256Kb; 3.0 V
40 MHz SPI; RTC2
Ind3

CY14B256I
256Kb; 3.0 V
3.4 MHz I2C; RTC2
Ind3

STK11C68-5
64Kb; 5.0 V
35, 55 ns; x8
Mil6

STK12C68-5
64Kb; 5.0 V
35, 55 ns; x8
Mil6

CY14B064P
64Kb; 3.0 V
40 MHz SPI; RTC2
Ind3

CY14B064I
64Kb; 3.0 V
3.4 MHz I2C; RTC2
Ind3

64Kb-256Kb

512Kb-16Mb

NEW

Higher Densities
nvSRAM
NDA Contact Sales

Concept Development Sampling Production


1 Low-pin-count
2 Real-time
3 Industrial

clock
grade: -40C to +85C

Document No. 001-89435 Rev. *L

4 Open

NAND flash interface


5 AEC-Q100: -40C to +125C
6 Military grade: -55C to +125C

Quad serial peripheral interface


8 Extended Industrial grade: -40C to +105C

Industrial
Automotive
Availability

QQYY

QQYY

222

Automotive nvSRAM Package


Package
Balls
Body Size

BGA
48
6 x 10 mm

Family

Pitch

0.75 mm

Parallel

4Mb

Document No. 001-89435 Rev. *L

223

Automotive Portfolio: F-RAM


Low Power | High Endurance
Processor
Companion

4Kb-256Kb

512Kb-4Mb

LPC1 F-RAM

Wireless
Memory

Parallel F-RAM

FM25H20/V20A
2Mb; H20: 2.7-3.6 V
V20A: 2.0-3.6 V
40 MHz SPI; Ind2

CY15B104Q
4Mb; 2.0-3.6 V
40 MHz SPI; Ind2

Higher Densities
F-RAM
NDA Contact Sales

FM22L16/LD16
4Mb; 2.7-3.6 V
55 ns; x8; Ind2

CY15B102Q
2Mb; 2.0-3.6 V
25 MHz SPI
Grade: E3

FM25V10/VN10
1Mb; 2.0-3.6 V
40 MHz SPI;
Grade: Ind2, A4

FM24V10/VN10
1Mb; 2.0-3.6 V
3.4 MHz I2C;
Grade: Ind2, A4

FM28V102A
1Mb; 2.0-3.6 V
60 ns; x16; Ind2

FM28V202A
2Mb; 2.0-3.6 V
60 ns; x16; Ind2

FM25V05
512Kb; 2.0-3.6 V
40 MHz SPI;
Grade: Ind2, A4

FM24V05
512Kb; 2.0-3.6 V
3.4 MHz I2C;
Grade: Ind2, A4

CY15B101N
1Mb; 2.0-3.6 V
60 ns; x16
Grade: A4

CY15B102N
2Mb; 2.0-3.6 V
60 ns; x16
Grade: A4

FM25V02/W256
256Kb; V02: 2.0-3.6 V
W256: 2.7-5.5 V
40 MHz SPI; Ind2, A4

FM24V02/W256
256Kb; V02: 2.0-3.6 V
W256: 2.7-5.5 V
3.4 MHz I2C; Ind2, A4

FM33256
256Kb; 3.3V; 16 MHz SPI
RTC5; Power Fail
Watchdog; Counter; Ind2

FM28V020
256Kb; 2.0-3.6 V
70 ns; x8; Ind2

FM18W08
256Kb; 2.7-5.5 V
70 ns; x8; Ind2

FM25V01A
128Kb; 2.0-3.6 V
40 MHz SPI;
Grade: Ind2, A4

FM24V01A
128Kb; 2.0-3.6 V
3.4 MHz I2C;
Grade: Ind2, A4

FM31256/31(L)278
256Kb; 3.3, 5.0V; 1 MHz
I2C; RTC5; Power Fail
Watchdog; Counter; Ind2

FM1808B
256Kb; 5.0 V
70 ns; x8; Ind2

FM16W08
64Kb; 2.7-5.5 V
70 ns; x8; Ind2

FM25640/CL64
64Kb; 3.3, 5.0 V
20 MHz SPI;
Grade: Ind2, E3

FM24C64/CL64
64Kb; 3.3, 5.0 V
1 MHz I2C;
Grade: Ind2, E3

FM3164/31(L)276
64Kb; 3.3, 5.0 V; 1 MHz
I2C; RTC5; Power Fail
Watchdog; Counter; Ind2

FM25C160/L16
16Kb; 3.3, 5.0 V
20 MHz SPI;
Grade: Ind2, E3

FM24C16/CL16
16Kb; 3.3, 5.0 V
1 MHz I2C;
Grade: Ind2, A4

FM25040/L04
4Kb; 3.3, 5.0 V
20 MHz SPI;
Grade: Ind2, E3

FM24C04/CL04
4Kb; 3.3, 5.0 V
1 MHz I2C;
Grade: Ind2, A4

Wireless Memory
NDA Contact Sales

Concept Development Sampling Production


1

Low-pin-count
2 Industrial grade -40C to +85C
3 AEC-Q100: -40C to +125C

Document No. 001-89435 Rev. *L

4 AEC-Q100:

-40C to +85C
5 Real-time clock

Industrial
Automotive
Availability

QQYY

QQYY

224

Automotive F-RAM Packages


Package

SOIC

DFN

EIAJ

TSOP I

TSOP II

32

44

Family

Pins

LPC

4Kb
16Kb
64Kb
128Kb
256Kb
512Kb
1Mb
2Mb
4Kb
16Kb
64Kb
128Kb
256Kb
512Kb
1Mb
1Mb
2Mb

I2C

Parallel

Document No. 001-89435 Rev. *L

225

Automotive Flash Memory

Document No. 001-89435 Rev. *L

226

Automotive Portfolio: Parallel NOR


S29AS-J
110 nm, 1.8 V

S29AL-J
110 nm, 3.0 V

S29JL-J1
110 nm, 3.0 V

S29PL-J1,2
110 nm, 3.0 V

S29GL-N2
110 nm, 3.0 V

Density (Name)
Initial / Page Access

256Mb

All parts supported by


Longevity Program
unless noted

32Mb

64-128Mb

Automotive Portfolio:
Parallel NOR
(NDA)
16Mb
70 ns / -Grade: A3

16Mb
55 ns / -Grades: A3 and M4

8Mb
70 ns / -Grade: A3

8Mb
55 ns / -Grades: A3 and M4

128Mb
60 ns / 20 ns
Grade: A3

2Gb5
110 ns / 20 ns
Grades: A3 and B6

Q416
2Gb5
110 ns / 20 ns
Contact Sales

1Gb
100 ns / 15 ns
Grades: A3 and B6

1Gb
100 ns / 15 ns
Grades: A3, B6 and M4

512Mb
100 ns / 15 ns
Grades: A3 and B6

512Mb
100 ns / 15 ns
Grades: A3, B6 and M4

128Mb
90 ns / 15 ns
Grades: A3 and B6

64Mb
55 ns / -Grade: A3

64Mb
55 ns / 20 ns
Grade: A3

64Mb
90 ns / 25 ns
Grade: A3

32Mb
60 ns / -Grade: A3

32Mb
55 ns / 20 ns
Grade: A3

32Mb
90 ns / 25 ns
Grade: A3

64Mb
70 ns / 15 ns
Grades: A3, B6 and M4

Concept Development Sampling Production

Document No. 001-89435 Rev. *L

S29GL-T2
45 nm, 3.0 V

256Mb
90 ns / 15 ns
Grades: A3 and B6

1 Supports

simultaneous read/write operation


Supports Page mode
3 AEC-Q100: -40C to +85C
4 AEC-Q100: -40C to +125C
5 S70 series (stacked die)
6 AEC-Q100: -40C to +105C

S29GL-S2
65 nm, 3.0 V

Industrial
Automotive
Availability
EOL(Last-Time-Ship)

QQYY

QQYY
QQYY

227

NOR Flash Memory Family Decoder


S 29 G L 128 S

Document No. 001-89435 Rev. *L

Technology:

J = 110 nm Floating Gate


K = 90 nm Floating Gate
L = 65 nm Floating Gate

N = 110 nm MirrorBit
P = 90 nm MirrorBit
S = 65 nm MirrorBit
T = 45 nm MirrorBit

Density:

001 = 1Mb
002 = 2Mb
004 = 4Mb
008 = 8Mb

016 = 16Mb
032 = 32Mb
064 = 64Mb
128 = 128Mb

256 = 256Mb
512 = 512Mb
01G = 1Gb
02G = 2Gb

Voltage:

D = 2.5V

L = 3.0V

S = 1.8V

Family:

A = Standard ADP (Address-Data Parallel)


C = Burst Mode ADP (Address-Data Parallel)
F = Serial
G = Page Mode
J = Simultaneous Read/Write ADP (Address-Data Parallel)
K = HyperBus
P = Page Mode Simultaneous Read/Write ADP (Address-Data Parallel)

Series:

25 = SPI
29 = NOR

Prefix:

26 = HyperFlash
70 = Stacked Die

1 = 63 nm DRAM

04G = 4Gb
0CG = 64Gb
08G = 8Gb
0AG = 16Gb
0BG = 32Gb

27 = HyperRAM
79 = Dual Quad SPI

228

64-128Mb

256Mb

Automotive Portfolio: HyperFlash,


HyperRAM, & Burst Parallel NOR
HyperFlash
S26KS-S1
65 nm 1.8 V

HyperFlash
S26KL-S1
65 nm 3.0 V

HyperRAM
S27KS-12
63 nm 1.8 V

HyperRAM
S27KL-12
63 nm 3.0 V

Density
Initial / Page Access
Temp Range

All parts supported by


Longevity Program
unless noted

1Gb3
96 ns / 166 MHz
Contact Sales

1Gb3
96 ns / 100 MHz
Contact Sales

512Mb
96 ns / 166 MHz
Grades: A5, B6 and M7

512Mb
96 ns / 100 MHz
Grades: A5, B6 and M7

256Mb
96 ns / 166 MHz
Grades: A5, B6 and M7

256Mb
96 ns / 100 MHz
Grades: A5, B6 and M7

256Mb3
36 ns / 166 MHz
Contact Sales

256Mb3
36 ns / 100 MHz
Contact Sales

128Mb
96 ns / 166 MHz
Grades: A5, B6 and M7

128Mb
96 ns / 100 MHz
Grades: A5, B6 and M7

128Mb3
36 ns / 166 MHz
Contact Sales

128Mb3
36 ns / 100 MHz
Contact Sales

32Mb

64Mb
36 ns / 166 MHz
Grades A5 and B6

Q416

64Mb
36 ns / 100 MHz
Grades A5 and B6

S29CD-J3
110 nm, 2.5 V

S29CL-J3
110 nm, 3.0 V

32Mb
54 ns / 75 MHz
Grades: A5, M7 and T8

32Mb
54 ns / 75 MHz
Grades: A5, M7 and T8

16Mb
54 ns / 66 MHz
Grades: A5, M7 and T8

16Mb
54 ns / 66 MHz
Grades: A5, M7 and T8

Q416

Concept Development
1 S26

= HyperFlash
2 S27 = HyperRAM
3 ADP (Address Data Parallel) Burst
4 S70 series (stacked die)

Document No. 001-89435 Rev. *L

5 AEC-Q100:

-40C to +85C
6 AEC-Q100: -40C to +105C
7 AEC-Q100: -40C to +125C
8 AEC-Q100: -40C to +145C

Industrial
Automotive
Availability

Sampling

Production

QQYY

QQYY
QQYY

229

Automotive Portfolio: SPI NOR


S25FL1-K
90 nm, 3.0V
4KB1

S25FL-L
65 nm, 3.0 V
4KB1

S25FL-P
90 nm, 3.0 V
>4KB1

S25FL-S
65 nm, 3.0 V
>4KB1

Density (Name)
SDR / DDR Clock
Temp Range

256Mb

All parts supported by


Longevity Program
unless noted

64-128Mb

Q316
256Mb
133 MHz / 66 MHz
Grades: A4, B5 and M6

64Mb
108 MHz / -Grades: A4 and B5

32Mb

S79FL-S2
65 nm, 3.0 V
>4KB1

S25FS-S
65 nm, 1.8 V
>4KB1

1Gb3
133 MHz / 80 MHz
Grades: A4 and B5

Q316
1Gb
133 MHz / 80 MHz
Grades: A4 and B5

Q316
1Gb3
133 MHz / 80 MHz
Grades: A4, B5 and M6

512Mb
133 MHz / 80 MHz
Grades: A4 , B5 and M6

Q316
512Mb
133 MHz / 80 MHz
Grades: A4 and B5

Q316
512Mb
133 MHz / 80 MHz
Grades: A4, B5 and M6

256Mb
133 MHz / 80 MHz
Grades: A4 , B5 and M6

Q316
256Mb
133 MHz / 80 MHz
Grades: A4 and B5

128Mb7
104 MHz / -Grades: A4 and B5

128Mb8
133 MHz / 80 MHz
Grades: A4, B5 and M6

128Mb
133 MHz / 66 MHz
Grades: A4, B5 and M6

128Mb9
104 MHz / -Grades: A4 and B5

128Mb10
108 MHz
Grades: A4 and B5

64Mb
108 MHz / -Grades: A4, B5 and M6

64Mb
104 MHz / -Grades: A4 and B5

32Mb
108 MHz / -Grades: A4 and B5

Roadmap

256Mb
133 MHz / 80 MHz
Grades: A4 and B5
128Mb
133 MHz / 80 MHz
Grades: A4 and B5

Q316
64Mb
133 MHz / 100 MHz
Grades: A4, B5 and M6

32Mb
104 MHz / -Grades: A4 and B5

16Mb
108 MHz / -Grades: A4 and B5

Logical sector size


S79 series, Dual Quad SPI (stacked die)
3 S70 series (stacked die)
4 AEC-Q100: -40C to +85C
5 AEC-Q100: -40C to +105C
6 AEC-Q100: -40C to +125C
2

Document No. 001-89435 Rev. *L

S25FL129P
S25FL128S
9 S25FL128P
10 S25FL127S
8

Quad SPI
133-MHz SDR / 80-MHz DDR
Dual SPI
108-MHz SDR

Concept Development
Industrial
Automotive
Availability
EOL(Last-Time-Ship)

Sampling

Production

QQYY

QQYY
QQYY

230

NAND and e.MMC Family Decoders


NAND
S 34 M L 08G 2
Technology: 1 = 4x nm

2 = 32 nm

Density:

01G = 1Gb
02G = 2Gb

04G = 4Gb
08G = 8Gb

Voltage:

L = 3.0 V

S = 1.8 V

Family:

M = NAND (Address-Data Multiplexed)

Series:

34 = NAND

Prefix:

Controller:

B1 = e.MMC 4.51

B2 = e.MMC 5.1

Revision:

1 = NAND MLC1 1x nm

2 = NAND MLC1 1y nm

Density:

004 = 4GB
008 = 8GB

064 = 064GB
128 = 128GB

0AG = 16Gb
0BG = 32Gb

e.MMC
S 40 41 016 1 B1

Controller Architecture:

1 Multi-level

016 = 16GB
032 = 32GB
41 = e.MMC

Series:

40 = Managed Memory

Prefix:

cell

Document No. 001-89435 Rev. *L

231

Automotive Portfolio: SLC NAND &


e.MMC
S34ML-11
4x nm, 3.0 V
SLC, ONFI 1.04

S34MS-11
4x nm, 1.8 V
SLC, ONFI 1.04

S34ML-22
32 nm, 3.0 V
SLC, ONFI 1.04

S34MS-22
32 nm, 1.8 V
SLC, ONFI 1.04

S4041-1B1
1x nm, 3.0 V
MLC, e.MMC 4.515

S34SL-22, 3
32 nm, 3.0 V
SLC, ONFI 1.04

S4041-2B2
1y nm, 3.0 V
MLC, e.MMC 5.15

16Gb; x8
40 MBps

8Gb; x8 Q417
40 MBps
Grades: A6 and B7

1G-4Gb

32GB-64GB

All parts supported by


Longevity Program
unless noted

4Gb; x8/16 Q418


40 MBps
Grades: A6 and B7

4Gb; x8
40 MBps
Grade: B7

2Gb; x8/16 Q418


40 MBps
Grades: A6 and B7

2Gb; x8
40 MBps
Grade: B7

1Gb; x8 Q418
40 MBps
Grades: A6 and B7

1Gb; x8
40 MBps
Grade: B7

Q418

Q418

Q418

8Gb; x8
40 MBps
Grades: A6 and B7

8Gb; x8
40 MBps

4Gb; x8
40 MBps
Grades: A6 and B7

4Gb; x8/16
40 MBps

4Gb; x8
40 MBps

2Gb; x8/16
40 MBps
Grades: A6 and B7

2Gb; x8/16
40 MBps

2Gb; x8
40 MBps

1Gb; x8/16
40 MBps
Grades: A6 and B7

1Gb; x8/16
40 MBps
Grade: A

1Gb; x8
40 MBps

64GB; x8
400 MBps
Grade: A6
32GB; x8
400 MBps
Grade: A6

Q117

16GB; x8
400 MBps
Grade: A6

Q117

8GB; x8
400 MBps
Grade: A6

16GB; x8
200 MBps

8GB-16GB

8Gb-16Gb

Density; Bus Width


Interface Bandwidth

8GB; x8
200 MBps

1-bit ECC
4-bit ECC
3 Secure NAND
4 ONFI = Open NAND Flash Interface
5 e.MMC = Embedded Multi Media Card
6 AEC-Q100: -40C to +85C
7 AEC-Q100: -40C to +105C
2

Document No. 001-89435 Rev. *L

Concept Development Sampling Production


Industrial
Automotive
Availability
EOL(Last-Time-Ship)

QQYY

QQYY
QQYY

232

Parallel NOR Flash Memory Packages


Package
Balls/Pins

FBGA

BGA

TSOP

Fortified BGA

48

48

56

64

64

0.8 mm

0.5 mm

0.8 mm

0.8 mm

1.0 mm

48

56

Family

Density

Pitch

AS-J

8Mb

S29AS008J

16Mb

S29AS016J

8Mb

S29AL008J

16Mb

S29AL016J

32Mb

S29JL032J

64Mb

S29JL064J

32Mb

S29PL032J

64Mb

S29PL064J

128Mb

S29PL127J

32Mb

S29GL032N

64Mb

S29GL064N

64Mb

S29GL064S

128Mb

S29GL128S

256Mb

S29GL256S

512Mb

S29GL512S

1Gb

S29GL01GS

2Gb

S70GL02GS

512Mb

S29GL512T

1Gb

S29GL01GT

2Gb

S70GL02GT

AL-J
JL-J
PL-J

GL-N
GL-S

GL-T

Document No. 001-89435 Rev. *L

233

HyperFlash, HyperRAM, & Burst


Parallel NOR Packages
Package

BGA

FBGA

PQFP

80

80

Family

Density

Balls/Pins

25

KS-S

128Mb
256Mb
512Mb
1Gb
128Mb
256Mb
512Mb
1Gb
64Mb
128Mb
256Mb
64Mb
128Mb
256Mb
16Mb
32Mb
16Mb
32Mb

S26KS128S
S26KS256S
S26KS512S
S70KS01GS
S26KL128S
S26KL256S
S26KL512S
S70KL01GS
S26KS0641
S26KS1281
S70KS2561
S26KL0641
S26KL1281
S70KL2561
S29CD016J
S29CD032J
S29CL016J
S29CL032J

KL-S

KS-1

KL-1

CD-J
CL-J

1 Known

KGD1
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales
Contact Sales

Good Die

Document No. 001-89435 Rev. *L

234

SPI NOR Flash Memory Packages


Package
Balls/Pins
Family

Density Body Size

FL1-K

16Mb
32Mb
64Mb
64Mb

S25FL116K
S25FL132K
S25FL164K
S25FL064L

128Mb
256Mb

S25FL128L
S25FL256L

32Mb
64Mb

S25FL032P
S25FL064P

128Mb
128Mb
128Mb
128Mb
256Mb
512Mb
1Gb
256Mb

S25FL128P
S25FL129P
S25FL127S
S25FL128S
S25FL256S
S25FL512S
S70FL01GS
S79FL256S

512Mb

S79FL512S

1Gb
64Mb
128Mb

S79FL01GS
S25FS064S
S25FS128S

256Mb
512Mb
1Gb

S25FS256S
S25FS512S
S70FS01GS

FL-L

FL-P

FL-S

FL-S
Dual
Quad
FS-S

SOIC

USON

16

150 Mil

208 Mil

300 Mil

UD
UD

4 x 3 mm

WSON
4 x 4 mm

Contact Sales Contact Sales


UD

UD
UD

Contact Sales

25

24

8 x 6 mm

8 x 6 mm

UD
UD

UD
UD

Contact Sales

6 x 5 mm 8 x 6 mm

UD
UD

UD

UD

Contact Sales

UD

LGA (UD)
Contact
Sales

KGD1

BGA

Contact Sales
Contact Sales
Contact Sales

UD

1 Known
2 UD

Good Die
= Under Development

Document No. 001-89435 Rev. *L

235

SLC NAND and e.MMC Packages


Package

BGA

BGA

LBGA

TSOP

153

100

48

Family

Density

Balls/Pins

63

ML-1

1Gb
2Gb
4Gb
8Gb
1Gb
2Gb
4Gb
8Gb
16Gb
1Gb
2Gb
4Gb
1Gb
2Gb
4Gb
8Gb
8GB
16GB
8GB
16GB
32GB
64GB

S34ML01G1
S34ML02G1
S34ML04G1
S34ML08G1
S34ML01G2
S34ML02G2
S34ML04G2
S34ML08G2
S34ML16G2
S34MS01G1
S34MS02G1
S34MS04G1
S34MS01G2
S34MS02G2
S34MS04G2
S34MS08G2
S40410081B1
S40410161B1
S40410082B2
S40410162B2
S40410322B2
S40410642B2

ML-2

MS-1

MS-2

41-1B1
41-2B2

Document No. 001-89435 Rev. *L

236

Automotive USB

Document No. 001-89435 Rev. *L

237

Automotive Portfolio: USB


Device

USB 1.1

USB 2.0

USB 3.0

FX3: CYUSB301x
32-Bit Bus to USB 3.0
ARM9, 512KB RAM
FX3PD
USB 3.1 Gen 2 Type-C
Peripheral Controller with PD
NDA Contact Sales

Hub
HX3: CYUSB33xx
4 Ports, Shared Link1
BC 1.22, Ghost Charge3
Grade A4
HX3C
USB 3.1 Gen 1 Type-C
Hub with PD
NDA Contact Sales
HX3PD
USB 3.1 Gen 2 Type-C
Hub with PD
NDA Contact Sales

FX2LP: CY7C6801x/53
16-Bit Bus to USB 2.0
8051, 16KB RAM

HX2VL: CY7C656x4
4 Ports
4 Transaction Translators

TX2UL: CY7C68003
ULPI10 PHY
13, 19.2, 24, 26 MHz

HX2LP: CY7C656x1
4 Ports
1 Transaction Translator

Bridge

Host

Storage

Type-C

CX3: CYUSB306x
CSI-25 to USB 3.0
4 CSI-25 Lanes, 1 Gbps/Lane

FX3S: CYUSB303x
16-Bit Bus to USB 3.0
RAID6, Dual SDXC7/eMMC8
Grade A4

DX3
USB 3.0 to DSI9 TX
NDA Contact Sales

SD3: CYUSB302x
SDXC7/eMMC8 to USB 3.0
RAID6

CCG1: CYPD1xxx
USB Type-C Port Controller
2 PD Ports, 5 Profiles, 100 W
Grade A4
CCG2: CYPD2xxx
USB Type-C Cable Controller
1 PD Port, Termination, ESD
Grade A4
CCG3: CYPD3xxx
USB Type-C Port Controller
Grade A4

GX3: CYUSB361x
USB 3.0 to Gigabit Ethernet

Bay: CYWB016xBB
HS USB OTG
Dual SDXC7/eMMC8

GX2
USB 2.0 to 10/100 Ethernet
Contact Sales

CYUSB201x
FX2G2
32-Bit Bus to USB 2.0
ARM9 512KB RAM
USB-Serial: CY7C6521x
UART/SPI/I2C to USB
2 Channels, CapSense

SL811HS
FS USB Host/Device
256Byte RAM

enCoRe III: CY7C64215


M8C MCU, 50 GPIOs, ADC
I2C/SPI, 16KB Flash

USB-to-UART (Gen 2):


CY7C65213
3 Mbps, 8 GPIOs

EZ-Host: CY7C67300
4 Ports, FS USB OTG
32 GPIOs
Grade: A4

enCoRe V: CY7C643xx
M8C MCU, 36 GPIOs, ADC
I2C/SPI, 32KB Flash

USB-to-UART (Gen 1):


CY7C64225
230 Kbps

EZ-OTG: CY7C67200
2 Ports, FS USB OTG
25 GPIOs

USB 2.0 and USB 3.0


traffic on the same port
2 Battery Charging specification v1.2
3 Enables USB charging without host connection

Document No. 001-89435 Rev. *L

CCG4
USB Type-C Port Controller
NDA Contact Sales

NX2LP: CY7C6803x
NAND Flash to USB 2.0
8051, 15KB RAM

CCG5
USB Type-C AFE
NDA Contact Sales

AT2LP: CY7C683xx
Parallel ATA to USB 2.0
8051

enCoRe II: CY7C638xx


M8C MCU, 20 GPIOs
SPI, 8KB Flash

1 Simultaneous

Arroyo, Astoria:
CYWB022xABS
16-Bit Bus to USB 2.0
8051, Dual SD/eMMC7

AEC-Q100: 40C to +85C


Serial Interface v2.0
6 Redundant array of independent disks
7 SD extended capacity
4

5 Camera

Embedded MultiMedia Card


Display Serial Interface
10 UTMI low-pin interface

Type-C product
applies to any
USB speed

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

238

Automotive HX3: USB 3.1 Gen 1 Hub


Applications

Block Diagram
Upstream Port

Automotive infotainment

EEPROM
2

4
HX3 Hub
SS3 PHY

USB 2.0 PHY

MCU

USB 3.1 Gen 1 PHY

I2C

32

16

32

Features
USB 3.1 Gen 1-compliant four-port Hub Controller
USB-IF certified (Test ID: 330000047)
WHQL certified for Windows 7, Window 8, Windows 8.1
Shared Link: Supports simultaneous USB 2.0 and
USB SuperSpeed (SS) Devices on the same port
Ghost Charge: Enables USB charging while the Hub is
disconnected from a USB Host
Charging Standard support:
USB-IF Battery Charging v1.2
Apple Charging Standard
Charging an OTG Host in an ACA-Dock
Programming of external EEPROM via USB
Configurable USB SS & USB 2.0 PHY. Drives 11 trace
100-BGA (6 x 6 x 1.0 mm)

SuperSpeed Hub
Controller

Buffers

Transaction translator

Document No. 001-89435 Rev. *L

4x TT1

Repeater

16

32
Routing Logic

Routing Logic
32
16

USB 3.1 Gen 1 PHY


SS3 PHY

USB 3.1 Gen 1 PHY

USB 2.0 PHY SS3 PHY

USB 3.1 Gen 1 PHY

USB 2.0 PHY SS3 PHY

Downstream Port 2

USB 3.1 Gen 1 PHY

USB 2.0 PHY SS3 PHY

Downstream Port 3

USB 2.0 PHY

Downstream Port 4

Availability

Datasheet:
Application Note:
Kits:
Configuration Utility:
1

16

32

Downstream Port 1

Collateral

USB 2.0 Hub Controller

HX3 Datasheet
HX3 Hardware Design Guide
CY4609, CY4603, CY4613
Blaster Plus2
2

Sampling:
Production:

Q4 2016
Q4 2016

A Cypress GUI-based PC application for setting HX3 configuration parameters

SuperSpeed

239

Automotive CCG2:
USB Type-C and PD Port Controller
Applications

Block Diagram

USB Type-C EMCA, powered accessories, UFP, DFP, DRP

CCG2: USB Type-C Port Controller With PD


MCU Subsystem

Features

CC7

Collateral

Flash
(32KB)

SRAM
(4KB)

VCONN1

SCB1
SPI, UART)

VCONN2

SCB1
(I2C, SPI, UART)

Programmable I/O Matrix

48 MHz

Advanced High-Performance Bus (AHB)

CORTEX-M0

(I2C,

Profiles and
Configurations
Baseband MAC
Baseband PHY

VDDIO
GPIO5
Port

Integrated RP2, RD3,


RA4

Serial Wire Debug

Availability
CCG2 Datasheet
CCG2 RDK

communication block configurable as UART, SPI or I2C


Termination resistor read as a DFP

Production: Industrial (Now)

1 Serial

4 Termination

Document No. 001-89435 Rev. *L

I/O Subsystem

TCPWM6

32-bit MCU Subsystem


48-MHz ARM Cortex -M0 CPU with 32KB flash and 4KB SRAM
Integrated Digital Blocks
Integrated timers, counters and pulse-width modulators
Two SCBs1 configurable to I2C, SPI or UART modes
Type-C Support
Integrated transceiver, supporting one Type-C port
Integrated DFP (RP2), UFP (RD3), EMCA (RA4) termination resistors
Power Delivery (PD) Support
Standard power profiles
Low-Power Operation
Two independent VCONN rails with integrated isolation
Independent supply voltage pin for GPIO5
2.7-V to 5.5-V operation
Sleep: 2.0 mA; Deep Sleep: 2.5 A
System-Level ESD on CC6 and VDD Pins
8-kV contact, 15-kV Air Gap IEC61000-4-2 level 4C
Package
24-pin 4mm x 4mm QFN with 0.55-mm pin pitch

Datasheet:
Reference Design Kit:

Integrated Digital Blocks

Termination resistor read as a UFP


resistor read as an EMCA

5 General-purpose
6

input/output
Timer, counter, pulse-width modulation block

7 Configuration

Channel

240

Automotive CCG3: USB Type-C and PD Port


Controller
Applications

Block Diagram

Accessories and power adapters

CCG3: USB Type-C Cable Controller

Collateral
Datasheet:

Cortex-M0
48 MHz

Flash
(64KB)

Flash
(64KB)

4x TCPWM9
4x SCB4
(I2C, SPI, UART)
Crypto Engine

I/O Subsystem

Programmable
I/O Matrix

Type-C Support
Integrated transceiver, supporting one Type-C port
Alternate Modes1, Crypto Engine2 for USB Authentication3
Power Delivery (PD) Support for Standard Power Profiles
Integrated Digital Blocks for VBUS Power and MUX Interface
Four timers, counters and pulse-width modulators, 24x GPIOs
Four SCBs4 for configurable master/slave I2C, SPI or UART
USB Billboard Controller5 with Billboard Device Class6 support
Integrated Analog Blocks for OVP, OCP7
20-V OVP7 and OCP8; 4:2 cross-bar switch
32-bit ARM Cortex-M0 CPU with MCU Subsystem
2x64KB flash for fail-safe updates over CC, I2C or USB interfaces
Low-Power Operation
2x VBUS Gate Drivers8, for consumer and provider power paths
2x high-voltage (5-20 V, 25 V Max) VBUS voltage inputs
Sleep: 2.0 mA; deep sleep: 2.5 A with wake-on-I2C or wake-on-CC
System-Level ESD on CC/VCONN, VBUS, and SBU Pins
8-kV contact, 15-kV Air Gap IEC61000-4-2 level 4C
Package
40-pin QFN

Integrated Digital Blocks

Advanced High-Performance Bus (AHB)

MCU Subsystem

Features

CC

24x GPIO
Ports

USB PD Subsystem
Baseband MAC

Baseband PHY

20-V Regulator

2x VCONN FETs

Overcurrent
Protection

2x 20V VBUS FET


Gate Drivers8

System Resources

Overvoltage
Protection

Integrated Resistors
(RP, RD, RA)10

Full-Speed USB
Billboard Controller

4:2 Analog
Cross-Bar Switch

8-bit SAR ADC

SRAM
(8KB)

Availability
CCG3 Datasheet

Production: Industrial (Now)

Mode of operation in which the data lines are repurposed to transmit non-USB data
The encryption hardware and software required to implement USB Authentication
3 A USB-IF specification that defines the authentication protocol for Type-C accessories
4 Serial communication block configurable as UART, SPI or I 2C
5 A USB Device controller that informs the USB Host of the supported Alternate Modes

Document No. 001-89435 Rev. *L

A specification that defines the method for a USB Device to communicate the supported Alternate Modes
Overvoltage protection, overcurrent protection
8 Circuits to control the gates of external power Field-Effect Transistors (FETs) on V
BUS (5-20 V)
9 Timer/counter/pulse-width modulator block
10 Termination resistors: R read as a DFP, R as a UFP, R as an EMCA
P
D
P

241

Automotive USB Packages


Package
Pins
Body Size
Functionality

Family

Pitch

Hub

HX3

CYUSB33XX

Host

EZ-Host

CY7C67300

Storage

FX3S

CYUSB303X

Type-C

CCG2

CYPD2XX

Type-C

CCG3

CYPD3XX

Document No. 001-89435 Rev. *L

TQFP

BGA

QFN

100

100

121

24

40

14 x 14 mm

6 x 6 mm

10 x 10 mm

4 x 4 mm

6 x 6 mm

0.5 mm

0.5 mm

0.8 mm

0.5 mm

0.5 mm

242

Automotive Timing Solutions

Document No. 001-89435 Rev. *L

243

Automotive Portfolio: Timing Solutions


Clock Generators
EMI Reduction
Q416
CY274x
Max. Frequency: 700 MHz
7 Outputs; PCIe 3.0; 4 PLL
0.7-ps RMS Jitter1; Ind2; Auto A3

Standard
Performance

High
Performance

NEW

CY276x
Max. Frequency: 700 MHz
4-8 Outputs; PCIe 3.0, 10GbE; 2 PLL
0.7-ps RMS Jitter1; Ind2; Auto A3

Clock Buffers

Non-EMI Reduction

PLL ICs

Zero/Non-Zero Delay Buffer

CY294x/ CY5107
Max. Frequency: 2.1 GHz
1 Output; 40/100 GbE; 1 PLL
0.15-ps RMS Jitter1; Ind2

MB15F63UL
Max. Input Frequency: 2 GHz
Sigma-Delta and Integer PLL;
-88.5 dBc/Hz CNR4; Ind2;
CY2DLx/DMx/DPx/CPx
Max. Frequency: 1.5 GHz
2-10 Outputs; LVDS, LVPECL, CML
0.05-ps RMS Jitter1; Ind2

CY314X/CY344X
Max. Frequency: 2.1 GHz
12 Outputs; 1-4 PLL; Hitless Switching5
0.15-ps RMS Jitter1; Ind2
CY2Xx (FleXO)
Max. Frequency: 690 MHz
1 Output; Frequency Margining
0.6-ps RMS Jitter1; Ind2

CY254x/CY251x
Max. Frequency: 166 MHz
3-9 Outputs; 1-4 PLL; I2C
100-ps CCJ4; Ind2

CY2239x/CY229x/CY2238x
Max. Frequency: 200 MHz
3-6 Outputs; 3-4 PLL; I2C
400-ps CCJ6; Ind2; Auto E7

MB15E07SL/05SL/03SL
Max. Input Frequency: 2.5GHz
1 PLL; < 4mA PSC8 ; Ind2;

CY230x/EP0x
Max. Frequency: 220 MHz
5-9 Outputs; LVCMOS
22-ps CCJ6; Ind2; Auto A3

CY22800/801/2429x
Max. Frequency: 200 MHz
2-4 Outputs; 1 PLL; PCIe 1.1
250-ps CCJ6; Ind2, Auto A3

CY22050/150
Max. Frequency: 200 MHz
3-6 Outputs; 1 PLL
250-ps CCJ6; Ind2

MB15E07SR/06SR/05SR
Max. Input Frequency: 3GHz
1 PLL; -86 dBc/Hz CNR4 ; Ind2

CY230xNZ
Max. Frequency: 133 MHz
4-18 Outputs; LVCMOS
250-ps CCJ6; Ind2

MB88151Ax/2Ax/3Ax/4Ax
Max. Frequency: 134 MHz
1 Output; 1 PLL;
< 200-ps CCJ6; Ind2;

MB15F78UL/73UL/72UL
Max. Input Frequency: 2.6 GHz
2 PLL; < 2.8 mA PSC8; Ind2;

CY23S02/05/08/09/FP12
Max. Frequency: 200 MHz
2-12 Outputs; Spread Aware
200-ps CCJ6; Ind2

MB88155x
Max. Frequency: 80 MHz
1 Output; 1 PLL;
< 200-ps CCJ6; Ind2;

MB15F07SL
Max. Input Frequency: 1.1 GHz
2 PLL; < 5 mA PSC8; Ind2;

CY7B99x (RoboClock)
Max. Frequency: 200 MHz
8-18 Outputs; Configurable Skew
50-ps CCJ6; Ind2

2 Industrial

6 Cycle-to-cycle

Integrated phase noise across 12-kHz to 20-MHz offset


grade: -40C to +85C
3 AEC-Q100: -40C to +85C
4 Carrier-to-noise ratio

Document No. 001-89435 Rev. *L

Automatic clock switching on failure of a clock source


jitter
7 AEC-Q100: -40C to +125C
8 Power supply current

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

244

High Performance 4-PLL Clock Generator


(CY274x)
Applications

Block Diagram

Infotainment systems
High-Performance 4-PLL Clock Generator
PLL 1 Block

Divider

Out1

Divider
PLL

Out2
Divider

Divider

Features

Out3P

XIN1

High frequency: 700-MHz differential, 250-MHz single-ended


Pin select and I2C programming
Seven outputs:
Three configurable as differential or single-ended
Four single-ended
Reference clock support for PCIe 3.0, SATA 2.0 and 10 GbE
RMS phase jitter <0.7 ps
Additional features:
Configurable as zero or non-zero delay buffer
Glitch-free frequency switching
Frequency select
Early/late clocks
PLL cascading
Voltage-controlled frequency synthesis

XOUT2
IN1P3

Input
Block

Out4P
PLL 2 Block
Out4N

IN1N3

Out5P
SCLK4
SDAT4
VIN5
FS16

Memory
and
Control
Logic

PLL 3 Block

Out5N
Output
Bank 2

Out6P

FS06

Out6N
PLL 4 Block
Out7

Collateral
Preliminary Datasheet:

Output
Bank 1

Availability
Contact Sales

Contact Sales
1

4 Serial

5 Voltage

Crystal input
Crystal output
3 Reference clock inputs

Document No. 001-89435 Rev. *L

port
input pin for VCFS
6 Frequency select inputs

245

Automotive Timing Solutions Packages


SOIC

TSSOP

QFN

16

48

Body Size

150 Mil

4.4 x 5.0 mm

7 x 7 mm

Functionality

Pitch

0.05 in

0.65 mm

0.5 mm

Clock Buffer

CY2305

Clock Generators

CY22393

CY24293

Package
Pins

CY274X

Document No. 001-89435 Rev. *L

246

Automotive PMIC

Document No. 001-89435 Rev. *L

247

Automotive PMIC1 Family Portfolio


ADAS2

High-End

Instrument Cluster

Mid-Range

NEW

NEW

CYxxx1
Boost+Buck Cnv3
12 V Vbat4, 4 A Output
20-pin TSSOP

NEW

Low-End

Body Control Module

S6BP203A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 3.3 V/2.4 A Output
16-pin TSSOP

CYxxx2
Multi-SMPS5
12 V Vbat4
High Output Current

NEW

Q316
S6BP502A
3xSMPS5
SSCG7, PG6
12 V Vbat4, 2.0 A Output
32-pin Side-Wettable8 QFN

NEW

S6BP201A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 5 V/1 A Output
16-pin TSSOP

CYxxx3
Multi-SMPS5 and LDO
3.0-5.5 V input

NEW

NEW

S6BP401A
4xSMPS5, 2xLDO
WDT9, PG6
5 V Input, 3.0 A Output
40-pin QFN

S6BP203A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 3.3 V/2.4 A Output
16-pin TSSOP

S6BP202A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 5 V/2.4 A Output
16-pin TSSOP

Q316
S6BP502A
3xSMPS5
SSCG7, PG6
12 V Vbat4, 2.0 A Output
32-pin Side-Wettable8 QFN

NEW

NEW

S6BP201A
1xBuck-boost Cnv34, PG6
12 V Vbat4, 5 V/1 A Output
16-pin TSSOP

Q316
S6BP501A
3xSMPS5
SSCG7, PG6
12 V Vbat4, 1.4 A Output
32-pin Side-Wettable8 QFN

NEW

S6BP202A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 5 V/2.4 A Output
16-pin TSSOP

NEW

CYxxx1
Boost+Buck Cnv3
12 V Vbat4, 4 A Output
20-pin TSSOP

S6BP202A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 5 V/2.4 A Output
16-pin TSSOP

NEW

Q316
S6BP501A
3xSMPS5
SSCG7, PG6
12 V Vbat4, 1.4 A Output
32-pin Side-Wettable8 QFN

NEW

NEW

S6BP401A
4xSMPS5, 2xLDO
WDT9, PG6
5 V Input, 3.0 A Output
40-pin QFN

S6BP201A
1xBuck-boost Cnv3, PG6
12 V Vbat4, 5 V/1 A Output
16-pin TSSOP

NEW

S6BP201A
1xBuck-boost Cnv34, PG6
12 V Vbat4, 5 V/1 A Output
16-pin TSSOP

Market Segment
1 Power

Management IC: An IC that converts extremely fluctuating automobile power to safe,


stable power for ECUs
2 Advanced Driver Assistance Systems
3 Converter: A general-purpose regulator IC that integrates power MOSFETs
4 Battery voltage
5 Switch-Mode Power Supply: A general-purpose regulator IC that uses a switching circuit to
up-convert and/or down-convert a voltage source to a different voltage for powering other ICs

Power Good: An output signal that PMICs provide to signify that the supplied power by PMICs is
proper and ready
7 Spread Spectrum Clock Generator
8 A package whose flanks are processed to improve soldering adherence and to simplify the
optical inspection, which follows soldering
9 Watchdog timer
Concept Development Sampling Production
Industrial
Automotive
Availability

Document No. 001-89435 Rev. *L

QQYY

QQYY

248

One-Channel Automotive PMIC1


Automotive PMIC1 Family | S6BP20x
Applications

Family Table

General-purpose automotive: Instrument cluster, body control,


ADAS2

Output Voltage
5.0-5.2 V

Features
1-Channel PMIC: Synchronous buck-boost converter
Wide Input Voltage Range: 2.5-42 V
Low Quiescent Current: 20 A
Programmable Switching Frequency: 0.2-2.1 MHz
Synchronization with external clock from 200 kHz to 400 kHz
Autonomous PFM/PWM3 switching
BOM Integration: Built-in switching transistors
System Safety Function Support:
Undervoltage protection (UVP), overvoltage protection (OVP)
Undervoltage locked-out (UVLO), thermal shutdown (TSD)
Overcurrent protection (OCP)
Voltage supervisor with independent PG4 pins
Operating Temperature Range: -40C to +125C
Package: 16-pin Thermally Enhanced TSSOP
Qualification: AEC-Q1005 Grade-1

1.0 A

S6BP202A

3.3 V

2.4 A

S6BP203A

Document No. 001-89435 Rev. *L

UVP/OVP Threshold
6

4.5%

4.5%, 8.0%
8.0%

Block Diagram
Battery

2.5-42 V

Enable
5.0 V

S6BP20xA

5.0-V LDO,
Enable
Buck-Boost
DC/DC
Converter
2.1 MHz

PFM/PWM3 Switch
External Clock for
Synchronization

5.0 V or 3.3 V

Oscillator,
External
Sync

Frequency
Setting

S6BP201A S6BP202A S6BP203A


S6BP201A S6BP202A S6BP203A
Easy DesignSim Software

Management IC: An IC that converts extremely fluctuating automobile power to safe,


stable power for ECUs
2 Advanced Driver Assistance Systems
3 PFM: Pulse-Frequency modulation, PWM: Pulse-Width modulation
4 Power Good: An output signal that PMICs provide to signify that the supplied power by
PMICs is proper and ready

S6BP201A

2.4 A

Protection
Function

1 Power

MPN

5.0-5.2 V

Collateral
Datasheet:
Evaluation Kit:
Software:

Max. Output Current

Power Good4
Function

Power Good4

GND

Availability
Samples: Now

Production: Now

5A

quality standard defined by the Automotive Electronics Council used to verify the reliability of
ICs and qualify them for automotive applications
6 S6BP201A and S6BP202A have factory-selectable options of output voltage, power-on-reset
time, UVP/OVP threshold, and SYNC Function

249

Three-Channel Instrument Cluster Automotive


PMIC1
Automotive PMIC1 Family | S6BP50x
Applications

Family Table

Low-end to mid-range hybrid automotive cluster system

Buck Converter
Output Specification

Features
3-Channels:
Buck controller, boost converter, buck converter
Wide Range Input: 2.5-42 V
Low Quiescent Current: 15 A
High Switching Frequency:
Boost converter and buck converter: 2.1 MHz
Built-in SSCG2
Synchronization with external clock from 1.8 to 2.4 MHz
System Safety Function Support:
Undervoltage protection (UVP), overvoltage protection (OVP)
Undervoltage lock-out (UVLO), thermal shutdown (TSD)
Overcurrent protection (OCP)
Voltage supervisor with independent PG3 pins
Temperature supervisor with thermal warning feature
Operating Temperature Range: -40C to +105C
Package: 32-pin Thermally Enhanced Side-Wettable4 QFN
Qualification: AEC-Q1005 Grade-2

MPN

Buck Controller
Output Specification

Boost Converter
Output Specification

1.15 V6, 1.4 A

S6BP501A

3.3 V6, 1.6 A

5.0 V6, 1.3 A

1.2 V6, 2.0 A

S6BP502A

3.3 V6, 1.9 A

5.0 V6, 1.3 A

Block Diagram
2.5-42 V

S6BP50x
Battery

Power
Sources

Enable SSCG2

External Clock for


Synchronization
Enable

GND

An IC that converts extremely fluctuating automobile power to safe, stable power for ECUs
Spread Spectrum Clock Generator
3 Power Good: An output signal that PMICs provide to signify that the supplied power by PMICs
is proper and ready
4 A package whose flanks are processed to improve soldering adherence and to simplify the
optical inspection, which follows soldering
2

Document No. 001-89435 Rev. *L

5.0 V6

Boost
Converter
2.1 MHz

Collateral
Preliminary Datasheet: S6BP501A S6BP502A
Evaluation Kit:
User Guide

Buck
Controller
0.42 MHz

3.3 V6
SSCG2,
External
Sync
Enable,
LDO

Protection
Function

Bypass Switch
Buck
Converter
2.1 MHz

Power Good3
and Thermal
Warning

1.2 V6 or 1.15 V6

Thermal
Warning
Power
Good3

Availability
Samples: Now

Production: August 2016

A quality standard defined by the Automotive Electronics Council used to verify the reliability of
ICs and qualify them for automotive applications
6 Output voltages are finely adjustable with external resistive dividers

250

Six-Channel ADAS Automotive PMIC1


Automotive PMIC1 Family | S6BP401A
Applications

Block Diagram
2.5-42 V

Automotive Advanced Driver Assistance Systems (ADAS)


Security camera systems

S6BP202A
Automotive PMIC1

Battery

5.0 V

Features
6-Channel PMIC: 4-channel buck converters, 2-channel LDOs
Input Voltage Range: 4.5-5.5 V
High Switching Frequency: 2.1 MHz
Synchronization with external clock from 1.8 to 2.4 MHz
BOM Integration:
Built-in switching transistors and LDO output transistors
Built-in voltage setting resistors and compensation circuitry
Built-in discharge resistors
System Safety Function Support:
Built-in windowed watchdog timer (WDT)
Voltage supervisor with independent PG2 pins
Independent enable pins
Overcurrent protection (OCP), overvoltage protection (OVP)
Undervoltage locked-out (UVLO), thermal shutdown (TSD)
Operating Temperature Range: -40C to +125C
Package: 40-pin Thermally Enhanced QFN
Qualification: AEC-Q1003 Grade-1

S6BP401A
Enable for 6
6-Channel
1.8 V

External Clock for


Synchronization

Trigger
Input
Reset
Output
(Combined with
Power Good2
for LDO1)

GND

1.8V LDO,
Enable

Oscillator,
External
Sync

Windowed
Watchdog
Timer

Power Sources
Buck Converter
2.1 MHz (DC/DC 1)

1.200-1.575 V4
2.0 A
(MCU Core)

Buck Converter
2.1 MHz (DC/DC 2)

1.000-1.275 V4
3.0 A
(ISP Core)

Buck Converter
2.1 MHz (DC/DC 3)

1.200-2.575 V4
2.0 A
(DDR)

Buck Converter
2.1 MHz (DC/DC 4)

3.300-3.400 V4
1.0 A
(Flash Memory)
3.300-3.400 V4
0.2 A
(MCU I/O)

LDO 1

1.200-2.875 V4
0.5 A
(Camera Module)

LDO 2

Protection
Function

Power Good2

Power Good2
for 5-Channel
(Except LDO1)

Collateral
Datasheet:
S6BP401A
Evaluation Kit: User Guide

Availability
Samples: Now

Production: Now

1 An

IC that converts extremely fluctuating automobile power to safe, stable power for ECUs 3 A quality standard defined by the Automotive Electronics Council used to verify the
Good: An output signal that PMICs provide to signify that the supplied power by
reliability of ICs and qualify them for automotive applications
4 S6BP401A has factory-selectable options of output voltage for each channel
PMICs is proper and ready

2 Power

Document No. 001-89435 Rev. *L

251

Automotive LED Driver

Document No. 001-89435 Rev. *L

252

Automotive LED Driver Portfolio


Fog Light
Clearance Light

Daytime Running
Light

Turn Light

Head Light

Matrix Control1

Q416

CYxxx1
Asynchronous Boost2
1 ch3, 1.0 A4, 2.1 MHz5,
SSCG6,
60 V7, 24-Pin HTSSOP

CYxxx1
Asynchronous Boost2
1 ch3, 1.0 A4, 2.1 MHz5,
SSCG6,
60 V7, 24-Pin HTSSOP

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

CYxxx2_HG
Switch2,
8 ch3, 0.5 A4,1 kHz5,
60 V7, 24-Pin HTSSOP

CYxxx2_SG
Switch2,
4 ch3, 1.0 A4,1 kHz5,
60 V7, 20-Pin HTSSOP

CYxxx2_HG
Switch2,
8 ch3, 0.5 A4,1 kHz5,
60 V7, 24-Pin HTSSOP

Mid-Range
Simple Lighting

Q416

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

Q416

S6BL112A
Synchronous Buck2
1 ch3, 2.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

S6BL112A
Synchronous Buck2
1 ch3, 2.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Q416

S6BL111A
Asynchronous Buck2,
1 ch3, 1.0 A4, 2.1 MHz5,
42 V7, 16-Pin HTSSOP

Market Segment

A new front lighting technology that controls individual LEDs


Main topology
3 Output channel
4 Maximum output current

Document No. 001-89435 Rev. *L

Maximum switching frequency


Spread spectrum clock generator
7 Maximum Input and output voltage

Concept Development Sampling Production


Industrial
Automotive
Availability

QQYY

QQYY

253

One-Channel Automotive LED Driver


S6BL111A
Applications

Family Table

Daytime running lights, clearance lights, fog lights, turn lights


and headlights

Maximum Output Current

MPN

FET ON Resistor

Method

1.0 A

S6BL111A

Hi-Side: 480 m

Asynchronous Buck

2.0 A

S6BL112A

Hi-Side: 200 m
Lo-Side: 150 m

Synchronous Buck

Features
Asynchronous rectification buck LED driver
High efficiency: >90 %
Wide input voltage range: 4.5-42 V
Maximum output current: 1 A
High accuracy output current: 2.0 %
Adjustable switching frequency: 0.205-2.1 MHz
Minimum on time1: 35 ns
System safety functions for system protection
Dimming function: Analog2, PWM3
Slew rate control4 for noise reduction
Package: 16-pin thermally enhanced TSSOP (4.4 mm x 5.0 mm)
Qualification: AEC-Q100 Grade-1

Block Diagram
VBAT

VIN

MASK6

S6BL111A
BGR5

4.2-V LDO

MASK6

Oscillator

VCC

RT

PVIN
UVLO7

UVLO7

DIM
SRCNT
BST

Collateral
Preliminary Datasheet:
Automotive LED Driver Evaluation Kit:

S6BL111A
Contact Sales

1A

Document No. 001-89435 Rev. *L

LED
Current
Control

4A

PWM
Control

LX
PGND
CSP

Protection
Function

Production: Q4 2016

spec of switching on time of power MOSFET used in the LED driver


method to control the brightness of an LED using varying DC current
3 A method to control the brightness of an LED using a pulse width
modulated signal generated by a microcontroller
2A

VCC
DIAG

Availability
Sampling: Now

ADJ

function that reduces switching noise by controlling


the rise time (Tr) and fall time (Tf) of the internal switching
power MOSFET
5 Band gap reference

CSN

LED

6 Prevents

a false LED open detection when a drop in


the input voltage causes the output voltage to fall
below the forward voltage of the LED devices
7 Undervoltage lockout

254

One-Channel Automotive LED Driver


S6BL112A
Applications

Family Table

Headlights, daytime running lights, clearance lights, fog lights and


turn lights

Maximum Output Current

MPN

FET ON Resistor

Method

1.0 A

S6BL111A

Hi-Side: 480 m

Asynchronous Buck

S6BL112A

Hi-Side: 200 m
Lo-Side: 150 m

Synchronous Buck

2.0 A

Features
Synchronous rectification buck LED driver
High efficiency: >90 %
Wide input voltage range: 4.5-42 V
Maximum output current: 2 A
High accuracy output current: 2.0 %
Adjustable switching frequency: 0.205-2.1 MHz
Minimum on time1: 35 ns
System safety functions for system protection
Dimming function: Analog2, PWM3
Slew rate control4 for noise reduction
Package: 16-pin thermally enhanced TSSOP (4.4 mm x 5.0 mm)
Qualification: AEC-Q100 Grade-1

Block Diagram

Contact Sales
Contact Sales

Availability

DIAG

Production: Q4 2016

A spec of switching on time of power MOSFET used in the LED driver


A method to control the brightness of an LED using varying DC current
3 A method to control the brightness of an LED using a pulse width
modulated signal generated by a microcontroller
2

Document No. 001-89435 Rev. *L

UCD

BGR6

4.2-V LDO

MASK6

Oscillator

VCC

VCC

RT

PVIN

LED
Current
Control

ADJ

VCC

Preliminary Datasheet:
Automotive LED Driver Evaluation Kit:

S6BL112A

MASK6

Collateral

Sampling: Q2 2016

VIN

VBAT

DIM
SRCNT
BST

UVLO7
Under
Current
Detection
Protection
Function

A function that reduces switching noise by controlling


the rise time (Tr) and fall time (Tf) of the internal switching
power MOSFET
5 Band gap reference

PWM
Control

LX
PGND
CSP
CSN

LED

Prevents a false LED open detection when a drop in


the input voltage causes the output voltage to fall below
the forward voltage of the LED devices
7 Undervoltage lockout

255

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