IJSTE - International Journal of Science Technology & Engineering | Volume 2 | Issue 11 | May 2016

ISSN (online): 2349-784X

Analysis & Design of low Power Dynamic

Latched Double-Tail Comparator
Manish Kumar
Department of Electronics & Communication Engineering
Indus Institute of Engineering and Technology, Kinana, Jind,
Haryana, India - 126102

Kapil Sachdeva
Department of Electronics & Communication Engineering
Indus Institute of Engineering and Technology, Kinana, Jind,
Haryana, India - 126102

Abstract
The need for low power, high speed Analog-To-Digital converters is pushing towards the use of dynamic comparator to maximize
speed &power efficiency. In this paper, we designed a Dynamic Latched Double-Tail Comparator which is used in implementation
of many ADCs. An analysis on the delay of the comparator will presented. Simulation results in 0.18um CMOS technology
confirm the analysis results. The main idea of this Dynamic Latched Comparator is to reduce the static power consumption by
completely cutoff the leakage current to ground. For this purpose, the Power Gating technique is used. The frequency of this
comparator is 1GHz at supply voltage of 1.8V.
Keywords: CMOS technology, MOSFET, Dynamic Latched Comparator
________________________________________________________________________________________________________
I.

INTRODUCTION

Comparator is one of the fundamental building blocks in most analog-to-digital converters (ADCs). Many high speed ADCs, such
as flash ADCs, require high-speed and low-power when the supply voltage is smaller. In other words, in a given technology, to
achieve high speed, larger transistors are required to compensate the reduction of supply voltage, which also means that more die
area and power is needed. Besides, low-voltage operation results in limited common-mode input range, which is important in many
high-speed ADC architectures, such as flash ADC. Many techniques, such as supply boosting methods [2], [3], techniques
employing body-driven transistors [4], [5], current-mode design [6] and those using dual-oxide processes, which can handle higher
supply voltages have been developed to meet the low-voltage design challenges. Boosting and bootstrapping are two techniques
based on augmenting the supply, reference, or clock voltage to address input-range and switching problems. These are effective
techniques, but they introduce reliability issues especially in UDSM CMOS technologies. Body-driven technique adopted by
Blalock [4], removes the threshold voltage requirement such that body-driven MOSFET operates as a depletion-type device. Based
on this approach, in [5], a 1-bit quantizer for sub-1V modulators is proposed. Despite the advantages, the body-driven transistor
suffers from smaller trans-conductance (equal to gmb of the transistor) compared to its gate-driven counterpart while special
fabrication process, such as deep n-well is required to have both NMOS and PMOS transistors operate in the body-driven
configuration [7],[8]. Apart from technological modifications, developing new circuit structures which avoid stacking too many
transistors between the supply rails is preferable for low-voltage operation, especially if they do not increase the circuit complexity.

Fig. 1: Typical block diagram of a high-speed voltage comparator

In this paper, an analysis about the delay of dynamic latched comparator has been presented. Furthermore, based on the doubletail structure proposed in [9], a dynamic comparator is presented, which does not require boosted voltage or stacking of too many
transistors. Merely by adding a few minimum-size transistors to the conventional double-tail dynamic comparator, latch delay time
is profoundly reduced. This also results in considerable power savings when compared to the conventional dynamic comparator
and double-tail comparator. The rest of this paper is organized as follows. Section I investigates the design of the Dynamic Latched
Double-Tail Comparator. Section II describes the operation of this comparator. The results & waveform will be discussing in
section III. The conclusion is described in section IV.

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II. DYNAMIC LATCHED COMPARATOR

Dynamic Latched comparator has found wide applications in many high-speed ADCs since they can make fast decisions due to
the strong positive feedback in the regenerative latch. Recently, many analyses have been presented, which investigate the
performance of these comparator from different aspects, such as noise [11], offset [12], [13], random decision errors [14] and kickback noise [15]. In this section, a delay analysis is presented.

Fig. 2: Schematic diagram of dynamic latched double-tail comparator

Operation of Dynamic Latched Comparator

The operation of the comparator shown in Fig. 2 is as follows. During reset phase (CLK = 0, Mtail1 and Mtail2 are off, avoiding
static power), M3 and M4 pulls both fn and fp nodes to VDD, hence transistor Mc1 and Mc2 are cut off. Intermediate stage
transistors, MR1 and MR2, reset both latch outputs to ground. During decision-making phase (CLK = VDD, Mtail1, and Mtail2
are on), transistors M3 and M4 turn off. Furthermore, at the beginning of this phase, the control transistors are still off (since fn
and fp are about VDD). Thus, fn and fp start to drop with different rates according to the input voltages. Suppose VINP > VINN,
thus fn drops faster than fp, (since M2 provides more current than M1). As long as fn continues falling, the corresponding PMOS
control transistor (Mc1 in this case) starts to turn on, pulling fp node back to the VDD; so another control transistor (Mc2) remains
off, allowing fn to be discharged completely. In the proposed structure as soon as the comparator detects that for instance node fn
discharges faster, a PMOS transistor (Mc1) turns on, pulling the other node fp back to the VDD. Therefore, by the time passing,
the difference between fn and fp (Vfn/fp) increases in an exponential manner, leading to the reduction of latch regeneration time.
Despite the effectiveness of the proposed idea, one of the points which should be considered is that in this circuit, when one of the
control transistors (e.g., Mc1) turns on, a current from VDD is drawn to the ground via input and tail transistor (e.g., Mc1, M1,
and Mtail1), resulting in static power consumption. To overcome this issue, two NMOS switches are used below the input

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Analysis & Design of low Power Dynamic Latched Double-Tail Comparator

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transistors, as shown in Fig. 2. At the beginning of the decision making phase, due to the fact that both fn and fp nodes have been
pre-charged to VDD. Waveforms are shown in Fig. 3.

Fig. 3: Transient simulation of dynamic latched comparator

During the reset phase, both switches are closed and fn and fp start to drop with different discharging rates. As soon as the
comparator detects that one of the fn/fp nodes is discharging faster, control transistors will act in a way to increase their voltage
difference. Suppose that fp is pulling up to the VDD and fn should be discharged completely, hence the switch in the charging path
of fp will be opened (in order to prevent any current drawn from VDD) but the other switch connected to fn will be closed to allow
the complete discharge of fn node. In other words, the operation of the control transistors with the switches emulates the operation
of the latch. In this proposed structure shown in Fig. 4, the power gating technique is used with domino logic. This structure
supports to pull the fp node up to vdd and discharging the fn node completely. This is possible as both the switching transistor will
be opened at the same time. At the same time Msw3 & Msw4 will be closed. In this structure, Power Gating Technique & use of
domino logic style reduces the overall power consumption.
III. RESULTS & WAVEFORM
In order to analyze this dynamic latched comparator, this circuit has been simulated in 180 nm CMOS technology with 1.8V power
supply at 1GHz clock frequency. Tanner EDA tool is leading provider to easy to use. PC electronic design automation (EDA)
software solution for the design, layout and verification of analog-mixed signal integrated circuits. Particular care was taken in the
layout to avoid affecting delay and power of the comparator.
The design of this comparator has been drawn using S-Edit. The results are simulated in T-spice. The waveform is shown through
W-edit which represents in Fig. 5.

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Analysis & Design of low Power Dynamic Latched Double-Tail Comparator

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Fig. 4: Schematics of proposed dynamic latched comparator

Fig. 5: Waveform of proposed dynamic latched comparator

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Table 1
Performance Comparison of proposed comparator with conventional comparator
Parameters
Conventional comparator Proposed double tail comparator
Technology
180nm
180nm
Supply voltage
1.8V
1.8V
Power
48.5uw
18uw
Delay
691ps
350ps

IV. CONCLUSION
In this paper, we presented a delay analysis for dynamic latched comparator. Based on theoretical analyses, dynamic comparator
with low-voltage low-power capability was proposed in order to improve the performance of the comparator. Post-layout
simulation results in 0.18-m CMOS technology confirmed that the delay and power of the proposed comparator is reduced to a
great extent.
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