MICROPROCESSOR

UNIT I

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SYLLABUS
UNIT I INTRODUCTION
Evolution of Microprocessors, Microcontrollers and Computers,
Microprocessor based system design need-steps, Advantages and
limitations organization of a microcomputer, Bus system
Decoders Tri state logic Interrupts Memory devices:
classifications and its interfacing Data Transfer Concepts,
Methods Parallel I/O interfacing Serial I/O interfacing concepts
Use of SID and SOD lines DMA method of transfer.
UNIT II - MICROPROCESSORS
Intel 8085, Z-80, 8086, 80186, Pentium Architecture Functions of
various blocks and signals addressing modes Program execution
Instruction set Assemblers Instruction Timing and status
signals Stack and subroutine, Pipelining concepts Simple
programs.

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Microprocessor and Microcontroller

Microprosessor
Microprocessor is an IC which has only the CPU inside them.
These microprocessors dont have RAM, ROM, and other
peripheral on the chip.
A system designer has to add them externally to make them
functional. Application of microprocessor includes Desktop PCs,
Laptops, notepads etc.
Microcontroller
Microcontrollers are designed to perform specific tasks. Specific
means applications where the relationship of input and output is
defined.
Depending on the input, some processing needs to be done and
output is delivered.
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EVOLUTION OF MICROPROCESSORS
Microprocessors were categorized into five generations:
First
Second
Third
Fourth
Fifth
Their characteristics are described below:

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First-generation
The microprocessors that were introduced in 1971 to 1972
were referred to as the first generation systems.
First-generation microprocessors processed their instructions
seriallythey fetched the instruction, decoded it, then
executed it.
When an instruction was completed, the microprocessor
updated the instruction pointer and fetched the next
instruction, performing this sequential drill for each
instruction in turn.

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Second generation
By the late 1970s, enough transistors were available on the IC to
usher in the second generation of microprocessor sophistication:
16-bit arithmetic and pipelined instruction processing.
Motorolas MC68000 microprocessor, introduced in 1979, is an
example. Another example is Intels 8080.
This generation is defined by overlapped fetch, decode, and
execute steps (Computer 1996). As the first instruction is processed
in the execution unit, the second instruction is decoded and the
third instruction is fetched.
The distinction between the first and second generation devices
was primarily the use of newer semiconductor technology to
fabricate the chips.
This new technology resulted in a five-fold increase in instruction,
execution,
speed,
and
higher
chip
densities.

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Third generation
The third generation, introduced in 1978, was represented by Intels
8086 and the Zilog Z8000, which were 16-bit processors with
minicomputer-like performance.
The third generation came about as IC transistor counts approached
250,000.
Motorolas MC68020, for example, incorporated an on-chip cache
for the first time and the depth of the pipeline increased to five or
more stages.
This generation of microprocessors was different from the previous
ones in that all major workstation manufacturers began developing
their own RISC-based microprocessor architectures (Computer,
1996).

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Fourth generation
As the workstation companies converted from commercial
microprocessors to in-house designs, microprocessors entered their
fourth generation with designs surpassing a million transistors.
Leading-edge microprocessors such as Intels 80960CA and
Motorolas 88100 could issue and retire more than one instruction
per clock cycle.

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Fifth generation
Microprocessors in their fifth generation, employed decoupled
super scalar processing, and their design soon surpassed 10 million
transistors.
In this generation, PCs are a low-margin, high-volume-business
dominated by a single microprocessor.

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Organization of Microcomputer
The basic components of a
microcomputer are:
1) CPU
ALU
Control
Register

2) Program memory
3) Data memory
4) Output ports
5) Input ports
6) Clock generator.

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Central Processing Unit:

The CPU consists of ALU (Arithmetic and Logic Unit), Register unit
and control unit.
The CPU retrieves stored instructions and data word
from memory; it also deposits processed data in memory.

ALU (Arithmetic and Logic Unit)

This section performs computing functions on data.
These functions are arithmetic operations such as additions
subtraction and logical operation such as AND, OR rotate etc.
Result are stored either in registers or in memory or sent to output
devices.

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Register Unit:
It contains various register. The registers are used primarily to store
data temporarily during the execution of a program.
Some of the registers are accessible to the uses through
instructions.

Control Unit:
It provides necessary timing & control signals necessary to all the
operations in the microcomputer.
It controls the flow of data between the processor and peripherals
(input, output & memory).
The control unit gets a clock which determines the speed of the
microprocessor.

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Program Memory:
The basic task of a microcomputer system into ensure that its CPU
executes the desired instruction sequence is the program properly.
The instruction sequence is started in the program memory on
initialization- usually a power up and manual reset the processor
starts by executing the instruction in a predetermined location in
program memory.

Data Memory:
A microcomputer manipulates data according to the algorithm
given by the instruction in the program in the program memory.
These instruction may require intermediate results to be stored, the
functional block in c have same internal registers which can also
be used if available for such storage external data memory is
needed if the storage requirements is more.

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Input / Output Ports:

The input & output ports provide the microcomputer the
capability to communicate with the outside world.
The input ports allow data to pass from the outside world to the
c data which will be used in the data manipulation being done
by the microcomputer to send data to output devices

Clock Generator:

Operations inside the microprocessor, are usually synchronous by

nature.
The clock generator generates the appropriate clock periods
during which instruction executions are carried out by the
microprocessor

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Bus system of Microcomputer

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Address Bus:
The address bus consists of 16, 20, 24, or more parallel signal lines,
through which the CPU sends out the address of the memory
location.
This memory location is used for to written to or read from.
The number of memory location is depends on 2 to the power N
address lines.

Data Bus:
The data bus consists of 8, 16, 32 or more parallel signal lines.
The data bus lines are bidirectional.
This means that the CPU can read data from memory or from a I/O
port as well as send data to a memory location or to a I/O port.

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Control Bus:
The control bus consists of 4-10 parallel signal lines.
The CPU sends out signals on the control bus to enable the outputs
of addressed memory devices or port devices.
Typically control bus signals are memory read, memory write, I/O
read and I/O write.
To read a data from a memory location, the CPU sends out the
address of the desired data on the address bus and then sends out
a memory read signal on the control bus.

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8085 microprocessor

8-bit general purpose

Address 64kB memory
40 pins
+5 V single power supply
3 MHz clock frequency

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PIN DIAGRAM

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8085 microprocessor (Architecture)

Accumulator:-It is a 8-bit register which is used to perform
arithmetical and logical operation. It stores the output of any
operation. It also works as registers for i/o accesses.
Temporary Register:-It is a 8-bit register which is used to hold the
data on which the accumulator is computing operation. It is also
called as operand register because it provides operands to ALU.

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 ALU:-ALU performs the arithmetic operations and logical

operation.
Flag Registers:-It consists of 5 flip flop which changes its status
according to the result stored in an accumulator. It is also
known as status registers. It is connected to the ALU.
There are five flip-flops in the flag register are as follows:
1.Sign(S)
2.zero(z)
3.Auxiliary carry(AC)
4.Parity(P)
5.Carry(C)

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 The bit position of the flip flop in flag register is:

Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As

we know that a number on the D7 always decides the sign of the
number.
if D7 is 1: the number is negative.
if D7 is 0: the number is positive.
Zeros(Z)-If the result stored in an accumulator is zero then this flip
flop is set otherwise it is reset.
Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output
then it is set otherwise it is reset.
Parity(P)-If the no of 1's is even in the output stored in the
accumulator then it is set otherwise it is reset for the odd.
Carry(C)-If the result stored in an accumulator generates a carry in
its final output then it is set otherwise it is reset.
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REGISTER ARRAY
Registers:-These are general purpose registers. Microprocessor
consists 6 general purpose registers of 8-bit each named as B,C,D,E,H
and L.
Generally these registers are not used for storing the data
permanently. It carries the 8-bits data. These are used only during the
execution of the instructions.

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 These registers can also be used to carry the 16 bits data by making
the pair of 2 registers. The valid register pairs available are BC,DE,
HL. We can not use other pairs except BC,DE and HL. These registers
are programmed by user.
Program Counter:-It is a 16 bit register used as memory pointer. It
stores the memory address of the next instruction to be executed.
So we can say that this register is used to sequencing the program.
The program counter is set to 0000H.
Stack Pointer:-It is also a 16 bit register used as memory pointer. It
points to the memory location called stack. Generally stack is a
reserved portion of memory where information can be stores or
taken back together.

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 Instruction registers(IR):-It is a 8-bit register. When an

instruction is fetched from memory then it is stored in this
register.
Instruction Decoder:- Instruction decoder identifies the
instructions. It takes the information from instruction register
and decodes the instruction to be performed (sequence of
events to follow).
Timing and Control Unit:-It provides timing and control signal
to the microprocessor to perform the various operations . It
has four control signals. It controls all external and internal
circuits. It operates with reference to clock signal. It
synchronizes all the data transfers.

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Control Signals: READY, RD, WR, ALE

Status Signals: S0, S1, IO/M
DMA Signals: HOLD, HLDA
RESET Signals: RESET IN, RESET OUT

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 There are four control signal:

1.ALE-Airthmetic Latch Enable
2.RD- This is active low used for reading operation.
3.WR-This is active low used for writing operation.
4. READY- waits for slow responding peripherals
READY= 0 , waits
READY= 1 , normal operation

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ALE

ALE=1, AD0-AD7 are address lines

ALE=0, AD0-AD7 are data lines
This technique is called Address/Data demultiplexing.

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There are three status signal used in microprocessor S0, S1 and

IO/M. It changes its status according the provided input to these
pins.

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 Interrupt Unit -There are 6 interrupt pins in this unit. Generally an

external hardware is connected to these pins. These pins provide
interrupt signal sent by external hardware to microprocessor and
microprocessor sends acknowledgement for receiving the interrupt
signal (INTA )
Interrupt signals present in 8085 are:

INTR
RST 7.5
RST 6.5
RST 5.5
TRAP

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 Of the above four interrupts TRAP is a NON-MASKABLE interrupt

control and other three are maskable interrupts.
A non-maskable interrupt is an interrupt which is given the highest
priority in the order of interrupts. Suppose you want an instruction
to be processed immediately, then you can give the instruction as a
non-maskable interrupt. Further the non-maskable interrupt cannot
be disabled by programmer at any point of time.
Whereas the maskable interrupts can be disabled and enabled
using EI and DI instructions. Among the maskable interrupts RST 7.5
is given the highest priority above RST 6.5,RST 5.5 and least priority
is given to INTR.

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 Serial I/O control

Serial Input Output Control-There are two pins in this unit.
This unit is used for serial data communication.
The input and output of serial data can be carried out using 2
instructions in 8085 (RIM & SIM).
SID-Serial Input Data
SOD-Serial Output Data

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Address buffer and Address-Data buffer

The contents of the stack pointer and program counter are loaded
into the address buffer and address-data buffer.
These buffers are then used to drive the external address bus and
address-data bus.
As the memory and I/O chips are connected to these buses, the
CPU can exchange desired data to the memory and I/O chips.
The address-data buffer is not only connected to the external data
bus but also to the internal data bus which consists of 8-bits. The
address data buffer can both send and receive data from internal
data bus.

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Address bus and Data bus:

We know that 8085 is an 8-bit microprocessor. So the data
bus present in the microprocessor is also 8-bits wide.
So 8-bits of data can be transmitted from or to the
microprocessor. But 8085 processor requires 16 bit address
bus as the memory addresses are 16-bit wide.
The 8 most significant bits of the address are transmitted with
the help of address bus and the 8 least significant bits are
transmitted with the help of multiplexed address/data bus.
The eight bit data bus is multiplexed with the eight least
significant bits of address bus.
The address/data bus is time multiplexed. This means for few
microseconds, the 8 least significant bits of address are
generated, while for next few seconds the same pin generates
the data. This is called Time multiplexing.

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Addressing Modes of 8085

To perform any operation, we have to give the
corresponding instructions to the
microprocessor.
In each instruction, programmer has to
specify 3 things:
Operation to be performed.
Address of source of data.
Address of destination of result.
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 Addressing Modes of 8085

The method by which the address of source of
data or the address of destination of result is
given in the instruction is called Addressing
Modes.
The term addressing mode refers to the way in
which the operand of the instruction is
specified.
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Types of Addressing Modes

Intel 8085 uses the following addressing
modes:
1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

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Direct Addressing Mode

In this mode, the address of the operand is
given in the instruction itself.
LDA 2500 H
Load the contents of memory location
2500 H in accumulator.
LDA is the operation.
2500 H is the address of source.
Accumulator is the destination.
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Register Addressing Mode

In this mode, the operand is in general
purpose register.
MOV A, B
Move the contents of register B to A
MOV is the operation.
B is the source of data.
A is the destination
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Register Indirect Addressing

Mode
In this mode, the address of operand is specified
by a register pair.
MOV A, M
Move data from memory location specified by
H-L pair to accumulator.
MOV is the operation.
M is the memory location specified by
H-L register pair.
A is the destination.
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Immediate Addressing Mode

In this mode, the operand is specified within
the instruction itself.
MVI A, 05 H
Move 05 H in accumulator
MVI is the operation.
05 H is the immediate data (source).
A is the destination.

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Implicit Addressing Mode

If address of source of data as well as address of
destination of result is fixed, then there is no
need to give any operand along with the
instruction.
CMA
Complement accumulator
CMA is the operation.
A is the source.
A is the destination.
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Microprocessor based system design

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Feasibility Study
Provides background for actual system development.
Helps in the selection of particular level of
technology depending on the availability of expertise
to operate and maintain the product.
Analyses various approaches like purchasing a system
and modifying or designing the system.
System Specification
System development is done.
A system is defined in terms of set of entities and the
relation between entities.

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The inputs and outputs are called the environment of

the system.
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Initial Design
It defines the functions that will be carried out by
both hardware and software.
Analysis of the problem should be done to define
performance requirements, hardware and software
routines.
Hardware Design
The matching of electrical characteristics and timing
of ICs is done using a complete microprocessor and
peripheral chips.

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Software Design
This involves the following steps
Environment and problem specification( data format,
data transfer)
State transition diagram
Flowchart
Memory I/O and register organization
Editing and assembling
Test and debug
Testing should be done by simulating the environment in
which the module is to work.
Once the tests are successfully completed, actual
software is tested block by block.

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Integration
Integration of hardware and software is carried out
and the system is simulated under real/simulated
conditions.
Documentation
It helps in the coordinated approach to system
development.
The system specifications, environment, hierarchical
chart, flowchart, state transition diagrams, test
procedures etc. should be included in the
documentation.
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Address Decoder
Logical circuit that identifies each combination of signals present at
input
An address decoder is a binary decoder circuit that has two or more
bits of an address bus as inputs and that has one or more device
selection lines (I/O peripherals or memory) as outputs.
When the address for a particular device appears on the address
bus, the address decoder asserts the selection line for that device.

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Tri-state Logic
Has three logic states: logic 0, logic1 and high impedance
Has three lines: input, output and enable line
When enable is activated, tri-state device acts as a normal
device
When enable is deactivated, the logic device goes to high
impedance state ( i.e, disconnected from the system)
Hence the peripherals do not load the bus system
Used when Microprocessor allow multiple logic devices to be
connected to the same wire or bus without damage or loss of
data
Truth Table

Logically
A

A
enable

enable
0
0
1
1

A
0
1
0
1

Output
(Z)
(Z)
1
0
53
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Interrupts
Interrupt is a mechanism by which an I/O or an instruction can
suspend the normal execution of processor and get itself
serviced.
Generally, a particular task is assigned to that interrupt signal.
In the microprocessor based system the interrupts are used
for data transfer between the peripheral devices and the
microprocessor.
The processor will check the interrupts always at the 2nd Tstate of last machine cycle.

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Interrupt Service Routine(ISR):

A small program or a routine that when executed services the
corresponding interrupting source is called as an ISR.
Classification of interrupts:
Maskable/Non-Maskable Interrupt
An interrupt that can be disabled by writing some instruction
is known as Maskable Interrupt otherwise it is called NonMaskable Interrupt.
Hardware / Software Interrupts
Vectored/ Non vectored Interrupts

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Hardware interrupts:
An external device initiates the hardware interrupts and
placing an appropriate signal at the interrupt pin of the
processor.
If the interrupt is accepted then the processor executes an
interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP
(2) RST 7.5
(3) RST 6.5
(4) RST 5.5
(5) INTR
Software Interrupts:
A software interrupts is a particular instructions that can be
inserted into the desired location in the program.
There are eight Software interrupts in 8085 Microprocessor.
From RST0 to RST7

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Vectored and non vectored interrupts

INTR non vectored interrupt

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8085 Interrupts and Vector Locations

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TRAP:
This interrupt is a non-maskable interrupt. It is unaffected by
any mask or interrupt enable.
TRAP bas the highest priority and vectored interrupt.
TRAP interrupt is edge and level triggered. This means that
the TRAP must go high and remain high until it is
acknowledged.
In sudden power failure, it executes a ISR and send the data
from main memory to backup memory.
The signal, which overrides the TRAP, is HOLD signal. (i.e., If
the processor receives HOLD and TRAP at the same time then
HOLD is recognized first and then TRAP is recognized).
There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal)

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RST 7.5:
The RST 7.5 interrupt is a maskable interrupt.
It has the second highest priority.
It is edge sensitive. ie. Input goes to high and no need to
maintain high state until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.

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RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input
goes to high and stay high until it recognized.
Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
The RST 6.5 has the third priority whereas RST 5.5 has the
fourth priority.

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INTR:
INTR is a maskable interrupt. It is disabled by,
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.
Enabled by EI instruction.
Non- vectored interrupt. After receiving INTA (active low)
signal, it has to supply the address of ISR.
It has lowest priority.
It is a level sensitive interrupts. ie. Input goes to high and it is
necessary to maintain high state until it recognized.
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 The following sequence of events occurs when INTR signal

goes high.
1. The 8085 checks the status of INTR signal during execution of
each instruction.
2. If INTR signal is high, then 8085 complete its current
instruction and sends active low interrupt acknowledge
signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an
instruction OPCODE on the data bus. In the case of multibyte
instruction, additional interrupt acknowledge machine cycles
are generated by the 8085 to transfer the additional bytes
into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next
instruction on stack and execute the received instruction
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SIM

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RIM

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Memory Devices

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Classification of RAM

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Memory Interfacing

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 Consider a system in which the full memory space 64kb is

utilized for EPROM memory. Interface the EPROM with
8085 processor.
The memory capacity is 64 Kbytes. i.e
2^n = 64 x 1000 bytes where n = address lines.
So, n = 16.
In this system the entire 16 address lines of the processor
are connected to address input pins of memory IC in order
to address the internal locations of memory.
The chip select (CS) pin of EPROM is permanently tied to
logic low (i.e., tied to ground).
Since the processor is connected to EPROM, the active low
RD pin is connected to active low output enable pin of
EPROM.
The range of address for EPROM is 0000H to FFFFH.
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 Consider a system in which the available 64kb memory space is

equally divided between EPROM and RAM. Interface the EPROM
and RAM with 8085 processor.
Implement 32kb memory capacity of EPROM using single IC 27256.
32kb RAM capacity is implemented using single IC 62256.
The 32kb memory requires 15 address lines and so the address
lines A0 - A14 of the processor are connected to 15 address pins of
both EPROM and RAM.
The unused address line A15 is used as to chip select. If A15 is 1, it
select RAM and If A15 is 0, it select EPROM.
Inverter is used for selecting the memory.
The memory used is both Ram and EPROM, so the low RD and WR
pins of processor are connected to low WE and OE pins of memory
respectively.
The address range of EPROM will be 0000H to 7FFFH and that of
RAM will be 8000H to FFFFH.
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PROBLEM
Interface two numbers of 4Kb EPROM and one 8Kb RAM with 8085
processor. Draw interface diagram and allocate binary address to
memory ICs

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Data Transfer Concepts

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FORMATS OF DATA TRANSFER

Synchronous
At the same time transmitter and receiver are
synchronized with the same clock.
Used in high speed data transmission.

Asynchronous
Here the transmitter and receiver
synchronized at irregular intervals.
Used in low speed data transmission.

are

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MODES OF DATA TRANSFER

Parallel Mode

Entire word is transferred at one time (4,8 or 16bits depending on the processor)
Eg: Keyboard, seven segment LEDs, data
converters memory

Serial Mode
Data is transferred one bit at a time over a single
line
Before transfer parallel to serial conversion is
done and vice versa at reception
Eg: printers(also used in parallel I/O mode),
modems for telephone lines
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TYPES OF I/O
Peripheral I/O
Peripheral is indentified with 8-bit address
Instructions
IN : transfers from i/p device to accumulator
OUT : transfers from accumulator to o/p device

Memory mapped I/O

Peripheral is connected as memory location
Data is transferred with memory related instructions
STA, LDA,MOV M,R
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CONDITIONS OF DATA TRANSFER

Microprocessor controlled
When peripheral response is slow compared to
microprocessor
Conditions are required for data transfer so that data
is not lost
Microprocessor controlled data transfer is done under
5 conditions

Peripheral controlled
When peripheral is faster than microprocessor
Eg: DMA (Direct memory access)

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TYPES OF MICROPROCESSOR CONTROLLED

DATA TRANSFER
Unconditional data transfer
Microprocessor assumes that a peripheral is always
available
Eg: Display data at LED port
Data transfer with Polling
Microprocessor is kept in a loop to check whether data are
available (Does no work except checking)
Read data from input keyboard, Mp keeps polling till a key
is pressed

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TYPES OF MICROPROCESSOR CONTROLLED

DATA TRANSFER(cont..)
Data transfer with interrupt
When a peripheral is ready to transfer data, it sends an
interrupt signal to the processor.
The processor stops the execution of the program, accepts
the data from the peripheral, then returns to the program.
Free to perform other tasks unlike polling
Data transfer with READY signal
Peripheral response is slower READY signal is used to add
T-states & extend execution time

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TYPES OF MICROPROCESSOR CONTROLLED

DATA TRANSFER(cont..)
Data transfer with handshake signals
Signals are exchanged between the processor and
peripheral prior to actual data transfer; these signals are
called handshake signals.
Handshake signals ensures the readiness of the peripheral
and to synchronize the timing of the data transfer
Eg: A/D converter is used as input device Mp waits for end
of conversion signal. After conversion A/D converter sends
data ready (DR) signal. Mp waits for handshake signal DR
handshake signal prevents reading same data more than
once & writing new data before a data is read
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Serial Input Data

Serial Input data

8085 Microprocessor has two Serial Input/output pins
that are used to read/write one bit data to and from
peripheral devices.
SID (Serial Input Data) line
There is an One bit Input line inside the 8085 CPU (Pin
number 5)
1 bit data can be externally read and stored using this SID
line
The data that is read is stored in the A7th bit of the
Accumulator
RIM instruction is used to read the SID line
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Serial Output Data

SOD (Serial Output Data) Line

There is a One bit Output port inside the 8085 CPU
(Pin number 4)
1 bit data can be externally written in this port.
To write data into this port, SIM instruction is used.
The data that is to be written in this port must be
stored in the A7th bit of the Accumulator.
Bit A6 of the Accumulator is known as SOE (Serial
output Enable). This bit must be set to 1 to enable
Serial data output.
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Serial Output Data

SOD (Serial Output Data) Line

There is a One bit Output port inside the 8085 CPU
(Pin number 4
1 bit data can be externally written in this port.
To write data into this port, SIM instruction is used.
The data that is to be written in this port must be
stored in the A7th bit of the Accumulator.
Bit A6 of the Accumulator is known as SOE (Serial
output Enable). This bit must be set to 1 to enable
Serial data output.
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