International Journal of Electrical and

Electronics Engineering Research (IJEEER)

ISSN(P): 2250-155X; ISSN(E): 2278-943X
Vol. 6, Issue 4, Aug 2016, 43-50
TJPRC Pvt. Ltd

AN ULTRALOW-POWER LOW-NOISE CMOS BIO AMPLIFIER FOR

NEURAL RECORDING APPLICATION
SUBHARAJIT JENA & ANANYA DASTIDAR
Electronics and Communication Engineering, Centre for Advanced Post Graduate Studies, BPUT, Odisha, India
ABSTRACT
This research aims at design strategy for a neural recording amplifier array with ultralow power
low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but
supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feed
forward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection.
For a two-channel amplifier, the measurements show a mid-band gain of 58.7 dB and a pass band from 490 mHz to 10.5
kHz. The amplifier consumes 2.85 A per channel from a 1-V supply and exhibits an input-referred noise of 3.04 V rms
from 0.1 Hzto 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than
50 dB in the pass band. The amplifier is fabricated in a 90-nm CMOS process and occupies0.137 mm2 of chip area.

Rejection Ratio

Received: Jun 13, 2016; Accepted: Jul 04, 2016; Published: Jul 11, 2016; Paper Id.: IJEEERAUG20165

1. INTRODUCTION

Original Article

KEYWORDS: Power Supply Rejection Ratio, Operational Trans Conductance Amplifier, Pseudo Resistor, Common Mode

Education Minimally invasive monitoring of the electrical activity of specific brain areas using implantable
Microsystems offers the promise of diagnosing brain diseases, as well as detecting and identifying neural patterns
which are specific to behavioral phenomenon. Neural pattern classification and recognition require simultaneous
recording from a large number of neurons .However, extensive recording in-vivo demands complying with severe
safety requirements. For example, the maximum temperature increase due to the operation of the cortical implant in
any surrounding brain tissue should be kept at less than 1 C. This requirement constrains the maximum allowable
power dissipation in the implant, which should not exceed 4 to 5 mA drawn from a 1.8-V supply. The limited total
power budget imposes strict specifications on the circuit design of the low-noise analog front-end and high-speed
circuits in the wideband wireless link which transmits the recorded data to a base station located outside the skull.
The design constraints are more pronounced when the number of recording sites increases to several hundred for
typical multielectrode arrays (MEAs).Rapid advances in implanting systems have allowed neuroscientists and
clinicians integrated neural record to treat neurological disorders, such as epilepsy, Parkinsons disease, and spinal
cord injuries. Large multichannel recording systems (e.g., [1]) are capable of observing many neurons
simultaneously. However, because thermal dissipation and wireless power delivery limitations constrain the total
allowable power dissipation, large arrays must limit the power consumption of each channel.
Recent advances in low-power low-noise CMOS bio potential amplifiers have been reported in [3][10].
The capacitive feedback approach proposed in [3] that uses capacitors to set the gain and to achieve dc offset
rejection has become the most popular topology in building bio potential amplifiers. Noise-power efficiency has
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Subharajit Jena &Ananya Dastidar

been further improved by employing current scaling [4] and current splitting [5] techniques in folded-cascade operational
trans-conductance amplifiers (OTAs). However, the severe current scaling scheme between the input differential pairs and
the folded branches requires that current errors caused by mirroring be well controlled. Additionally, the voltage headroom
required by the large source degeneration increases the minimum supply voltage.
An open-loop single-ended current-reuse complimentary input (CRCI) amplifier demonstrated very high power
efficiency but suffered from poor linearity and supply rejection. Because of the poor power supply rejection ratio (PSRR),
low-noise voltage regulation circuitry may be required, which consumes additional power and potentially increases the
design complexity. Recently, a closed-loop fully differential CRCI amplifier has been presented in [7], in which the PSRR
was greatly improved. However, at a given power budget, the input referred thermal noise power was twice that of the
single-ended amplifier because the output noise was doubled by the differential branches, which significantly degraded the
noise power efficiency.
This brief presents a two-stage amplifier configuration combined with CRCI technique and sharing architecture,
which achieves a very good power-noise tradeoff and adequate PSRR. The ac-coupled input rejects large dc offsets
generated at the electrodetissue interface. This brief is organized as follows. Section II describes the proposed architecture
and the design considerations, including the analysis of PSRR, noise optimization, and noise efficiency factor (NEF)
calculation. Section III presents the experimental results and biological recordings. Finally, Section IV concludes this brief.

2. NEURAL AMPLIFIER DESIGN

2.1 Overall System Design
Figure 1 shows the configuration of our proposed bio potential amplifier. The first-stage amplifier is a
single-ended CRCI amplifier with capacitive feedback, which achieves very high power-noise efficiency but poor PSRR.
In order to improve the PSRR, we employ a reference amplifier (shared by Nchannels) which is identical to the first stage.
The second stage is a fully differential OTA with capacitive feedback. The supply noise, which is equally coupled to the
outputs of the first stage and the reference, is suppressed as a common-mode signal by the second stage. The sharing
architecture of the reference amplifier results in a significant reduction of power dissipation. By using this approach, the
amplifier achieves good PSRR while keeping superior noise-power efficiency.

Figure 1: Configuration of the Proposed Bio Potential Amplifier

2.1.1 Closed Loop versus Open Loop Neural Amplifier
Many neuroscientists have proven that the information is essentially encoded in the spike time-stamps and
inter-spike intervals. Hence a small gain error due to processvoltagetemperature (PVT) variations is not detrimental to

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the information. Also the amplitude of the EAP is strongly dependent on the electrodeneuron distance which is not well
controlled. So having a highly deterministic gain in the neural amplifier does not really contribute. Typically an electrode
picks up signals from a number of neighboring neurons. These signals are discriminated using special algorithms known as
spike sorting algorithms. These algorithms use spike shapes to distinguish different neuronal sources and hence constrain
distortion that can be introduced by the amplifier. Pseudo-resistors show good linearity and large resistance for small
swings only. In feedback configuration, pseudo-resistor experiences larger signal swing across it and can cause more signal
distortion. Open loop amplifiers consume lower power than closed loop configurations for same accuracy requirements.
For same steady state error, an amplifier in closed loop configuration needs large open loop gain which requires more than
one stage in deep submicron technologies. It may also need compensation for stable operation.
Assuming that the first stage and the reference amplifier are perfectly matched, the ideal PSRR of the whole
amplifier can be expressed as
.

PSSR ideal =

= PSSR1 * CMRR2

(1)

Where Av1 is the signal gain of the first stage, As1 is the supply noise gain of the first stage, Av2 and Acm2 are the
differential mode gain and common-mode gain of the second stage, respectively, PSRR1 is the PSRR of the first stage, and
CMRR2 is the common-mode rejection ratio of the second stage.Taking the mismatch between the first stage and the
reference amplifier in to consideration, (1) can be modified as
PSSR =

(2)

Where As represents the supply noise gain mismatch between the first stage and the reference If the supply noise
gain mismatch (As) is sufficiently small, (2) can be reduced to (1). Using a similar approach, the CMRR of the whole
amplifier can be expressed as
CMRR =

(3)

Where Av1 represents the signal gain mismatch between the first stage and the reference
Assuming that the first stage and the reference amplifier are identical (I1 = IREF), the total current consumption
per channel can be expressed as
I total = 1 +

+ 2=

1+ 2

(4)

Where I1, IREF, and I2 represent the current consumption of the first stage, the reference amplifier, and the
second stage, respectively, while N is the number of channels. Considering that the first stage and the reference amplifier
are identical (v2ni1 = v2niREF) and the gain of the first stage Av1 is set to be sufficiently large, the input-referred noise power
of each amplifier can be calculated as
=

(5)

Where v2ni1, v2niREF, and v2ni2 represent the input-referred noise powers of the first stage, the reference amplifier,
and the second stage, respectively, while Av1 is the gain of the first stage

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Subharajit Jena &Ananya Dastidar

2.2 First-Stage Design

The schematic of the first-stage amplifier is shown in Figure 2. In order to reject the large dc offsets generated at
the electrodetissue interface, MOS-bipolar pseudo resistors with high resistances and on-chip capacitors are employed.
The incremental resistance of the pseudo resistors is extremely high (>100 G) when the voltage across it is small
(|V| <0.2 V). The open-loop single-ended CRCI amplifier can give superior noise performance for a given power budget
at the expense of reduced linearity and imprecise gain control. According to (2) and (3), the gain mismatch between the
first stage and the reference amplifier should be minimized to achieve good PSRR and CMRR. To improve gain accuracy
and linearity, capacitive feedback is used in the first stage and reference amplifier. The mid band gain Av1 of the first stage
amplifier is set by C1/Cf1. In order to achieve sufficient matching for the required PSRR and CMRR, the capacitors (C1
and Cf1) are large and carefully laid out, occupying 45% of the chip area in this design.

Figure 2: Schematic of the First Phase Amplifier

By driving the gates of both PMOS and NMOS input transistors, the CRCI technique reuses the current and
doubles the effective trans conductance, significantly reducing the input referred noise. Additionally, transistors MN1 and
MP1 are sized large enough to reduce the flicker noise to an acceptable level. The aspect ratios of MN1 and MP1 are
chosen for weak inversion operation in order to maximize gm/ID. Finally, the RC network formed by the pseudoresistor
and the ac-coupling capacitor at the gate of MP1 presents a low-pass characteristic to filter out most of the noise from the
current reference MP2 and the pseudo resistor PR1.
Assuming that thermal noise contribution is dominant, analysis of this circuit reveals that the input-referred noise
power of the first-stage amplifier can be expressed as

+!

+!
!

"

"

=!

"

"
"

"

# .

"

"
.

"

# .$
"

# . !'(
)-

%'(

%&

,%& )-

)-/

56

( )

( ) *

01 234
<
48 483
7
;
48 : 483

(6)

# .

( ) *

# . 4kTRpr+

=&

=( )

where gmn1, gmp1,2 are the trans conductance of the transistors MN1, MP1, and MP2, respectively, ron1 and
rop1 are the output resistances of the transistors MN1 and MP1, respectively, RPR represents the equivalent resistance of
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An Ultralow-Power Low-Noise CMOS Bio Amplifier for Neural Recording Application

47

the pseudo resistors, and is the reciprocal of the sub threshold slope factor np. The last two items in (6) represent the
noise contributions from the pseudo resistors and the current reference MP2, which are filtered by the pseudo resistor and
feedback capacitor. In order to minimize the noise contributions from the pseudo resistors and the current reference MP2,
long channel (L = 10 m) pseudo resistors are used to increase their equivalent resistance. Assuming that gmn1 = gmp1 =
gm and the noise contributions from the pseudo resistors and the current reference MP2 is negligible, (6) then reduces to

=!

"

"

"

# .!

=&

=(

(7)

Examination of (5) and (7) indicates that C1 /Cf1 should be large to minimize the input-referred noise of the first
stage and the noise contribution from the second stage.
2.3 Second-Stage Design
The schematic of the second-stage fully differential amplifier is shown in Figure 3. The circuit employs capacitive
feedback rather than resistive feedback to achievelow-noise operation. In the real design we have reduced the length and
width of each transistor used in the OTA The midland gain Av2 is set by the ratio of C2/Cf2. The MOSbipolar pseudo
resistors combined with the feedback capacitorsCf2 create a low-frequency high-pass corner.

Figure 3: Schematic of Second Stage Amplifier

Figure 4: Schematic of OTA

The schematic of the OTA is shown in Figure 3(b). The noise contribution from the second stage is v2ni2/A2v1,
where v2ni2 represents the input-referred noise power of the second stage and Av1 represents the gain of the first stage.
Since the noise contribution of the second stage is reduced by a factor of Av1, the noise performance of the second stage
can be sacrificed for ultralow-power operation. In order to reduce the flicker noise and achieve better matching, the
transistors are large. The input-referred thermal noise power of the second stage can be expressed as

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=>

,=&

= ( )

+ 16@AB

(63

+ 8@AB

(63

E.!

"

"

"

(8)

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Subharajit Jena &Ananya Dastidar

Where is the reciprocal of the sub threshold slope factor npand is the excess noise factor of the transistor in the
strong inversion regime ( = 2/3). Based on (8), the input pair transistors MP1 and MP2 are biased in weak inversion to
maximize gm/ID, while MN1 MN4, MP5, and MP6 are biased in strong inversion regime to minimize gm/ID. Assuming
that thermal noise is dominant and the noise of the second stage is negligible, from (5) and (7), the input-referred noise
power of the amplifier is expressed as

=!

"

"

# .$

"

%'(

,%&

( ) *

(9)

Since C1Cf1 and gmn1 = gmp1 = gm

=&

=(

(10)

To compare the power-noise tradeoff among amplifiers, the NEF is adopted

NEF = F

HK .

,-

IJI

LM .,=&.NO

(11)

Wherek is the Boltzmanns constant, UTis the thermal voltage, v

n i,rmsis

the total input referred noise, BW is the

3-dB bandwidth of the amplifier, and Itotis the total current consumption.Assumingthat the current consumed by the
second stage isnegligible (Itot [(N + 1)/N]ID), the the oretical NEF limit of our proposed architecture is derived as
NEF =

'

(12)

Where 1/(2) is the theoretical limit of the NEF for a single ended CRCI amplifier.
2.4 Class F Amplifier
Class-F amplifiers boost both efficiency and output by using harmonic resonators in the output network to shape
the output waveform into a square wave. Class-F amplifiers are capable of high efficiencies of more than 90% if infinite
harmonic tuning is used. Class F amplifiers resemble class E amplifiers, but use a more complex load network. In part, this
network improves the impedance match between the load and the switch. Moreover, its designed to eliminate the input
signals even harmonics so the switching signal is more nearly a square-wave. It improves efficiency because the switch
runs at saturation or cutoff for a longer period.

3. EXPERIMENTAL RESULTS

Figure 5: Schematic of First Stage Amplifie

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An Ultralow-Power Low-Noise CMOS Bio Amplifier for Neural Recording Application

49

Figure 6: Schematic of Class-F Amplifier

Table 1: Comparison of Existing and Propsedapproach
Model
EXISTING
PROPOSED

Power(Mw)
26.539
4.649

Gain(Db)
0.15
0.27

4. CONCLUSIONS
In this study, we have proposed a design strategy utilizing a CRCI topology and reference-sharing architecture,
which is suitable for implementing a neural recording amplifier array with ultralow-power low-noise operation.
The fabricated two-channel amplifier exhibited a low input-referred noise of 3.04 Vrms while consuming 2.85
W/channel from a 1-V supply, corresponding to a NEF of 1.93 The PSRR of at least 50 dB is sufficient for typical
recording scenarios. The NEF can be further improved when the reference amplifier is shared by more channels.
Additionally, the 1-V supply is well suited for integration with low-power digital circuitry in complex systems-on-chip.
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