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1
Service Pack 1
Release Notes
Copyright
Copyright 2005 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied, reproduced,
translated, or reduced to any electronic medium or machine-readable form without
prior written consent from Lattice Semiconductor Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L
(stylized), L (design), Lattice (design), LSC, E2CMOS, GAL, GDX, Generic Array
Logic, ISP, ispATE, ispCLOCK, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV,
ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLEVERCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA,
ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeXP, MACH, MachXO,
ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Silicon Forest, Speedlocked,
Speed Locking, SuperBIG, SuperCOOL, SuperFAST, SuperWIDE, sysCLOCK,
sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The Simple Machine for Complex
Design, TransFR, UltraMOS, XPIO, and specific product designations are either
registered trademarks or trademarks of Lattice Semiconductor Corporation or its
subsidiaries in the United States and/or other countries. ISP and Bringing the Best
Together are service marks of Lattice Semiconductor Corporation.
Other product names used in this publication are for identification purposes only and
may be trademarks of their respective companies.
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NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS AS IS
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Contents
Chapter 1
Preference Flow 2
Enhanced Documentation 2
Automatic Backup of Pre-5.1 Projects
Synthesis 2
Synplify 8.2H 2
Precision RTL Synthesis 2005b.91OEM
CPLD 4
Five-Volt Option for PCI and LVTTL I/O Types 4
Forced Fast Bypass 4
GLB Reservation for ispMACH 4000 4
CPLD Flow Tutorial on HDL Design with Precision RTL Synthesis
Chapter 2
Project Navigator 7
Error While Loading Shared Libraries
Floorplanner/Preference Editor 8
Assigning LOCATEs to ILVDS or OLVDS Fails 8
Cannot Drag Items from Pre-Mapped View to Floorplan View
Cannot Drag Items from Package View to Floorplan View 8
Floorplanner Loses LOCATE Preferences 9
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Contents
12
ispLeverDSP 13
RAM/ROM Blocks Cannot Support Data Greater Than 64 Bits 13
MATLAB Sees Algebraic Loop with RAM Blocks 13
Dual-Port RAM with Different Data Widths Have Same Data Rate 13
Parallel-to-Serial, Serial-to-Parallel Clock Enable from Testbench 14
Parameter Names of EBR and Distributed RAM/ROM Changed 14
Input Ports of EBR RAM/ROM and Distributed RAM/ROM Changed 14
FFT Compiler Does Not Work 15
Some DSP Elements Are Not Supported in Non-DSP FPGAs 15
Simulation Mismatch When Downsample Drives Parallel-to-Serial 15
Output of FIR Filter Incorrect for Four-Multiplier Design 15
FIR Filter Simulink Block Does Not Support Saturation Logic 16
Limit on Interpolation Factor 16
Map Design Process 16
False Undefined Property Warning 16
DRC Errors for Sub-module Connectivity Problems
17
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Contents
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Contents
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1
New Features and
Enhancements
Version 5.1 Service Pack 1 of the ispLEVER design tools provides a variety
of enhancements and fixes for the ispLEVER and synthesis software.
For updates to this software and documentation, run ispUPDATE. In
Windows, choose ispUPDATE from the Lattice Semiconductor program
group in the Windows Start menu. In UNIX and Linux, enter iupdate in a
command terminal. Or check the Lattice Semiconductor web site at
www.latticesemi.com/software.
Installation Requirements
The ispLEVER 5.1 Service Pack 1 software is in four parts:
Part 1 is required and must be installed first. Then either Part 2 or Part 3 is
required. You can install both Part 2 and Part 3, if you wish, in any order. You
must have ispLEVER 5.1 installed before installing Part 1.
Preference Flow
Preference Flow
Enhanced Documentation
To obtain a good understanding of the new preference flow in 5.1, begin with
the Preference Design Flow help topic located in FPGA Flow Help > Design
Implementation > Setting Preferences. This topic provides a good overview of
the updated preference flow and how it differs from the previous flow. You can
also reach this topic from the top-level of the help system.
Synthesis
Updates to the Synplicity Synplify synthesis software and the Mentor
Graphics Precision RTL Synthesis software are available for download after
you install the ispLEVER part of the service pack.
Synplify 8.2H
Synplify 8.2H adds RAM/ROM inferencing. Memory inference is supported by
block RAM (EBR) and distributed RAM. If the memory is 2 kilobits or more, it
is mapped into EBR. If the memory is less than 2 kilobits, distributed RAM is
used. The use of EBR or distributed RAM can also be specified with the
syn_ramstyle attribute (see below). Asynchronous read can only be mapped
to distributed RAM. For more information, see Inferring RAMs in Chapter 5,
Design Optimization, of the Synplify for Lattice User Guide.
True Dual Port RAM only supports one write and two read ports, and only
uses EBR.
Synthesis
Verilog
reg [7:0] dataout[31:0]
/* synthesis syn_ramstyle = "block_ram" */;
VHDL
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";
Verilog
reg [7:0] reg_shift
/* synthesis syn_srlstyle = "registers" */;
VHDL
attribute syn_srlstyle : string;
attribute syn_srlstyle of reg_shift : signal is "registers";
CPLD
CPLD
Five-Volt Option for PCI and LVTTL I/O Types
Two new options, PCI_5V and LVTTL_5V, were added to the I/O Types
constraint for the ispMACH 4000 and ispXPLD 5000MX device families.
You can assign these options to input pins via the Constraint Editor to achieve
5-V inputs for the PCI and LVTTL I/O standards. The software will assign each
5-V input to a bank that has a 3.3-V VCCO.
Note
Each device can support up to sixty-four 5-V inputs.
CPLD
CPLD
2
Known Issues and
Solutions
Following are issues and solutions known at the time of this release. If you do
not see your issue here, check the Lattice Semiconductor web site for a more
recent version of the release notes. Issues and solutions discovered after the
release are documented there.
Project Navigator
Error While Loading Shared Libraries
On Linux or UNIX, you may get the following error when you try to start
Project Navigator (ispgui):
ispgui &
projnav: error while loading shared libraries: liboleaut32.so:
cannot open shared object file: No such file or directory
Floorplanner/Preference Editor
Floorplanner/Preference Editor
Assigning LOCATEs to ILVDS or OLVDS Fails
If you instantiate ILVDS or OLVDS primitives in your design and assign
LOCATE's to these ports, Preference Editor or Floorplanner fails.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
If you use ILVDS or OLVDS primitives in your design, add your LOCATE
assignments with the Text Editor. In Project Navigator, select the device and
then double-click Edit Preferences (ASCII) in the Processes Window.
Otherwise, do not use the primitives and use HDL Attributes or Preference
Editor to set your LVDS settings.
Floorplanner/Preference Editor
Floorplanner/Preference Editor
Use the Preference Editors Spreadsheet Viewer to create CSV files. In the
Spreadsheet Viewer, choose File > Export and then choose the type of file.
10
Floorplanner/Preference Editor
Floorplanner Hangs
On the Linux platform, the Floorplanner hangs if it is already running and you
click Pre-Map Logical Design Floorplan, Post-Map Physical Design
Floorplan, or Post-PAR Design Floorplan in the Project Navigator to re-load
the design.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Close the existing Floorplanner application first.
Create the project in Project Navigator, import the source files, and then
run the Pre-Map Logical Design Floorplan process.
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ispLeverDSP
ispLeverDSP
These issues only apply to ispLEVER on Windows.
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ispLeverDSP
Currently, the RAM blocks are single rate. Designs using the dual-port RAM
with different data widths for the purpose of extracting or packing fields need
to up or down sample appropriately.
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ispLeverDSP
15
This issue is only seen for the four-multiplier design. Use other multipliers.
Map still writes the preference to the .prf file and par honors the constraint.
Device affected: LatticeECP-DSP
This warning message can be safely ignored.
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the bus has more than eight DQ data bits, so that a large portion of the
hardwired DQS bus in the device is expected to be occupied, or
the I/O bank has dedicated pins such as primary clock input pins.
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Synthesis
Synthesis
These issues only apply to ispLEVER on Windows.
For Verilog:
//exampler attribute result lattice_nomap_carry_chain true
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Synthesis
For example,
Module (In, In2, Out); /* synthesis syn_useioff=0 */
If necessary, you can also specify this for each output as follows:
Output out /* synthesis syn_useioff=0 */;
Use the Constraint Editor, at the Timing Constraints sheet, to set the
target Delay or Frequency.
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Synthesis
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Synthesis
Verilog Syntax
//pragma attribute name hierarchy preserve
For example:
module x
//pragma
//pragma
//pragma
(i,o,c);
attribute x hierarchy preserve
attribute x PGROUP modx
attribute x PBBOX 5,5
VHDL Syntax
attribute hierarchy : string;
attribute hierarchy of name: architecture is "preserve";
For example:
architecture x of CONTROLLER is
signal i : std_logic;
signal o : std_logic;
signal c : std_logic;
attribute PGROUP: string;
attribute PGROUP of x: architecture is "modx";
attribute hierarchy : string;
attribute hierarchy of x: architecture is "preserve";
attribute PBBOX: string;
attribute PBBOX of x: architecture is "5,5";
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Synthesis
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ispTRACY
ispTRACY
These issues only apply to ispLEVER on Windows.
Array types of two or more dimensions will not be shown in the port or
node section.
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ispTRACY
Generate statement
If function calls are used in the array declaration, the actual size of the
array will be unknown to the Core Linker.
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Documentation
Set INBUF = ON
Documentation
Memory Initialization Help Documentation
The Finding Instance Names for Memory Initialization topic is missing from
the online help in the FPGA Flow Help. Please refer to the documentation
below for instructions on finding instance names in the text version of an NCD
file for running memory initialization:
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Documentation
Take the following steps in finding instance names for memory initialization:
1. Take your physical design (.ncd) file and run NCDREAD on it to generate
a text file showing the contents of the design. See the Reading NCD
Files topic for more details on using this NCDREAD utility.
ncdread rom8x8.ncd -o rom8x8.out
In the above command line, an .ncd file named rom8x8 is used as input
for NCDREAD, outputting a text file called rom8x8.out.
2. Now, look in the rom8x8.out text file for the instance name using a text
editing tool to search on the word INITVAL in the Config String. When
you find an occurrence of INITVAL, look for the corresponding COMP
name in the line right above it as shown in the example below:
NC_COMP:20 - <TEST/rom8x8_0_0_0>, site = EBR_R10C6
See Also
Memory Initialization
26
The JTAGA element description does not illustrate the input pins TCK,
TMS, and TDI in the schematic diagram nor are they listed in the pinout in
Documentation
the documentation. The Test clock (TCK), Test mode select (TMS), and
Test data in (TDI) are standard interface pins for this element.
and
and
(A0
and
B0)
B2)
and
B2)
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