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ispLEVER 5.

1
Service Pack 1
Release Notes

Technical Support Line 1-800-LATTICE (528-8423) or 503-268-8001


Web Update To view the most current version of this document, go to
www.latticesemi.com/software.
December 2005

Copyright
Copyright 2005 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied, reproduced,
translated, or reduced to any electronic medium or machine-readable form without
prior written consent from Lattice Semiconductor Corporation.

Trademarks
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(stylized), L (design), Lattice (design), LSC, E2CMOS, GAL, GDX, Generic Array
Logic, ISP, ispATE, ispCLOCK, ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV,
ispGDX2, ispGENERATOR, ispJTAG, ispLEVER, ispLEVERCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP, ispXPGA,
ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeXP, MACH, MachXO,
ORCA, PAC, PAC-Designer, PAL, Performance Analyst, Silicon Forest, Speedlocked,
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Other product names used in this publication are for identification purposes only and
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ii

ispLEVER 5.1 Service Pack 1 Release Notes

Contents

Chapter 1

New Features and Enhancements


Installation Requirements

Preference Flow 2
Enhanced Documentation 2
Automatic Backup of Pre-5.1 Projects

Synthesis 2
Synplify 8.2H 2
Precision RTL Synthesis 2005b.91OEM

CPLD 4
Five-Volt Option for PCI and LVTTL I/O Types 4
Forced Fast Bypass 4
GLB Reservation for ispMACH 4000 4
CPLD Flow Tutorial on HDL Design with Precision RTL Synthesis
Chapter 2

Known Issues and Solutions

Project Navigator 7
Error While Loading Shared Libraries

Floorplanner/Preference Editor 8
Assigning LOCATEs to ILVDS or OLVDS Fails 8
Cannot Drag Items from Pre-Mapped View to Floorplan View
Cannot Drag Items from Package View to Floorplan View 8
Floorplanner Loses LOCATE Preferences 9

ispLEVER 5.1 Service Pack 1 Release Notes

iii

Contents

Floorplanner Copies UGROUP/PGROUP from HDL to LPF 9


PIO PGROUP Dialog Box Does Not Save Bank 9
Package View Does Not Create CSV 9
Pin Layout CSV Shows VCC, GND, VCCAUX, VCCPLL in Bank 0 10
Pin Layout CSV Shows VCC, GND, VCCAUX, VCCIO as Pin Names 10
DRC in Package View Is Grayed Out 10
Floorplanner Opens With My Documents Folder 10
Floorplanner Hangs 11
Stand-alone Floorplanner Does Not Open Database Design File 11
Floorplanner/Preference Editor Triggers Firewall Message 11
IPexpress and Module/IP Manager 12
IPExpress PLL GUI Fails in Divider Mode 12
Stand-Alone Module/IP Manager Does Not Load LPC 12
Cannot Import Module/IP Manager LPC Files Generated in 4.2 or 5.0

12

ispLeverDSP 13
RAM/ROM Blocks Cannot Support Data Greater Than 64 Bits 13
MATLAB Sees Algebraic Loop with RAM Blocks 13
Dual-Port RAM with Different Data Widths Have Same Data Rate 13
Parallel-to-Serial, Serial-to-Parallel Clock Enable from Testbench 14
Parameter Names of EBR and Distributed RAM/ROM Changed 14
Input Ports of EBR RAM/ROM and Distributed RAM/ROM Changed 14
FFT Compiler Does Not Work 15
Some DSP Elements Are Not Supported in Non-DSP FPGAs 15
Simulation Mismatch When Downsample Drives Parallel-to-Serial 15
Output of FIR Filter Incorrect for Four-Multiplier Design 15
FIR Filter Simulink Block Does Not Support Saturation Logic 16
Limit on Interpolation Factor 16
Map Design Process 16
False Undefined Property Warning 16
DRC Errors for Sub-module Connectivity Problems

17

Place and Route Design Process 17


DQS Bus Assignment Fails 17
Synthesis 18
Only Output Registers Are Mapped 18
Case and if-then-else Mapped to and-or Trees 18
Arithmetic Function Mapped to Carry-Chain 18
LOCK_SENSITIVITY Always LOW 19
DIN/DOUT Turned On by Default 19
Design Fixed In a Previous Version Fails In 5.1 19
Project Path with Space Causes m_att.exe Error 20
Mapping Fails with Exit Code 0002 20
Digital Line Detect Error with Synplify Synthesis 20
PGROUPs Disappear During Synthesis 21

iv

ispLEVER 5.1 Service Pack 1 Release Notes

Contents

Attributes preserve_driver and preserve_signal Fail 22


Lattice and Actel OEM Versions of Synplify Licenses Conflict 22
I/O Assistant Flow Does Not Work with Precision RTL Synthesis 23
ispTRACY 23
ispTRACY Core Requires Synplify Synthesis Tool 23
Unsupported VHDL and Verilog Features in ispTRACY IP Manager
Connecting VHDL Signals to ispTRACY Core 24
ispTRACY Requires ispVM to Run from Starter 24
SPI Option for CONFIG_MODE Not Recognized 25
SPI Flash Memory Fails to Boot FPGA 25
Documentation 25
Memory Initialization Help Documentation 25
FPGA Libraries Manual Documentation Errata 26
Problems in Displaying ispLEVER Help on MFCIE Browser

ispLEVER 5.1 Service Pack 1 Release Notes

23

27

Contents

vi

ispLEVER 5.1 Service Pack 1 Release Notes

1
New Features and
Enhancements

Version 5.1 Service Pack 1 of the ispLEVER design tools provides a variety
of enhancements and fixes for the ispLEVER and synthesis software.
For updates to this software and documentation, run ispUPDATE. In
Windows, choose ispUPDATE from the Lattice Semiconductor program
group in the Windows Start menu. In UNIX and Linux, enter iupdate in a
command terminal. Or check the Lattice Semiconductor web site at
www.latticesemi.com/software.

Installation Requirements
The ispLEVER 5.1 Service Pack 1 software is in four parts:

Part 1: ispLEVER software

Part 2: Mentor Graphics Precision RTL Synthesis software

Part 3: Synplicity Synplify synthesis software

Part 1 is required and must be installed first. Then either Part 2 or Part 3 is
required. You can install both Part 2 and Part 3, if you wish, in any order. You
must have ispLEVER 5.1 installed before installing Part 1.

ispLEVER 5.1 Service Pack 1 Release Notes

Preference Flow

New Features and Enhancements

Preference Flow
Enhanced Documentation
To obtain a good understanding of the new preference flow in 5.1, begin with
the Preference Design Flow help topic located in FPGA Flow Help > Design
Implementation > Setting Preferences. This topic provides a good overview of
the updated preference flow and how it differs from the previous flow. You can
also reach this topic from the top-level of the help system.

Automatic Backup of Pre-5.1 Projects


When you open a project that was created with a previous version of
ispLEVER, Project Navigator converts the project files to use the new
preference flow. Because the new files are not compatible with previous
versions of ispLEVER, Project Navigator opens a dialog box offering you the
option of creating a ZIP file containing all the original files.
If you might want to work on this project with the previous version of
ispLEVER, click Yes for the ZIP file option.

Synthesis
Updates to the Synplicity Synplify synthesis software and the Mentor
Graphics Precision RTL Synthesis software are available for download after
you install the ispLEVER part of the service pack.

Synplify 8.2H
Synplify 8.2H adds RAM/ROM inferencing. Memory inference is supported by
block RAM (EBR) and distributed RAM. If the memory is 2 kilobits or more, it
is mapped into EBR. If the memory is less than 2 kilobits, distributed RAM is
used. The use of EBR or distributed RAM can also be specified with the
syn_ramstyle attribute (see below). Asynchronous read can only be mapped
to distributed RAM. For more information, see Inferring RAMs in Chapter 5,
Design Optimization, of the Synplify for Lattice User Guide.
True Dual Port RAM only supports one write and two read ports, and only
uses EBR.

ispLEVER 5.1 Service Pack 1 Release Notes

New Features and Enhancements

Synthesis

Use the syn_ramstyle attribute to specify the type of inferred memories:


registers, block_ram, or distributed. For example:

Verilog
reg [7:0] dataout[31:0]
/* synthesis syn_ramstyle = "block_ram" */;

VHDL
attribute syn_ramstyle : string;
attribute syn_ramstyle of mem : signal is "block_ram";

For more information, see Chapter 7, Synthesis Attributes and Directives, of


the Synplify for Lattice Reference Manual.
Use the syn_srlstyle attribute to specify the type of inferred shift registers:
registers or distributed. By default, shift registers are inferred as a
counter plus distributed memory.
For example, to have shift registers inferred as registers:

Verilog
reg [7:0] reg_shift
/* synthesis syn_srlstyle = "registers" */;

VHDL
attribute syn_srlstyle : string;
attribute syn_srlstyle of reg_shift : signal is "registers";

Precision RTL Synthesis 2005b.91OEM


Precision RTL Synthesis 2005b.91OEM includes a variety of fixes and
enhancements.

ispLEVER 5.1 Service Pack 1 Release Notes

CPLD

New Features and Enhancements

CPLD
Five-Volt Option for PCI and LVTTL I/O Types
Two new options, PCI_5V and LVTTL_5V, were added to the I/O Types
constraint for the ispMACH 4000 and ispXPLD 5000MX device families.
You can assign these options to input pins via the Constraint Editor to achieve
5-V inputs for the PCI and LVTTL I/O standards. The software will assign each
5-V input to a bank that has a 3.3-V VCCO.
Note
Each device can support up to sixty-four 5-V inputs.

Forced Fast Bypass


A new optionForcedwas added to the Fast Bypass constraint to improve
timing performance. This option is available for output and bidirectional
signals on ispMACH 4000 devices. In this release, you can only specify it in
the Constraint Editor's Pin Attributes sheet.
When Forced Fast Bypass is specified, the Fitter places the signal on the fast
bypass path if the architecture permits, unlike the Fast Bypass option which
may be ignored during placement. Assigning this option to signals sometimes
may cause the fitting process to fail. It is suggested that you use this option
only when necessary to meet timing requirements.

GLB Reservation for ispMACH 4000


The Constraint Editor has been enhanced to support generic logic block
(GLB) reservation for the ispMACH 4000 device family. To reserve GLBs,
choose Device > Resource Reservation and select GLB in the Resource
Reservation dialog box.

ispLEVER 5.1 Service Pack 1 Release Notes

New Features and Enhancements

CPLD

CPLD Flow Tutorial on HDL Design with


Precision RTL Synthesis
This new tutorial shows you how to use the Mentor Graphics Precision RTL
Synthesis tool with ispLEVER to synthesize a Verilog HDL design and to
generate an EDIF file for a CPLD device. It is intended for designers who are
using Precision RTL Synthesis for the first time and who are looking for the
basic data and process flow from HDL source code to a fully implemented
CPLD.
To access this tutorial, go to the ispTOOLS\ispcpld\Tutorial directory and open
precision_cpld_tutor.pdf.

ispLEVER 5.1 Service Pack 1 Release Notes

CPLD

New Features and Enhancements

ispLEVER 5.1 Service Pack 1 Release Notes

2
Known Issues and
Solutions

Following are issues and solutions known at the time of this release. If you do
not see your issue here, check the Lattice Semiconductor web site for a more
recent version of the release notes. Issues and solutions discovered after the
release are documented there.

Project Navigator
Error While Loading Shared Libraries
On Linux or UNIX, you may get the following error when you try to start
Project Navigator (ispgui):
ispgui &
projnav: error while loading shared libraries: liboleaut32.so:
cannot open shared object file: No such file or directory

Devices affected: All


Unset environment variable MWCURRENT_LIBPATH before running Project
Navigator:
unsetenv MWCURRENT_LIBPATH

ispLEVER 5.1 Service Pack 1 Release Notes

Floorplanner/Preference Editor

Known Issues and Solutions

Floorplanner/Preference Editor
Assigning LOCATEs to ILVDS or OLVDS Fails
If you instantiate ILVDS or OLVDS primitives in your design and assign
LOCATE's to these ports, Preference Editor or Floorplanner fails.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
If you use ILVDS or OLVDS primitives in your design, add your LOCATE
assignments with the Text Editor. In Project Navigator, select the device and
then double-click Edit Preferences (ASCII) in the Processes Window.
Otherwise, do not use the primitives and use HDL Attributes or Preference
Editor to set your LVDS settings.

Cannot Drag Items from Pre-Mapped View to


Floorplan View
When you try to drag-and-drop an instance from the Pre-Mapped View to the
Floorplan View, nothing changes.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
This issue has no work-around.

Cannot Drag Items from Package View to


Floorplan View
When you try to drag-and-drop an instance from the Package View to the
Floorplan View, nothing changes.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
This issue has no work-around.

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Floorplanner/Preference Editor

Floorplanner Loses LOCATE Preferences


LOCATE preferences on blocks in the logical preference file are lost when a
PGROUP is edited in the pre-map or post-map Floorplanner.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Double-click Edit Preferences (ASCII) in the Processes Window and
manually add the LOCATE preferences again before running MAP.

Floorplanner Copies UGROUP/PGROUP from


HDL to LPF
When you save changes made in the pre-map or post-map Floorplanner,
UGROUP and PGROUP attributes defined in the HDL are written into the
logical preference file (LPF). If you later make changes to the UGROUP and
PGROUPs in the HDL, they will not have any affect because the LPF has
higher priority.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Double-click Edit Preferences (ASCII) in the Processes Window and
manually remove the undesired UGROUP and PGROUP attributes from the
LPF.

PIO PGROUP Dialog Box Does Not Save Bank


Bank assignments added using the PIO PGROUP Dialog Box in the pre-map
Preference Editor are not saved in the logical preference file.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
In the Preference Editor, assign a Bank for each of the ports in the PGROUP
using the Bank Column of the spreadsheet. You can also double-click Edit
Preferences (ASCII) in the Processes Window and manually add a Bank
preference to the PIO PGROUP. For example:
LOCATE PGROUP "test" BANK 2 ;

Package View Does Not Create CSV


The Preference Editors Package View fails to create CSV files.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO

ispLEVER 5.1 Service Pack 1 Release Notes

Floorplanner/Preference Editor

Known Issues and Solutions

Use the Preference Editors Spreadsheet Viewer to create CSV files. In the
Spreadsheet Viewer, choose File > Export and then choose the type of file.

Pin Layout CSV Shows VCC, GND, VCCAUX,


VCCPLL in Bank 0
In the pin layout CSV file, VCC, GND, VCCAUX, and VCCPLL pins are
incorrectly associated with Bank 0.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
You can edit the CSV file to delete the bank value.

Pin Layout CSV Shows VCC, GND, VCCAUX,


VCCIO as Pin Names
The pin layout CSV file may show VCC, GND, VCCAUX, and VCCIO as pin
names.
Devices affected: LatticeXP, MachXO
You can edit the CSV file to delete the affected row.

DRC in Package View Is Grayed Out


The Design Rule Check (DRC) in the Package View is grayed out and
unavailable.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Run DRC from the Floorplanner or the Preference Editor.

Floorplanner Opens With My Documents Folder


In Windows: When you click the Floorplanner button in the Project Navigator
toolbar, the My Documents folder opens instead of the current project folder.
Devices affected: ORCA 4, ispXPGA, LatticeECP/EC, LatticeXP, MachXO
Open the Floorplanner from the Project Navigator's Processes pane by
double-clicking one of the Floorplanner processes, such as Post-PAR Design
Floorplan.

10

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Floorplanner/Preference Editor

Floorplanner Hangs
On the Linux platform, the Floorplanner hangs if it is already running and you
click Pre-Map Logical Design Floorplan, Post-Map Physical Design
Floorplan, or Post-PAR Design Floorplan in the Project Navigator to re-load
the design.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Close the existing Floorplanner application first.

Stand-alone Floorplanner Does Not Open


Database Design File
The stand-alone Floorplanner does not open a pre-map database design file
(.ngd).
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
There are two work-arounds for this issue:

Create the project in Project Navigator, import the source files, and then
run the Pre-Map Logical Design Floorplan process.

Type the following command at the command prompt:


flmainapp -inp "<database>.ngd" -dir "<path>"
-prj "<project>" -a <architecture> -p <device> -t <package>
-lpf "<logical_preference_file>.lpf"
-msg "Pre-Map Design Floorplan"

Floorplanner/Preference Editor Triggers


Firewall Message
If you have a local software firewall on your machine and you try to invoke the
Floorplanner or Preference Editor, you see a message stating that this
program is attempting to access the Internet. This message is caused by the
IPC (inter-process communication) function used in these applications and
the way the local software firewall is configured.
Devices affected: ORCA 4, LatticeECP/EC, LatticeXP, MachXO
Configure the firewall so that the following executables are granted access
automatically: flmainapp.exe, flmainappw.exe, flmain_la.exe, prfEdit.exe,
javaw.exe.

ispLEVER 5.1 Service Pack 1 Release Notes

11

IPexpress and Module/IP Manager

Known Issues and Solutions

IPexpress and Module/IP Manager


IPExpress PLL GUI Fails in Divider Mode
The IPExpress PLL GUI in divider mode does not work when the CLKOS port
is not used and the optimal valid CLKOP divider setting is not a power of 2.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
Use frequency mode or manually edit the divider settings in the netlist.

Stand-Alone Module/IP Manager Does Not Load


LPC
When Module/IP Manager is run in stand-alone mode (that is, without Project
Navigator), it sometimes refuses to load an LPC, incorrectly giving the error
message:
You are loading a parameter file which targets a device family other than
the current one. Program will not be able to load the parameter file.
Devices affected: ORCA 4, ispXPGA, ispXPLD
Run Module/IP Manager from the ispLEVER Project Navigator. Choose Tools
> Module/IP Manager or click the Module/IP Manager button in the Project
Navigator toolbar. In the Module/IP Manager, choose File > Load LPC.

Cannot Import Module/IP Manager LPC Files


Generated in 4.2 or 5.0
The Module/IP Manager Lattice Parameter Configuration (LPC) files
generated in ispLEVER version 4.2 or 5.0 cannot be imported into ispLEVER
5.1 because the module parameters have changed.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
Regenerate the module in ispLEVER 5.1 IPexpress.

12

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

ispLeverDSP

ispLeverDSP
These issues only apply to ispLEVER on Windows.

RAM/ROM Blocks Cannot Support Data Greater


Than 64 Bits
RAM and ROM blocks do not support data widths greater than 64 bits.
Device affected: LatticeECP-DSP
This issue has no work-around. Please contact Lattice Semiconductor
Technical Support.

MATLAB Sees Algebraic Loop with RAM Blocks


It is possible to incorporate RAM blocks in designs where the output of the
block is used to determine an input to the same block. If there are no delay
elements (blocks with latency != 0) in this feedback path, MATLAB reports
an algebraic loop. This happens even though the RAM block has latency != 0.
Device affected: LatticeECP-DSP
Add a single delay block immediately after the RAM block and set the latency
= 1. Change the latency of the RAM block by -1. If the latency of the RAM
block is 0, the identification of an algebraic loop is correct, and the circuit
needs to be changed. Adding the delay block still works; however, in this
case, a needed delay is now added to the circuit. If the latency of the RAM
block was 1 and the memory is block memory, the memory needs to be
changed to distributed memory (so that the latency can be set to 0), and the
added delay block set to latency = 1.

Dual-Port RAM with Different Data Widths Have


Same Data Rate
In designs using multiple True Dual Port RAM or Pseudo Dual Port RAM
blocks with different port widths, all the blocks have the same output data rate
even though their input rates are different. The output is not always at the
expected sample rate.
Device affected: LatticeECP-DSP

ispLEVER 5.1 Service Pack 1 Release Notes

13

ispLeverDSP

Known Issues and Solutions

Currently, the RAM blocks are single rate. Designs using the dual-port RAM
with different data widths for the purpose of extracting or packing fields need
to up or down sample appropriately.

Parallel-to-Serial, Serial-to-Parallel Clock


Enable from Testbench
The clock enable signal for the Parallel-To-Serial and Serial-to-Parallel blocks
is coming from the testbench. This implementation is incorrect especially for
multi-rate designs. The clock enable must be generated within the design
itself and shouldn't be provided by an external source.
Device affected: LatticeECP-DSP
This issue has no work-around. Please contact Lattice Semiconductor
Technical Support.

Parameter Names of EBR and Distributed RAM/


ROM Changed
In 5.1, EBR RAM/ROM and Distributed RAM/ROM models have changed in
terms of internal parameter naming. When opening up a pre-5.1 design that
contains these blocks, you see warning messages displayed on the MATLAB
command prompt indicating a change in parameter names.
Device affected: LatticeECP-DSP
When opening up a pre-5.1 design, you might have to manually edit the
design around the RAM/ROM blocks.

Input Ports of EBR RAM/ROM and Distributed


RAM/ROM Changed
In 5.1, EBR RAM/ROM and Distributed RAM/ROM models have changed in
terms of input ports as some of them can now be optionally enabled/disabled.
By default these input ports are disabled.
Device affected: LatticeECP-DSP
When opening up a pre-5.1 design, you might have to manually edit the
design around the RAM/ROM blocks.

14

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

ispLeverDSP

FFT Compiler Does Not Work


The FFT Compiler IP core (Lattice Part No. FFT-COMP-EP-N1) is not
compatible with the new IPexpress flow.
Device affected: LatticeECP-DSP
Use ispLEVER 5.0 SP_01 Module/IP Manager to configure the FFT Compiler
IP core. Contact Lattice Semiconductor Technical Support for assistance.

Some DSP Elements Are Not Supported in


Non-DSP FPGAs
The DSP elements for MAC, multadd2, and multadd4 are not supported in
LUT logic.
Devices affected: LatticeEC, LatticeXP, MachXO
Do not use these DSP elements with non-DSP FPGAs.

Simulation Mismatch When Downsample Drives


Parallel-to-Serial
A MATLAB simulation mismatch may result if you drive a parallel-to-serial
block with a downsample block.
Devices affected: LatticeECP-DSP
This issue has no work-around. Please contact Lattice Semiconductor
Technical Support.

Output of FIR Filter Incorrect for Four-Multiplier


Design
When a FIR filter has the following configuration (a four-multiplier design), its
MATLAB simulation output is slightly different from what it should be:
1 ch, 4 mults, 16 tap, ifact=1, dfact=1, inp&coeff bitwidth=12 bits, inp
bin.pt=8 bits, coeff bin pt.=11 bits, output bits=25, outp bin pt.=19,
ram=EBR, input=signed, output=signed, perf=0, rounding=nearest,
saturation logic=off, coeff entry=matlab exp.
Devices affected: LatticeECP-DSP

ispLEVER 5.1 Service Pack 1 Release Notes

15

Map Design Process

Known Issues and Solutions

This issue is only seen for the four-multiplier design. Use other multipliers.

FIR Filter Simulink Block Does Not Support


Saturation Logic
The FIR filter Simulink block currently does not support saturation logic.
Devices affected: LatticeECP-DSP
As a work-around, use the convert block to saturate.

Limit on Interpolation Factor


The FIR filter currently does not support an arbitrary interpolation factor. The
interpolation factor only supports this configuration:
number_of_taps/(ifact* number_of_multipliers) >=1
Devices affected: LatticeECP-DSP
As a work-around, ensure that number_of_taps/(ifact* number_of_multipliers)
is greater than or equal to one.

Map Design Process


False Undefined Property Warning
If a preference is assigned to a DSP component, either in the preference file
or RTL code, map may issue a spurious warning message:
WARNING - map: <COMP_NAME> :property <PROPERTY_NAME> is
undefined and will be ignored.

Map still writes the preference to the .prf file and par honors the constraint.
Device affected: LatticeECP-DSP
This warning message can be safely ignored.

16

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Place and Route Design Process

DRC Errors for Sub-module Connectivity


Problems
In a block modular design, if sub-module ports (input or output) are declared
but left unconnected at the top level, logic connectivity problems may occur
during assembly phase. For example: if a module output is declared for a net
that is used inside a sub-module but the module output is not connected to
anything outside the sub-module, the internal sub-module connections for the
net may be incorrect. These issues show up as DRC errors when bitgen runs.
Devices affected: LatticeEC, LatticeXP
Sub-modules should only have declared ports that are used somewhere else
in the design. Change the input HDL so that unused module ports are
removed from both top and sub-module netlists.

Place and Route Design Process


DQS Bus Assignment Fails
For DDR designs, the placement of a DQS bus assigned to an I/O bank may
fail if either:

the bus has more than eight DQ data bits, so that a large portion of the
hardwired DQS bus in the device is expected to be occupied, or

the I/O bank has dedicated pins such as primary clock input pins.

Devices affected: LatticeECP/EC, LatticeXP


Either assign the DQS bus to other I/O banks using PGROUP to group the
DQ strobe/data bits and LOCATE PGROUP, or assign the dedicated pins to
other I/O banks using LOCATE preference.

ispLEVER 5.1 Service Pack 1 Release Notes

17

Synthesis

Known Issues and Solutions

Synthesis
These issues only apply to ispLEVER on Windows.

Only Output Registers Are Mapped


By default, in Synplify 8.2d, only the output register is mapped.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
Specify syn_ioff on the input port or on the register.

Case and if-then-else Mapped to and-or Trees


The case or if-then-else constructs sometimes are not mapped into 4-to-1
MUX, especially if the entry of the case or if-then-else clause is not of the
power of 2. These constructs get mapped into and-or trees, which may lead to
sub-optimal solution in the fitter.
Devices affected: ispGDX2
Use the Synplify synthesis tool.

Arithmetic Function Mapped to Carry-Chain


The arithmetic function may be mapped to use the carry-chain cell.
Devices affected: ispMach5000MX
Use the following attribute to turn on and off mapping of carry-chain:
For VHDL:
attribute lattice_nomap_carry_chain : boolean;
attribute lattice_nomap_carry_chain of result : signal is true;

For Verilog:
//exampler attribute result lattice_nomap_carry_chain true

Please note, only adder and counter are supported.

18

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Synthesis

LOCK_SENSITIVITY Always LOW


The DQSDLL attribute LOCK_SENSITIVITY is always LOW no matter how
the value is set.
Devices affected: LFXP20E/C, LFXP15E/C, LFXP10E/C, LFXP6E/C,
LFXP3E/C
This issue has no work-around.

DIN/DOUT Turned On by Default


By default, DIN/DOUT is mistakenly turned on for synthesis in the ispLEVER
5.1 release. As a result, the value for DIN/DOUT is always set in the Cell
Attribute Sheet when running the Pre-Map Preference Editor process. This is
an issue with the synthesis interface tool support that will be corrected in
future releases. This feature is normally turned off unless you specify it.
To turn off the DIN/DOUT attribute, specify the following in your top-level
module:
/* synthesis syn_useioff=0 */

For example,
Module (In, In2, Out); /* synthesis syn_useioff=0 */

If necessary, you can also specify this for each output as follows:
Output out /* synthesis syn_useioff=0 */;

Design Fixed In a Previous Version Fails In 5.1


The updated synthesis tool might cause a design that has been fixed in a
previous version to fail when recompiled in this version.
Devices affected: ispXPLD 5000MX, ispMACH4000, ispMACH 5000VG
There are three work-arounds for this issue:

Open the ispEXPLORER application. Choose Process > Start Process,


and click OK to create a new version of process runs for your design
using the default predefined settings. The software creates a separate run
for each of the predefined LCI files and displays a spreadsheet
comparison of results and settings.

Use the Constraint Editor, at the Timing Constraints sheet, to set the
target Delay or Frequency.

ispLEVER 5.1 Service Pack 1 Release Notes

19

Synthesis

Known Issues and Solutions

Use the Optimization Constraint Editor to adjust some of the constraints,


such as the following:
Max_pterm_collapse
Clock_enable_optimization
Fmax_logic_level
Logic_optimizaiton_effort
Fmax_fanin
Max_area
Xor_synthesis

Project Path with Space Causes m_att.exe Error


If the project path contains a blank space ( ) when you use Synplify as your
synthesis tool, the following error is generated:
Error Code <atmain.c:242 Can't open input file generic.srd>
@E: : | Internal Error in m_att.exe

Devices affected: All


Change the blank space in the path to an underscore (_).

Mapping Fails with Exit Code 0002


In Precision RTL Synthesis, the DPR16X2B primitive fails the mapper. In the
automake log you see:
Starting: 'C:\ispTOOLS5_1\ispfpga\bin\nt\ngdbuild.exe ...
Done: failed with exit code: 0002.

Devices affected: MachXO 1200 and 2280


Use Synplicity Synplify instead or call Lattice Semiconductor technical
support.

Digital Line Detect Error with Synplify Synthesis


When you use the Synplify tool, a Digital Line Detect error may occur on
some Dell computers.
Devices affected: All

20

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Synthesis

The following download from Dell is available to resolve this issue:


Communications: Conexant D480 MDC V.92 Modem, Windows 2000,
Windows XP, Multi Language, Multi System, v.1.14, A07.
The file, R82541.EXE, is available at:
support.dell.com/support/downloads/
format.aspx?releaseid=r82541&c=us&l=en&s=gen&cs=

PGROUPs Disappear During Synthesis


When using the Precision RTL Synthesis tool, PGROUP assignments might
not be passed to the logical preference file.
This is because the Precision RTL Synthesis logic optimization is flattening
the design hierarchy. To keep the PGROUPs, add the preserve hierarchy
attribute to each PGROUP module instance.

Verilog Syntax
//pragma attribute name hierarchy preserve

For example:
module x
//pragma
//pragma
//pragma

(i,o,c);
attribute x hierarchy preserve
attribute x PGROUP modx
attribute x PBBOX 5,5

VHDL Syntax
attribute hierarchy : string;
attribute hierarchy of name: architecture is "preserve";

For example:
architecture x of CONTROLLER is
signal i : std_logic;
signal o : std_logic;
signal c : std_logic;
attribute PGROUP: string;
attribute PGROUP of x: architecture is "modx";
attribute hierarchy : string;
attribute hierarchy of x: architecture is "preserve";
attribute PBBOX: string;
attribute PBBOX of x: architecture is "5,5";

ispLEVER 5.1 Service Pack 1 Release Notes

21

Synthesis

Known Issues and Solutions

Attributes preserve_driver and preserve_signal


Fail
The Precision RTL Synthesis attributes preserve_driver and preserve_signal
appear to not work, losing the assigned signals instead of preserving them.
Actually the attributes do work but Precision RTL Synthesis changes the
signal names during synthesis. The design works as intended but it can be
difficult to track the signals.
Devices affected: All
This issue has no work-around. Please contact Lattice Semiconductor
Technical Support.

Lattice and Actel OEM Versions of Synplify


Licenses Conflict
When you have both the Lattice OEM version of Synplify and the Actel OEM
version of Synplify installed, the Lattice OEM version of Synplify accesses the
Actel libraries. This causes the Lattice version of Synplify to fail.
Devices affected: All
Until Synplicity can correct this problem permanently, Lattice recommends the
following work-around:
1. Set the Actel license to the SYNPLICITY_LICENSE_FILE and invoke the
Synplify OEM application for Actel.
2. Set the Lattice license to the LM_LICENSE_FILE and rename
SYNPLICITY_LICENSE_FILE to xSYNPLICITY_LICENSE_FILE.
Here is an example of a renamed Synplicity environment variable:
Variable: xSYNPLICITY_LICENSE_FILE
Value: C:\license\license.txt
3. Invoke the Synplify OEM version for Lattice.
Each time that you want to run the Actel version of Synplify, set the
SYNPLICITY_LICENSE_FILE environment variable. Each time that you want
to run the Lattice version of Synplify, rename SYNPLICITY_LICENSE_FILE to
xSYNPLICITY_LICENSE_FILE.

22

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

ispTRACY

If the Actel version of Synplify is running, you can rename


SYNPLICITY_LICENSE_FILE, and the Actel version will continue running.
Then you can start Synplify for Lattice.
SYNPLICITY_LICENSE_FILE in the license.txt file only points to the Actel
OEM version of the Synplify FEATURE line (synplify_pc).

I/O Assistant Flow Does Not Work with


Precision RTL Synthesis
The I/O Assistant flow does not work with the Precision RTL Synthesis tool.
Devices affected: LatticeECP/EC, LatticeXP, MachXO
Use Synplicity Synplify instead.

ispTRACY
These issues only apply to ispLEVER on Windows.

ispTRACY Core Requires Synplify Synthesis


Tool
The ispTRACY modules are created by using the Synplify synthesis tool.
You must have Synplify installed to successfully generate the ispTRACY
modules for your design. This process is transparent to you and allows you to
continue using your favorite synthesis tool. It will not affect use of your
synthesis tool of choice.
Devices affected: LatticeECP/EC, LatticeXP, ispXPGA

Unsupported VHDL and Verilog Features in


ispTRACY IP Manager
Some features that are valid in VHDL and Verilog are not supported in the
ispTRACY IP Manager Core Linker.

Array types of two or more dimensions will not be shown in the port or
node section.

ispLEVER 5.1 Service Pack 1 Release Notes

23

ispTRACY

Known Issues and Solutions

Component instances instantiated in the following statements will not be


shown in the hierarchical design tree:

Generate statement

Conditional statement, such as an if-then-else statement

Selection statement, such as a case statement

If function calls are used in the array declaration, the actual size of the
array will be unknown to the Core Linker.

Entity and architecture of the same design cannot be in different files.

Devices affected: LatticeECP/EC, LatticeXP, ispXPGA


This issue has no work-around. Please contact Lattice Semiconductor
Technical Support.

Connecting VHDL Signals to ispTRACY Core


The types of inputs and outputs used in the ispTRACY IP Manager core
template restrict the types of signals or ports that can be used in VHDL
designs to connect to the ispTRACY IP core.
Devices affected: LatticeECP/EC, LatticeXP, ispXPGA
In VHDL designs, use only std_logic_vector and std_logic for the types
of signals or ports or their array to connect to the ispTRACY IP core.

ispTRACY Requires ispVM to Run from Starter


When the ispTRACY Logic Analyzer is accessed from ispLEVER 5.1 Starter
and a new project is created, the TCG file cannot be selected, even though it
resides in the proper folder.
Devices affected: LatticeEC, LatticeXP, ispXPGA
The ispTRACY software requires ispVM in order to run correctly, but the 5.1
Starter package does not include ispVM. Manually download ispVM from this
link:
www.latticesemi.com/products/devtools/software/
ispLEVER-features-ispvm.cfm
After downloading ispVM, copy the ispvmsystem directory under the installed
ispVM directory to the ispLEVER Starter package directory.

24

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Documentation

SPI Option for CONFIG_MODE Not Recognized


If you set the preference CONFIG_MODE = SPI, bitgen gives the following
error message:
ERROR - Unknown setting "SPI" for option "CONFIG_MODE"

Devices affected: LatticeECP/EC


In the logical preference file, set CONFIG_MODE = SPIX.

SPI Flash Memory Fails to Boot FPGA


After downloading a bitstream file into SPI flash memory, the SPI flash
memory fails to boot the FPGA when you toggle the PROGRAMN pin or cycle
the power. The DONE pin does not turn ON again.
Devices affected: LatticeECP/EC
This only occurs when the bitstream is generated with the default settings:
CONFIG_MODE = SLAVE_SERIAL, INBUF = OFF. In the logical preference
file, do one of the following:

Set INBUF = ON

Set CONFIG_MODE = SPIX

Documentation
Memory Initialization Help Documentation
The Finding Instance Names for Memory Initialization topic is missing from
the online help in the FPGA Flow Help. Please refer to the documentation
below for instructions on finding instance names in the text version of an NCD
file for running memory initialization:

Finding Instance Names for Memory Initialization


The Memory Initialization process or the memedit program requires that you
supply the instance names for given memories you are initializing. This topic
informs you how to obtain those instance names. To obtain the HDL instance
name of a given memory, use the NCDREAD program utility on your NCD file
to generate a text file containing those names. You must run this program
from the command line.

ispLEVER 5.1 Service Pack 1 Release Notes

25

Documentation

Known Issues and Solutions

Take the following steps in finding instance names for memory initialization:
1. Take your physical design (.ncd) file and run NCDREAD on it to generate
a text file showing the contents of the design. See the Reading NCD
Files topic for more details on using this NCDREAD utility.
ncdread rom8x8.ncd -o rom8x8.out

In the above command line, an .ncd file named rom8x8 is used as input
for NCDREAD, outputting a text file called rom8x8.out.
2. Now, look in the rom8x8.out text file for the instance name using a text
editing tool to search on the word INITVAL in the Config String. When
you find an occurrence of INITVAL, look for the corresponding COMP
name in the line right above it as shown in the example below:
NC_COMP:20 - <TEST/rom8x8_0_0_0>, site = EBR_R10C6

In the above COMP name, TEST is the instance name. The


rom8x8_0_0_0 value is generated during module generation and is based
upon how many EBRs this particular memory takes. So, if the memory
takes two EBRs, there will be two NC_COMPs with the name values of
TEST/rom8x8_0_0_0 and TEST/rom8x8_0_0_1. In this case, the
instance name would still be TEST. See the Sample Text-Converted NCD
File topic if you wish to test this search on INITVAL.
3. In Project Navigator, supply the instance name TEST in the Memory
Instance Name text box in the Memory Initialization process properties
dialog box and on the MEMEDIT command line. See Running MEMEDIT
from the Command Line.

See Also

Memory Initialization

Running MEMEDIT from the Command Line

Reading NCD Files

Sample Text-Converted NCD File

FPGA Libraries Manual Documentation Errata


The following information in the FPGA Libraries Manual will be corrected in
upcoming versions of the user documentation:

26

TIBUF is not supported for LatticeECP/EC devices. However, this element


is supported in the ORCA Series 3 and Series 4 architectures.

The JTAGA element description does not illustrate the input pins TCK,
TMS, and TDI in the schematic diagram nor are they listed in the pinout in

ispLEVER 5.1 Service Pack 1 Release Notes

Known Issues and Solutions

Documentation

the documentation. The Test clock (TCK), Test mode select (TMS), and
Test data in (TDI) are standard interface pins for this element.

The MULT2 element equations are incorrect in the documentation. The


equations for the MULT2 elements should read as follows:
P0 = (A0
P1 = (A2
CO_int =
CO = (A2

and
and
(A0
and

B0)
B2)
and
B2)

XOR (A1 and B1) XOR CI;


XOR (A3 and B3) XOR CO_int;
B0) or (A1 and B1) or CI;
or ( A3 and B3) or CO_int;

Problems in Displaying ispLEVER Help on


MFCIE Browser
In UNIX and Linux: The ispLEVER software online help may not display
properly in using the default MFCIE 1.0 web browser. These intermittent
problems can include freezing up, crashing, or displaying graphics poorly.
Also, if you use the web browser to view the Lattice Semiconductor web site,
some advanced features, such as Flash demonstrations, do not work.
If necessary, view the ispLEVER online help using a full-featured web
browser, such as Netscape or Mozilla. Using a full-featured browser, navigate
to the following HTML file in your ispLEVER software installation:
<install_path>/isptools/ispcpld/webhelp/main.htm.

Click the desired help subject.

ispLEVER 5.1 Service Pack 1 Release Notes

27

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