Fall

2016 EE477L Lab 1

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Part 1: Due on September 8 (Thursday) 11:59 pm

Notes:

The goal of Lab1 is to design some basic gates and circuits that you will use in future assignments
and the final project.
This assignment is based on individual work. No collaboration is allowed.
Your lab report must be a single pdf file. Submit electronically to Blackboard Assignments
Lab1PartX (X = 1,2,3)
Use Cadence Virtuoso for all designs
Vdd = 1.8V, Gnd = 0V
Rise time and fall time for all input stimuli = 100 ps
Answers to the questions in italics are not required. But do try to solve them J

Part 1: Schematic Design and Propagation Delay Calculation

of Minimum Sized CMOS Gates and Logic Cells

Introduction:

The propagation delay of a circuit (ckt) is defined as the time from when an input voltage waveform
crosses 0.5Vdd to the time an output voltage waveform crosses 0.5Vdd. The propagation delay for a rising
output (0 to Vdd transition) is simply referred to as the rising delay (PLH) and the propagation delay for a
falling output (Vdd to 0 transition) is simply referred to as the falling delay (PHL). The propagation delays
of a circuit depend on its output (capacitive) load, because the charging and discharging time of the load
will affect the delay of rising and falling output, respectively.

The circuit being examined is called Design Under Test (DUT). To measure its delay, we use the FO4 (fanout
of 4) metric. FO4 is a technology independent metric to measure the delay of a circuit when Cload/Cin = 4,
i.e., the circuit drives 4 of its copies. Also, an inverter is connected to every input of the DUT. This is to
shape the input waveform and make it more realistic.
Can we use a buffer instead of an inverter??



Ckt X (Load)


Ckt X (Load)

Cadence

Ideal Input
Ckt X (DUT)

Waveforms
Ckt X (Load)



Ckt X (Load)

Steps:
1. Draw the schematic of these basic gates: An inverter, a 2-input NAND and a 2-input NOR. Use
minimum NMOS and PMOS width (i.e., WNMOS = WPMOS = 300 nm). Create symbols for these gates.
2. Use the NAND gates to draw the schematic of a 2-to-1 MUX circuit. Assume both Select (S) and its
complement (~S) inputs are available (i.e. no need to use inverter). Create a symbol for the MUX.
3. Using their symbols, draw the FO4 schematic for all the designs Inverter, NAND, NOR, MUX.
4. Perform transient analysis and measure the rising and falling delays of these circuits.
For the basic gates, you need to consider every possible input combination which can cause
a particular transition. For example, for the falling delay of a 2-input NAND, you should
separately test the 2 cases that may cause the output to go from 1 to 0: inputs go from 01 to
11, and inputs go from 00 to 11.
For MUX, you only need to measure the delays from the 2 data inputs to the output (delay
from S to output is not required). Do this one by one. In the MUX DUT, dont give any input
to S and ~S, just connect one of them to Vdd and the other to Gnd. After 1 data input is done,
switch S and ~S.
o Why dont we give inputs to S and ~S??

Take Cares:
DUT and load gates must always be the same
For the basic gates:
o For a 2 input gate, connect the output pin of the DUT to the 1st input pin (A) of all loads
o The other input pin (B) of the load is connected to Vdd for NAND and Gnd for NOR
Why are they connected like this??
For the load MUXes:
o Connect the output pin of the DUT to data input pin A of all loads
o Connect data input pin B of the loads to either Vdd or Gnd
Does it matter??
o Connect S and ~S of the loads such that data input A is always selected. Accordingly, keep
one always connected to Vdd and the other always to Gnd.
S and ~S in any MUX must always be complement of each other (E.g. S = ~S = 0 is not permitted)
o Then why do we have separate signals for S and ~S??
Each DUT input from which delay is measured must have an inverter before it.
Set the Cadence ideal inputs carefully as the inverters will invert it before propagating to the DUT.

Report should include:

Screenshot of the schematic view for all circuits obtained in Steps 1 and 2.
Screenshot of the FO4 transient analysis waveforms for all circuits obtained ins Steps 3 and 4.
Each screenshot should show all the input and output waveforms for the DUT and how you
calculate delay.
A table summarizing the rising and falling delays for all circuits.
Reports should be named EE477_Lab1P1_Username_USCID.pdf