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Inverter
Buffer
Undetermined behavior
High impedence
6) What is the propagation delay for the following transition, i.e. low to
high, at the output of CMOS inverter (same size PMOS & NMOS
transistors) with following parameters:
Req (PMOS) = 1 kohm
Req (NMOS) = 400 ohm
CL = 29pf
Tp(LH) = ?
d.
e.
f.
g.
25 ns
29 ns
20 ns
10ns
8) Ring counter's initial state is 1000. After how many clock cycles will
it return to the initial state?
a. 5
b. 6
c. 4
d. 3
9) 2:1 mux can be converted into 2-input OR gate without any additional
logic gate by how many methods:
a.
b.
c.
d.
Not possible
1 method
2 methods
3 methods
B0
1
0
B1
0
B2
0
1
1
B3
1
B4
a.
b.
c.
d.
10101
01110
10110
00110
18) In the following circuit, what would be the max. frequency that can
be achieved using the following parameters:
Tsetup = 10 ns [D-ff setup time]
Td1 = 15 ns [ Delay for combinational logic1]
Td2 = 20 ns [Delay for combinational logic2]
Thold = 1 ns [D-ff hold time]
Tdff = 20 ns [D-ff clock to data propagation delay]
a. 10 MHz.
b. 25 MHz.
c. 20 MHz.
d. 15 MHz.
1b0
1b1
1bz
None
Buffer
Tri-state Buffer
Mux
Decoder
26) What would be the final decimal value of the register Q_Val in the
following verilog code:
Verilog Code:
module ValCal();
integer i; reg clk; reg [7:0] Q_Val;
initial begin
clk = 0;
Q_Val = 15;
#2 $finish;
end
always #1 clk = !clk;
always @ (posedge clk)
begin : FOR_OUT
for (i=0; i < 8; i = i + 1) begin
if (i == 5) begin
disable FOR_OUT;
end
Q_Val = Q_Val << 1;
$display ("Time = %g, Value of Q_Val = %d, i = %d", $time, Q_Val, i);
end
end
endmodule
a.
b.
c.
d.
240
440
224
200
28) Is the following VHDL code is a valid code? If there is an error, which
section/sections contains the error?
VHDL Code:
ENTITY andgate IS
PORT ( a : IN std_logic;
b : IN std_logic;
c : OUT std_logic );
END andgate;
ARCHITECTURE synthesis1 OF andgate IS
BEGIN
c <= a && b;
END synthesis1;
a.
b.
c.
d.
ENTITY Section
ARCHITECTURE Section
Both the Sections
No error