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VLSI Question Paper


1) Which is preferably used in VLSI implementation?
a. NAND gate
b. NOR gate
c. Both equally
d. None
2) In CMOS circuits, what happens to delay when we increase the load
capacitance?
a. Increase
b. Decrease
c. No effect
3) What happens when the PMOS and NMOS are interchanged with one
another in a CMOS inverter? It works like:
a.
b.
c.
d.

Inverter
Buffer
Undetermined behavior
High impedence

4) To obtain symmetrical CMOS inverter characteristics, what should be


PMOS & NMOS size:
a. PMOS bigger, NMOS smaller
b. PMOS smaller, NMOS bigger
c. Equal size
5) A transmission gate is comprises of:
a. PMOS & NMOS both
b. PMOS only
c. NMOS only
d. None of PMOS & NMOS

6) What is the propagation delay for the following transition, i.e. low to
high, at the output of CMOS inverter (same size PMOS & NMOS
transistors) with following parameters:
Req (PMOS) = 1 kohm
Req (NMOS) = 400 ohm
CL = 29pf
Tp(LH) = ?

d.
e.
f.
g.

25 ns
29 ns
20 ns
10ns

7) How many flip flops you require for modulo 19 counter?


a. 4
b. 7
c. 5
d. 9

8) Ring counter's initial state is 1000. After how many clock cycles will
it return to the initial state?
a. 5
b. 6
c. 4
d. 3
9) 2:1 mux can be converted into 2-input OR gate without any additional
logic gate by how many methods:

a.
b.
c.
d.

Not possible
1 method
2 methods
3 methods

10) In regards to number of gates to implement latches & flip flop:


a. Latches takes less gates than FF.
b. FF takes less gates than Latches
c. Both takes equal number of gates.
11) D flip flop can be created using 2 latches and a NOT gate:
a. True
b. False
12) If the inverted o/p of the D FF is connected to its input how this flipflop will behave as clock frequency:
a. Divider
b. Multiplier
c. Comparator
d. Adder
13) At high speed circuits, we require steady output for the whole clock
period. For this we must use:
a. Mealy FSM
b. Moore FSM
c. Both
d. None

14) Glitches are part of following Finite State Machine (FSM)?


a. Mealy FSM
b. Moore FSM
c. Both
d. None
15) Following state diagram shows the sequence detection for which
sequence:
reset

B0
1
0

B1

0
B2
0

1
1

B3
1
B4
a.
b.
c.
d.

10101
01110
10110
00110

16)Out of the following buses which can NOT be a bi-directional bus:


a. Data Bus
b. Address Bus
c. Set of Control signals
17) MESI protocol is used for:
a. Implementing Virtual memory
b. Cache Coherency
c. DMA
d. Pipelining

18) In the following circuit, what would be the max. frequency that can
be achieved using the following parameters:
Tsetup = 10 ns [D-ff setup time]
Td1 = 15 ns [ Delay for combinational logic1]
Td2 = 20 ns [Delay for combinational logic2]
Thold = 1 ns [D-ff hold time]
Tdff = 20 ns [D-ff clock to data propagation delay]

a. 10 MHz.
b. 25 MHz.
c. 20 MHz.
d. 15 MHz.

19) The 32 bit value 0x30a79847 is stored to the location 0x1000 in a


byte addressable system. What is the value of the byte in address
0x1002 if the system is big endian?
a. 0x30
b. 0xa7
c. 0x98
d. 0x47
20) Stack operation in computer architecture is based on:
a. FIFO
b. LIFO
c. Either one can be used
d. None
21) Snooping is a process related to:
a. Virtual memory
b. Stack
c. Cache Coherency
d. Pipelining
22) In the following two example codes, z is assigned to value 20 after
how many time units:
Example1:
initial begin
#10 x = 10;
#15 y = 15;
#20 z = 20;
end
Example2:
initial begin
#10 x <= 10;
#15 y <= 15;
#20 z <= 20;
end
a.
b.
c.
d.

Example1 : 20 time units, Example2: 20 time units


Example1 : 45 time units, Example2: 45 time units
Example1 : 45 time units, Example2: 20 time units
Example1 : 20 time units, Example2: 45 time units

23) What is the final value of d in the following example:


Verilog Code:
initial
begin
b = 1'b1; c = 1'b0;
#10 b = 1'b0;
end
initial
begin
d = #25 (b | c);
end
a.
b.
c.
d.

1b0
1b1
1bz
None

24) Following verilog code would implement?


Verilog Code:
module LogicImpl();
reg data_in, enable;
wire pad;
assign pad = enable ? data_in : 1bz;
endmodule
a.
b.
c.
d.

Buffer
Tri-state Buffer
Mux
Decoder

25) In Verilog, blocking & non-blocking assignments are type of:


a. Procedural assignments
b. Continuous assignments
c. Both
d. None

26) What would be the final decimal value of the register Q_Val in the
following verilog code:
Verilog Code:
module ValCal();
integer i; reg clk; reg [7:0] Q_Val;
initial begin
clk = 0;
Q_Val = 15;
#2 $finish;
end
always #1 clk = !clk;
always @ (posedge clk)
begin : FOR_OUT
for (i=0; i < 8; i = i + 1) begin
if (i == 5) begin
disable FOR_OUT;
end
Q_Val = Q_Val << 1;
$display ("Time = %g, Value of Q_Val = %d, i = %d", $time, Q_Val, i);
end
end
endmodule
a.
b.
c.
d.

240
440
224
200

27) In VHDL, One entity can be assigned to how many architecture?


a. One
b. Two
c. Three
d. Numerous

28) Is the following VHDL code is a valid code? If there is an error, which
section/sections contains the error?
VHDL Code:
ENTITY andgate IS
PORT ( a : IN std_logic;
b : IN std_logic;
c : OUT std_logic );
END andgate;
ARCHITECTURE synthesis1 OF andgate IS
BEGIN
c <= a && b;
END synthesis1;
a.
b.
c.
d.

ENTITY Section
ARCHITECTURE Section
Both the Sections
No error

29) In VHDL, an entity must be terminated with following clause?


a. end <entity_name>
b. endentity;
c. end <entity_name>;
d. none
30) In VHDL, set of states of an Finite State Machine (FSM) is usually
declared by :
a. Enumeration Type
b. Integer Type
c. Scalar Type
d. All of the above

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