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sjtece@tce.edu
I. INTRODUCTION
Long Term Evolution (LTE) is a Fourth generation
wireless broadband technology, which is capable of providing
high peak data rates (100 Mbps downlink and 50 Mbps
uplink),multi antenna support, reduced cost, wide range of
bandwidth(from 1.4 MHZ upto 20 MHZ),backward
compatibility with existing 2G and 3G networks, increased
spectrum efficiency and peak data rates at cell edges[1-3]. All
these criteria are satisfied by the efficient usage of the control
channels. The LTE physical layer is a highly efficient means
of conveying both data and control information between an
enhanced base station(e-Node B) and mobile user
equipment(UE). The LTE physical layer uses OFDM as the
access technology, QAM as the modulation scheme and
MIMO concepts. LTE differs from its predecessors by using
OFDM along with MIMO antennas. OFDM is selected ,owing
to its suitability for MIMO transmission and reception,
resistance of its symbol structure to multi path delay spread,
no need of equalization etc[4].
The downlink physical channels correspond to a set of
resource elements carrying information originating from the
higher layers. There are six physical downlink channels
available namely, Physical Downlink Shared Channel
(PDSCH), Physical Broadcast Channel(PBCH), Physical
Multicast Channel (PMCH), Physical Control Format
Indicator Channel (PCFICH), Physical Downlink Control
Channel (PDCCH), Physical Hybrid ARQ Indicator
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19
IEEE-ICRTIT 2011
be optimized using VLSI DSP techniques of Folding,
Unfolding, Retiming etc.
The rest of the paper is organized as follows. In Section II,
a brief discussion of PCFICH channel is done, followed by
block diagram and modelling of the transmitter and receiver
architecture is done. In Section III, assumptions are provided
and the architectures for the PCFICH transmitter and receiver
are proposed. Section IV, provides the simulation results and
discussion. Section V, contains some concluding remarks.
II. PHYSICAL CONTROL FORMAT INDICATOR CHANNEL
The PCFICH carries the information of number of
OFDM symbols used by the PDCCH to carry the scheduling
assignments and other control information. The information
carried by the PCFICH is called as Control Format Indicator
(CFI) and is located in the first OFDM symbol of each
subframe. The CFI can take the values of 1,2,3 and
4(Reserved) and are represented using two bits. For
bandwidths greater than ten resource blocks, number of
OFDM symbols used to contain the downlink control
information is the same as the actual CFI value. Otherwise
span of the downlink control information is CFI+1 symbols.
The exact position of CFI in the resource grid is based on the
bandwidth and physical layer cell identity. The CFI is the first
information received by the user equipment and so the overall
performance depends on the correctness of CFI detection.
CFI
Transmitter
Block Coding
Scrambling
Mapping to RE
Pre coding
QPSK
Modulation
A. PCFICH Transmitter
1) Block Coding: The original CFI value to be transmitted
is first represented in two bit format R1,R0 (01-->1,10-->2,11->3).The CFI is first encoded using a (32,2) block code, as
shown in TABLE I. The dmin between the code words is 21[5]. In
order to ensure high robustness, PCFICH use this type of
encoding.
TABLE I
CFI (32,2) Block Code
CFI
1
2
3
4
(Reserved)
Layer Mapping
~ (q )
b
Channel
CFI
Demapping
from RE
Decoding
ML Detection
Delayer
mapping
(i ) = (b (q ) (i ) + c (q ) (i ))mod 2 (1)
Receiver
59
b(i),b(i+1)
00
01
10
11
CFI = min
m =1, 2,3
k =1
which simplifies to
CFI = arg max z (m )
2
2
.. .
(6)
...
(7)
m =1, 2,3
z (m ) =
z(
m)
k
for m=1,2,3.
...
(8)
k =1
Which is simplified as
Re{ y
K
m =1, 2,3 k =1
B. PCFICH Receiver
1)Received Signal: In the receiver side, after removal of
cyclic prefix from the received signal, then FFT is performed
and then resource element de mapping is done. The complex
valued output at the k -th receive antenna is modelled in
eqn.(5)
k = 1,2,!, K
(5)
y k = hk d ( n ) + u k ,
where, y k is 16x1 received subcarrier vector, d (n ) is the 16x1
complex QPSK symbol vector corresponding to the 32- bit
CFI code words, where n varies from 1 to 3, hk is 16x1
complex channel frequency response and u k represents the
contribution of thermal noise and interference. The received
signal y k is represented in the Fig. 2,for single antenna case.
The noise term u k is modelled as zero mean circularly
symmetric
complex
Gaussian
with
covariance
E u k u kH = u2 I , since the interferers are uncorrelated due to
independent large scale propagation, short term fading and
uncorrelated scrambling sequences.
y k hk d (m )
60
*
(m )
k hk , d
...
(9)
x, y =
x y
i
*
i .The
i =1
Parameter
Channel Bandwidth (MHz)
Number of Physical Resource
Blocks
Sampling Frequency(Msps)
Number of occupied subcarriers
Cyclic Prefix
Number of OFDM symbols per sub
frame
Frame Structure
CFI(bits)
Gold Sequence(bits)
dmin between CFI code words (bits)
Modulated Symbol(bits)
Channel
channel
frequency
response
vector(hk)
Conjugate of channel frequency
response vector(hk*)
Noise vector(uk)
Assumption
1.4
6
1.92
73
Normal
14 (7 in each slot)
Type I(FDD)
2
32
21
16
Rayleigh fading
16 bit 16X1 vector
16 bit 16X1 vector
16 bit 16X1 vector
IEEE-ICRTIT 2011
A. Transmitter Architecture
Z1
STA1
R1
Z2
R0
X1
Re + j Im
Change (-j)
STA4
X2
STA3
Z3
Re + j Im
Change (-Re)
STA2
SFA1
Z4
Re + j Im
Change (-j)
Z5
Re + j Im
Change (-Re)
SFA7
SFA5
SFA3
..
SFA10
29
Z6
30
31
31
Re + j Im
Change (-j)
SFA16
31
SFA14
Z7
Re + j Im
Change (-Re)
SFA11
hk
31
30
..
..
..
..
Precoding
1 2 + j1 2
1 2 j1 2
1 2 + j 1 2
14
14
1 2 j 1 2
15
15
Frame
Slots
Memory buffers to store
7
15
14
...
31
30
...
16 QPSK sym.
yk
31
Layer
mapping
30
...
Z1
00-1ant
Z2,Z3
01-2ant
Z4,Z5,Z6,Z7
10-4ant
Parallel to
Serial
IFFT
Cyclic
Prefix
M
U
X
61
are done using Verilog HDL. The simulation results and the
device utilization summary, assuming that the channel
response is known are presented in this section.
Decoding
Z1
From
Resource
grids
Re+jim
Change(j)
Error
detection
Change(j)
Error
detection
Z3
Re+jim
Change(j)
Error
detection
Z4
Re+jim
Re+jim
Change(j)
Error
detection
Re+jim
Change(j)
Error
detection
Re+jim
Change(j)
Error
detection
z4,z5,z6,z7 z2,z3
R1
B. Receiver Architecture
The received signal is first demapped from the resource
elements in the grid. Only in 16 positions of first OFDM
symbol, CFI value is available. Decoding is done to get the
original symbols, by selecting the strongest signals. The
delayer mapping is just retrieving back the 16 symbols in
order. The receiver architecture is presented in Fig. 5. The 16
received signals are used to estimate the CFI value
transmitted. It is known that, there are only three possibilities
of signal transmitted, namely 01,10 or 11(CFI-1,2 or 3).So,
the demodulated signal will be one among the three, which is
used in the estimation of the CFI, by finding argument
maximum among three results. The received signal is yk and is
multiplied with the conjugate of the complex channel
frequency response vector hk*, element by element. Then this
resultant term undergoes inner product with the three possible
values of d(m). The three possible values are produced in the
same way as in the transmitter side. The inner product is done
using the formula in section II. The d(m)* is multiplied with
(yko hk*) product. For all the elements the multiplication is
done and the results are accumulated, and the result is a 64 bit
value. The real part of the accumulated value alone is taken,
which is a 32 bit value. This process is done for the three
values viz. d(0),d(1), d(2).Then among the three results, the
codeword which has the maximum argument value is detected
as the CFI.
R0
{}
Z7
z1
DeLayer
Mapping
{}
16 symb.
.
..
.
29
30
31
hk*
..
..
..
..
30
14
31
15
31
47
.. 1
46
d(m)*
31
30
0
1
2 + j1
2 j1
2 + j1
2 j1
..
..
MAC
14
Re| |
15
1
CFI 1
..
..
CFI 2
CFI 3
30
01
CFI
10
11
Count no.of
error bits and
find
minimum
error output
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Z6
yk
Z5
ctrl
31
Z2
o/p 1
o/p 2
o/p 3
31
IEEE-ICRTIT 2011
For the transmitter side, the inputs are clock and the two bit
CFI value (01,10 or 11). In fig.6,two bit CFI input is given.
Number of slices
616 /9312 ( 6% )
714 / 9312 (7% )
59.830MHz
16.714ns
143284 kilobytes
TABLE V
FPGA RESOURCE UTILIZATION SUMMARY FOR PCFICH RECEIVER FOR THE
XILINX SPARTAN 3E ,3S500EFT256-4 DEVICE
Number of Slices
Number of Slice Flip Flops
Number of 4 input LUTs
Number of MULT18X18SIOs
Max.Frequency
Delay(Min.period)
Total memory usage
63
[2]
[3]
[4]
[5]
3GPP TS36.211,Evolved Universal Terrestrial Radio Access(EUTRA);Physical Channels and Modlation(Release 8).
3GPP TS36.212,Evolved Universal Terrestrial Radio Access(EUTRA);Multiplexing and Channel Coding(Release 8).
3GPP TS36.306,Evolved Universal Terrestrial Radio Access(EUTRA);User Equipment radio access capabilities (Release 8).
S. J. Thiruvengadam, Louay M. A. Jalloul, Performance Analyis of the
3GPP-LTE Physical Control Channels, EURASIP Journal onWireless
Communications and Networking,vol.2010,Article ID 914934, 10
pages,Nov.2010
R.Love, R.Kuchibhotla, A.Ghosh et al.,Downlink control channel
design for 3GPP LTE, in proceedings of IEEE wireless
communication and Networking Conference(WCNC08),pp.813818,Las Vegas, Nev, USA ,April 2008